Operating Systems

Memory management PART2

Non-Contiguous Memory management scheme

Paging and Segmentation

1
 Overview

• Paging
• Page Tables
• TLB
• Hierarchical Pages
• Hashed Pages
• Inverted Pages
• Segmentation

2
 Address Translation
Scheme
■ Address generated by CPU is divided into:

● Page number (p) – used as an index into a page table which

contains base address of each page in physical memory
● Page offset (d) – combined with base address to define the
physical memory address that is sent to the memory unit

page number page offset

p d
m -n n

● For given logical address space 2m and page size 2n

Paging Hardware
Paging Model of Logical and Physical
Memory
 Paging Example

n=2 and m=4 32-byte memory and 4-byte

pages
 Paging (Cont.)

• Calculating internal fragmentation

– Page size = 2,048 bytes
– Process size = 72,766 bytes
– 35 pages + 1,086 bytes
– Internal fragmentation of 2,048 - 1,086 = 962 bytes
– Worst case fragmentation = 1 frame – 1 byte
– On average fragmentation = 1 / 2 frame size
– So small frame sizes desirable?
– But each page table entry takes memory to track
– Page sizes growing over time
• Solaris supports two page sizes – 8 KB and 4 MB
• Process view and physical memory now very different
• By implementation process can only access its own memory
 Free Frames

Before allocation After allocation

 Paging Example

0
▪ Page size = 4 bytes
Pag Fram
e
▪ Process address 1 e

space 21
011

= 4 pages
3
▪ Physical address
space
= 8 frames
▪ Logical address:
(1,3)
1101
= 0111 1

▪ Physical address:
(6,3)
 Addressing in Paging

▪ Logical address space of 16 pages of 1024

words each, mapped into a physical memory of 32
frames.
▪ Logical address size?
▪ Physical address size?
▪ Number of bits for p, f, and d?
 Addressing in Paging

▪ No. of bits for p = 4

bits
▪ No. of bits for f = 5 bits
▪ No. of bits for d = 11
bits
 Addressing in Paging

Logical address = |p| + |

size d|
= 4+11
= 15 bits

Physical address = |f| + |

size d|
= 5+11
= 16 bits
 Page Table Size

Page table size = NP * PTES

where NP is the number of pages in the process
address
space and PTES is the page table entry size (equal
to |f| table
Page based on =
our16discussion
*5 so far).
size bits
= 16 bytes
 Another Example

▪ Logical address = 32-bit

▪ Process address space = 232 B
= 4 GB
▪ Main memory = RAM = 512 MB
▪ Page size = 4K
▪ Maximum pages in a process address space =
232 / 4K
= 1M
 Another Example

▪ |d| = 12 bits
▪ |p| = 32 – 12 = 20
▪ bits
No. of = 512 M / 4 K
frames = 128
▪ |f| = 17 bits K

▪ Physical address = 17+12

bits
 Page Table Entries in Page Table

Frame Number – It gives the frame number in which the current page
you are looking for is present.
The number of bits required depends on the number of frames. Frame bit
is also known as address translation bit.
Number of bits for frame = Size of physical memory/frame size
Other Optional bits
1.Present/Absent bit – Present or absent bit says whether a particular
page you are looking for is present or absent. In case if it is not present,
that is called Page Fault. It is set to 0 if the corresponding page is not in
memory. Used to control page fault by the operating system to support
virtual memory. Sometimes this bit is also known as valid/invalid bits.
2.Protection bit – Protection bit says that what kind of protection you
want on that page. So, these bit for the protection of the page frame
(read, write etc).
3.Referenced bit – Referenced bit will say whether this page has been
referred in the last clock cycle or not. It is set to 1 by hardware when the
page is accessed.
 Page Table Entries in Page Table
4.Caching enabled/disabled – Sometimes we need the fresh data.
this bit enables or disable caching of the page.
5.Modified bit – Modified bit says whether the page has been modified
or not. Modified means sometimes you might try to write something on
to the page. If a page is modified, then whenever you should replace that
page with some other page, then the modified information should be
kept on the hard disk or it has to be written back or it has to be saved
back. It is set to 1 by hardware on write-access to page which is used to
avoid writing when swapped out. Sometimes this modified bit is also
called as the Dirty bit.
 Implementation of Page
Table
• Page table is kept in main memory
• Page-table base register (PTBR) points to the page table
• Page-table length register (PTLR) indicates size of the
page table
• In this scheme every data/instruction access requires two
memory accesses
– One for the page table and one for the data / instruction
• The two memory access problem can be solved
– by the use of a special fast-lookup hardware cache
– called associative memory or translation look-aside buffers
(TLBs)
 Implementation of Page Table

▪ Keep page table in the main memory

▪ Page table base register (PTBR)

▪ Teffective = 2Tmem
▪ Teffective is not acceptable
▪ Use a special, small, fast lookup hardware, called
translation look-aside buffer (TLB)
▪ Typically 64–1024 entries
▪ An entry is (key, value)
▪ Parallel search for key; on a hit, value is returned
 Implementation of Page Table

▪ (key,value) is (p,f) for paging

▪ For a logical address, (p,d), TLB is searched for p. If
an entry with a key p is found, we have a hit and f
is used to form the physical address. Else, page
table in the main memory is searched.
 TL
B

Logical
address: (p, d)

p
 Implementation of Page Table

▪ The TLB is loaded with the (p,f) pair so that

future references to p are found in the TLB,
resulting in improved hit ratio.
▪ On a context switch, the TLB is flushed and is
loaded with values for the scheduled process.
Paging Hardware With TLB
 Performance of Paging

▪ T on a hit = T +T
effective mem TLB
▪
T on a miss = 2T +T
effective mem TLB

▪ If HR is hit ratio and MR is miss ratio,

then

T = HR (T +T ) + MR (T + 2T )
effective TLB mem TLB mem
 Example

▪ Tmem = 100
nsec
▪ TTLB = 20 nsec
▪ Hit ratio is
80%
▪T Teffective
==
effective
?
0.8 (20 + 100) + 0.2 (20 + 2x100)
= 140 nanoseconds
 Example

▪ Tmem = 100
nsec
▪ TTLB = 20 nsec
▪ Hit ratio is
98%
▪ Teffective = ?
Teffective = 0.98 (20 + 100) + 0.02 (20 + 2x100)
= 122 nanoseconds
 Segmentation

▪ A memory management scheme that

supports programmer’s view of memory.
▪ A segment is a logical unit such as: main
program,

procedure, function, method, object, global

variables,

stack, symbol table

▪ A program is a collection of
segments
Segmentation
 Segmentation

3
4

5
 Segmentation

11

1 44

2
5
3
4
22

5 33
 Segmentation

11

44
1

2 5

3 22
4
segme
nt 33
5
table
 Segmentation

▪ Logical address consists of a two tuple:

<segment-number, offset>
▪ Segment table – maps two-dimensional
logical addresses to physical
addresses
 Segmentation

▪ Each segment table entry has:

▪ base – contains the starting physical
address where the segments reside
in memory.
▪ limit – specifies the length of the
segment.
 Segmentation

▪ Segment-table base register (STBR)

points to the segment table’s location in
memory.
▪ Segment-table length register (STLR) indicates
number of segments used by a program
▪ Segment number s is legal if s < STLR
 Segmentation

CPU
 Segmentation Architecture

▪ Dynamic Storage
Allocation
▪ First fit
▪ Best fit
▪ Worst fit

▪ External
fragmentation
Example
 Address Translation
▪ Logical and Physical Addresses
▪ (2, 399) – PA: 4300+399 = 4699
=
4700

▪ (6, 297) ⇒ trap

▪ (4, 0) – PA: 4700+0

▪ (4, 1000) ⇒ trap
▪ (3, 1300) ⇒ trap
 Issues with Segmentation

▪ Reduce external fragmentation by compaction

▪ Shuffle segments to place free memory
together in one block.
▪ Compaction is possible only if relocation is
dynamic, and is done at execution time.
Issues with Segmentation
▪ I/O problem
▪ Latch job in memory while it is involved
in I/O.
▪ Do I/O only into OS buffers
▪ Very large segments ⇒ page program
segments—
paged segmentation