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Lecture 05, Computer Architecture, CS 252

The document outlines the content of a Computer Architecture course (CS-252) at Sarhad University, focusing on system buses and interconnections. It covers foundational topics such as computer components, program concepts, instruction cycles, and interrupts. Recommended textbooks are provided alongside a detailed explanation of the instruction cycle and handling of interrupts in computer systems.

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13 views29 pages

Lecture 05, Computer Architecture, CS 252

The document outlines the content of a Computer Architecture course (CS-252) at Sarhad University, focusing on system buses and interconnections. It covers foundational topics such as computer components, program concepts, instruction cycles, and interrupts. Recommended textbooks are provided alongside a detailed explanation of the instruction cycle and handling of interrupts in computer systems.

Uploaded by

jameel717772
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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Computer Architecture

CS-252

BS - CS, SE, Telecom, Electronics

Credit Hours : 3-0

Department of Computer Science & IT


Sarhad University of Science and Information Technology, Peshawar
Chapter # 3
(Lect. 5)

System Buses/Interconnections

Department of Computer Science & IT


Sarhad University of Science and Information Technology, Peshawar
Previously (Lecture 1- 4)

• Prerequisite (Lect. 1)
• DLD, Basic Electronics & Microprocessor Architecture

• Chapter 1: Introduction (Lect. 2)


• Computer Architecture & Computer Organization

• A brief History of Computers (Lect. 3)


• The First Generation: Vacuum Tubes
• The Second Generation: Transistors Chapter 2
• The Third Generation: Integrated Circuits (ICs)

• Designing for Performance (Lect. 4)


Lecture Outlines
• Computer Components
• Program concept
• What is a program?
• Computer Components: Top-level view

• Computer Function
• Instruction cycle
• Fetch and Execute cycle
• Instruction cycle state diagram
• Interrupts
• Interrupt cycle
• Multiple interrupts
Recommended Books

1. Computer Organization and Architecture


by William Stallings, 8th or Latest Edition

2. Computer System Architecture


by Morris Mano, 3rd Edition

3. Computer Architecture and Organization


by John P. Hayes, International Edition
Computer Components
Program Concept
• Hardwired programs
– Programs in the form of hardware by small set of components to
store data and perform A/L operations on data
– are inflexible (hard/rigid)
Program Concept cont.…
• As alternative
– General purpose hardware (for A/L functions) can do different tasks
– Depending on correct control signals applied to hardware
• Instead of re-wiring for (each new program)
– Supply a new set of control signals
What is a program?
• A sequence of steps
• At each step, some arithmetic or logical operation is performed

– For each operation, a different set of control signals is needed


– i.e. unique code for each control signals
– e.g. ADD  addition, MOVE  data movement, Jump etc.

• A hardware segment (Instruction interpreter) accepts the code


and issues the control signals

• This method of programming, a sequence of codes or


instructions is called software
Components
• The Control Unit (CU) and the Arithmetic and Logic Unit
(ALU) constitute/compose the Central Processing Unit (CPU)
– i.e. CU+ALU=CPU (von Neumann Machine/Chapter-2)

• Data and instructions need to get


– into the system and (Input module)
– results need to get out (Output module)
• Together referred as I/O components

• Temporary storage of code and results is needed


– Main memory
Computer Components: Top Level View
Computer Basic Function
• Basic function performed by a computer is execution of a
program
– Consists of a set of instructions stored in memory
• Instruction processing consists of two step:
– Fetch (read instructions from memory one at a time)
– Execute (perform that instruction)
• Instruction cycle: The processing required for a single
instruction
Fetch Cycle
• Instruction cycle begins with fetch cycle
– Program Counter (PC) holds address of next instruction to be fetched
– Processor fetches instruction from memory location pointed to by PC
– Increment PC (to fetch the next instruction in sequence)
• Unless told otherwise

Execute Cycle
– Instruction loaded into Instruction Register (IR)
– Processor interprets instruction and performs required actions
Execute Cycle
• Actions perform by processor during execution cycle

– Processor-memory
• Data may be transfer between Processor and main memory
– Processor -I/O
• Data may be transfer between Processor and I/O module (unit)
– Data processing
• Perform arithmetic or logical operation on data
– Control
• Alteration of sequence of operations e.g. jump
– Combination of above actions
Example of Program Execution
(Add 3(940) & 2(941) and replace result at 941
Instruction Cycle State Diagram
(For example: ADD AX, BX)
Interrupts
• Mechanism by which other modules (e.g. I/O) may interrupt
normal sequence of processing
• Most common classes of interrupts:
– Program = occurs as a result of an instruction execution
• e.g. overflow, division by zero, illegal machine instruction
– Timer
• Interrupt generated by internal processor timer
• Used in pre-emptive multi-tasking/OS
– I/O
• Generated from I/O controller
• to signal normal completion of an operation or
• to signal a variety of error conditions
– Hardware failure
• e.g. power failure, memory parity error
Program Flow Control
(with and without interrupts)
Interrupt Cycle
• Added to instruction cycle
• Processor checks for interrupt
– Indicated by an interrupt signal
• If no interrupt, fetch next instruction
• If interrupt pending:
– Suspend execution of current program
– Save context (background information)
– Set PC to start address of interrupt handler routine
– Process interrupt
– Restore context and continue interrupted program
Transfer of Control via Interrupts
Instruction Cycle with Interrupts
Program Timing Short I/O Wait
Program Timing Long I/O Wait
Instruction Cycle -State Diagram
(Instruction cycle with Interrupts)
Multiple Interrupts(communication line & printing)
• Disable interrupts (1st approach)
– Processor will ignore further interrupts while processing one interrupt
– Interrupts remain pending and are checked after first interrupt has been
processed
– Interrupts handled in sequence as they occur

• Define priorities (2nd approach)


– Low priority interrupts can be interrupted by higher priority interrupts
– When higher priority interrupt has been processed, processor returns to
previous interrupt
Multiple Interrupts - Sequential
Multiple Interrupts – Nested
Time Sequence of Multiple Interrupts
Thank you

Department of Computer Science & IT


Sarhad University of Science and Information Technology, Peshawar

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