Lecture 05, Computer Architecture, CS 252
Lecture 05, Computer Architecture, CS 252
CS-252
System Buses/Interconnections
• Prerequisite (Lect. 1)
• DLD, Basic Electronics & Microprocessor Architecture
• Computer Function
• Instruction cycle
• Fetch and Execute cycle
• Instruction cycle state diagram
• Interrupts
• Interrupt cycle
• Multiple interrupts
Recommended Books
Execute Cycle
– Instruction loaded into Instruction Register (IR)
– Processor interprets instruction and performs required actions
Execute Cycle
• Actions perform by processor during execution cycle
– Processor-memory
• Data may be transfer between Processor and main memory
– Processor -I/O
• Data may be transfer between Processor and I/O module (unit)
– Data processing
• Perform arithmetic or logical operation on data
– Control
• Alteration of sequence of operations e.g. jump
– Combination of above actions
Example of Program Execution
(Add 3(940) & 2(941) and replace result at 941
Instruction Cycle State Diagram
(For example: ADD AX, BX)
Interrupts
• Mechanism by which other modules (e.g. I/O) may interrupt
normal sequence of processing
• Most common classes of interrupts:
– Program = occurs as a result of an instruction execution
• e.g. overflow, division by zero, illegal machine instruction
– Timer
• Interrupt generated by internal processor timer
• Used in pre-emptive multi-tasking/OS
– I/O
• Generated from I/O controller
• to signal normal completion of an operation or
• to signal a variety of error conditions
– Hardware failure
• e.g. power failure, memory parity error
Program Flow Control
(with and without interrupts)
Interrupt Cycle
• Added to instruction cycle
• Processor checks for interrupt
– Indicated by an interrupt signal
• If no interrupt, fetch next instruction
• If interrupt pending:
– Suspend execution of current program
– Save context (background information)
– Set PC to start address of interrupt handler routine
– Process interrupt
– Restore context and continue interrupted program
Transfer of Control via Interrupts
Instruction Cycle with Interrupts
Program Timing Short I/O Wait
Program Timing Long I/O Wait
Instruction Cycle -State Diagram
(Instruction cycle with Interrupts)
Multiple Interrupts(communication line & printing)
• Disable interrupts (1st approach)
– Processor will ignore further interrupts while processing one interrupt
– Interrupts remain pending and are checked after first interrupt has been
processed
– Interrupts handled in sequence as they occur