PIPELINING

• In computers, a pipeline is the continuous and somewhat overlapped

movement of instruction to the processor or in the arithmetic steps taken
by the processor to perform an instruction. Pipelining is the use of a
pipeline.

• Without a pipeline, a computer processor gets the first instruction from

memory, performs the operation it calls for, and then goes to get the next
instruction from memory, and so forth. While fetching (getting) the
instruction, the arithmetic part of the processor is idle. It must wait until it
gets the next instruction.

• With pipelining, the computer architecture allows the next instructions

to be fetched while the processor is performing arithmetic operations,
holding them in a buffer close to the processor until each instruction
operation can be performed. The staging of instruction fetching is
continuous. The result is an increase in the number of instructions that
can be performed during a given time period.
• MIPS instructions classically take five steps:
1. Fetch instruction from memory.
2. Read registers while decoding the instruction.
The regular format of MIPS instructions allows
reading and decoding to occur simultaneously.
3. Execute the operation or calculate an address.
4. Access an operand in data memory.
5. Write the result into a register.
Hence, the MIPS pipeline we explore in this
chapter has five stages. The following example
shows that pipelining speeds up instruction
execution just as it speeds up the laundry.
a. Instruction fetch cycle(IF)
• Send the program counter (PC) to memory and
fetch the current instruction from memory.
PC=PC+4.
b. Instruction decode/register fetch cycle (ID):
• Decode the instruction and read the registers. Do
the equality test on the registers as they are read,
for a possible branch. Compute the possible branch
target address by adding the sign-extended offset
to the incremented PC. Decoding is done in parallel
with reading registers, which is possible because
the register specifies are at a fixed location in a
RISC architecture, known as fixed-field decoding.
c. Execution/effective address cycle (EX):
The ALU operates on the operands prepared in the prior
cycle, performing one of three functions depending on
the instruction type.
i. Memory reference: The ALU adds the base register
and the offset to form the effective address.
ii. Register-Register ALU instruction: The ALU performs
the operation specified by the ALU opcode on the
values read from the register file.
iii. Register-Immediate ALU instruction: The ALU
performs the operation specified by the ALU opcode
on the first value read from the register file and the
sign extended immediate.
• d. Memory access (MEM)
If the instruction is a load, memory does a read
using the effective address computed in the
previous cycle. If it is a store, then the memory
writes the data from the second register read
from the register file using the effective address.
• e. Write-back cycle (WB)
Register-Register ALU instruction or Load
instruction: file, whether it comes from the
memory system (for a load).Write the result into
the register or from the ALU.
• The same principles apply to processors where
we pipeline instruction-execution.
• Formula for pipelining speed-up.-If the stages
are perfectly balanced, then the time
between instructions on the pipelined
processor—assuming ideal conditions—is
equal to
• Under ideal conditions and with a large number of
instructions, the speed-up from pipelining is
approximately equal to the number of pipe stages;
a five-stage pipeline is nearly five times faster.
• The formula suggests that a five-stage pipeline
should offer nearly a fivefold improvement over the
800 ps non pipelined time, or a 160 ps clock cycle.
• Moreover, pipelining involves some overhead, the
source of which will be clearer shortly. Thus, the
time per instruction in the pipelined processor will
exceed the minimum possible, and speed-up will be
less than the number of pipeline stages.
 Total time for each instruction calculated
from the time for each component
Instruction Instruction Register ALU Data Register Total
class fetch read operation access write time

Load word 200 ps 100ps 200ps 200ps 100ps 800ps

(lw)
Store 200 ps 100ps 200ps 200ps --- 700ps
word (sw)
R format 200 ps 100ps 200ps -- 100ps 600ps
instruction
Branch 200 ps 100ps 200ps -- -- 500 ps
(beq)
Step 1: Fetch and decode
Step 2: Read registers
Step 3: Use the ALU
Step 4: Access operand in memory
Step 5: Store result in register
 Pipelined Data Path and Control
The division of an instruction into five stages means a five -
stage pipeline, which in turn means that up to five
instructions will be in execution during any single clock cycle.
Thus, we must separate the data path into five pieces, with
each piece named corresponding to a stage of instruction
execution:
1. IF: Instruction fetch
2. ID: Instruction decode and register file read
3. EX: Execution or address calculation
4. MEM: Data memory access
5. WB: Write back
Datapath & Control in Pipeline Processing
• There are, however, two exceptions to this
left-to-right flow of instructions:
• The write-back stage, which places the result
back into the register file in the middle of the
datapath
• The selection of the next value of the PC,
choosing between the incremented PC and
the branch address from the MEM stage.
Pipelined Datapath
• It shows the pipelined datapath with the pipeline
registers highlighted. All instructions advance during
each clock cycle from one pipeline register to the
next. The registers are named for the two stages
separated by that register. For example, the pipeline
register between the IF and ID stages is called IF/ID.
• The pipeline registers separate each pipeline stage.
They are labeled by the stages that they separate;
for example, the first is labeled IF/ID because it
separates the instruction fetch and instruction
decodes stages. The registers must be wide enough
to store all the data corresponding to the lines that
go through them.