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Cmos Process

The document explains the functioning of MOS transistors as electrically controlled switches and their role in building logic gates such as CMOS inverters, NAND, and NOR gates. It also discusses the importance of layout design, including mask specifications and feature sizes, which affect transistor performance and chip design. Overall, it provides foundational knowledge for designing schematics and layouts for simple chips.

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Akash Hosmath
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6 views29 pages

Cmos Process

The document explains the functioning of MOS transistors as electrically controlled switches and their role in building logic gates such as CMOS inverters, NAND, and NOR gates. It also discusses the importance of layout design, including mask specifications and feature sizes, which affect transistor performance and chip design. Overall, it provides foundational knowledge for designing schematics and layouts for simple chips.

Uploaded by

Akash Hosmath
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Transistors as Switches

• We can view MOS transistors as electrically


controlled switches
• Voltage at gate controls path
g = 0 from source
g = 1 to

drain d d
OFF
d
nMOS g ON
s s s

d d d

pMOS g OFF
ON
s s s

0: Introduction Slide 15
CMOS Inverter

A Y VDD
0
1

A Y

A Y
GND
0: Introduction Slide 16
CMOS Inverter

A Y VDD
0
1 0 OFF
A=1 Y=0

ON
A Y
GND
0: Introduction Slide 17
CMOS Inverter

A Y VDD
0 1
1 0 ON
A=0 Y=1

OFF
A Y
GND
0: Introduction Slide 18
CMOS NAND Gate
A B Y
0 0
0 1 Y
1 0
A
1 1
B

0: Introduction Slide 19
CMOS NAND Gate
A B Y
0 0 1 ON ON
0 1 Y=1
A=0
1 0 OFF
1 1
B=0
OFF

0: Introduction Slide 20
CMOS NAND Gate
A B Y
0 0 1 OFF ON
0 1 1 Y=1
A=0
1 0 OFF
1 1
B=1
ON

0: Introduction Slide 21
CMOS NAND Gate
A B Y
0 0 1 ON OFF
0 1 1 Y=1
A=1
1 0 1 ON
1 1
B=0
OFF

0: Introduction Slide 22
CMOS NAND Gate
A B Y
0 0 1 OFF OFF
0 1 1 Y=0
A=1
1 0 1 ON
1 1 0
B=1
ON

0: Introduction Slide 23
CMOS NOR Gate
A B Y
0 0 1 A
0 1 0
1 0 0 B
1 1 0 Y

0: Introduction Slide 24
3-input NAND Gate
• Y pulls low if ALL inputs are 1
• Y pulls high if ANY input is 0

Y
A
B
C

0: Introduction Slide 25
Layout
• Chips are specified with set of masks
• Minimum dimensions of masks determine
transistor size (and hence speed, cost, and
power)
• Feature size f = distance between source and
drain
– Set by minimum width of polysilicon
• Feature size improves 30% every 3 years or so
• Normalize for feature size when describing
design rules 0: Introduction Slide 26
Simplified Design Rules
• Conservative rules to get you started

0: Introduction Slide 27
Inverter Layout
• Transistor dimensions specified as Width /
Length
– Minimum size is 4l / 2l, sometimes called 1 unit
– In f = 0.6 mm process, this is 1.2 mm wide, 0.6 mm
long

0: Introduction Slide 28
Summary
• MOS Transistors are stack of gate, oxide,
silicon
• Can be viewed as electrically controlled
switches
• Build logic gates out of switches
• Draw masks to specify layout of transistors

• Now you know everything necessary to start


designing schematics and layout for a simple
0: Introduction Slide 29
chip!

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