Chapter 2 Modern CMOS technology

1. Introduction.
2. CMOS process flow.

NE 343: Microfabrication and thin film technology

Instructor: Bo Cui, ECE, University of Waterloo; http://ece.uwaterloo.ca/~bcui/ 1
Textbook: Silicon VLSI Technology by Plummer, Deal and Griffin
 CMOS: complementary metal–oxide–semiconductor
• In the simplest CMOS technologies, we need to realize simply NMOS and PMOS transistors
for circuits like those illustrated below.
• Typical CMOS technologies in manufacturing add additional steps to implement multiple
device VTH, thin film transistors (TFT) in SRAMs, capacitors for DRAMs etc.
• CMOS described here requires 16 masks (through metal level 2) and >100 process steps.
• There are many possible variations on the process flow (e.g. LOCOS device isolation vs.
shallow trench isolation).

n-MOS & p-MOS require different channel background doping and source/drain region doping.
In CMOS, the gate is no longer “metal”, it is heavily doped poly-crystalline Si with low resistance.
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 CMOS is required by logic circuits
+V
+V

IN 1 NOR:
Inverter:
Output = IN1+IN2
Output = Input S
PMOS IN 2

D OUTPUT
OUTPUT

INPUT D
NMOS

S Output = GND = 0 if
any Input or both
GND are +V = 1
GND

CMOS (n-MOS & p-MOS) reduces static power dissipation.

Because (e.g. for the inverter) there is no current flow from +V to GND since one of
the MOS is always off.
The same inverter logic can also be realized by replacing the top PMOS with a
resistor R (ON NMOS << R << OFF NMOS), but current flows when NMOS is on.
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 N-MOSFET (field effect transistor) operation

Inverted to n-type
Body (bulk Si) is commonly tied to ground (0V).
When the gate is at a low voltage: When the gate is at a high voltage:
• P-type body is at low voltage, source-channel- • Positive charge on gate of MOS
drain is N+PN+. capacitor.
• If drain is positive bias (i.e. electrons flow from • Negative charge attracted to the top
the source and ‘drained’ to the drain), the right surface just below the gate oxide.
side PN+ diode is in reverse bias. • Inverts a channel under gate to n-
• Left side N+P is in zero-bias, as source is usually type, source-channel-drain is N+NN+.
connected to the grounded bulk Si. • Now current can flow through n-type
• No current flows through the channel, silicon from source through channel
transistor is OFF to drain, transistor is ON. 4
 P-MOSFET (field effect transistor) operation

Body tied to high voltage (= source voltage, supply voltage).

Gate low (grounded, which is lower than high voltage bulk Si): transistor is ON.
Gate high (same as bulk Si): transistor is OFF.

Since voltage has only a relative meaning. This is equivalent to the situation of:
grounded body/bulk Si, grounded source, negative (< 0V) drain voltage (so holes flow
from source and ‘drained’ to drain).
Then transistor is ON when gate is negatively biased, and OFF when gate is grounded.
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 Transistors as switches

We can view MOS transistors as electrically controlled switches,

and voltage at gate controls path from source to drain.

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 CMOS inverter
Inverter:
Output = Input
g=Input=0, NMOS is
off, PMOS is on.
Output=+V=1.
When Input =1,
Output=GND=0

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 CMOS NAND gate

Output = 0 only when both Inputs are 1

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Cross-section of the CMOS IC

p
This is what we are going to fabricate in this chapter. 9
 Fabrication “toolkit”
• Insulating Layers LPCVD: low pressure chemical vapor
o Oxidation, nitridation deposition.
o Deposition (LPCVD, PECVD, APCVD) PECVD: plasma enhanced CVD.
• Selective doping of silicon APCVD: atmospheric pressure CVD
o Diffusion (in-situ doping) RIE: reactive ion etching
o Ion implantation DRIE: deep RIE.
o Epitaxy (in-situ doping) CMP: chemical mechanical polishing
• Material deposition (silicon, metals, insulators)
o LPCVD
o PECVD
o Sputter deposition
• Patterning of Layers
o Lithography (UV, deep UV, e-beam & x-ray)
• Etching of (deposited) material
o Dry etches—plasma, RIE, sputter etch, DRIE
o Wet etches—etch in liquids, CMP etc

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 Chapter 2 Modern CMOS technology

1. Introduction.
2. CMOS process flow.

NE 343 Microfabrication and thin film technology

Instructor: Bo Cui, ECE, University of Waterloo 11
Textbook: Silicon VLSI Technology by Plummer, Deal and Griffin
 Choosing the substrate and active region formation

Nitride has high tensile stress, oxide has compressive stress.

The two stress can balance/compensate each other to reduce
stress in Si that may cause defects in Si.

LPCVD nitride: 3SiH4+4NH3  Si3N4+12H2, 800oC.

LPCVD: low pressure chemical vapor deposition

Substrate selection: moderately high resistivity (lightly doped, 10 15cm-3), (100)

orientation substrate (better Si/SiO2 interface than other orientations), P type.
Start from low doping, then dope P-well and N-well by ion implantation that is
much better controlled than substrate doping (done during crystal growth).
Wafer cleaning, thermal oxidation (≈ 40 nm, using O2, or H2O generated from H2
and O2 reaction, cleaner than H2O vapor from boiling water), Si3N4 LPCVD (≈ 80 nm),
12
photoresist spinning and baking (≈ 0.5 - 1.0 μm).
 Active region formation
Photolithography, nitride etching

Mask #1 patterns the active areas. The nitride is dry etched.

Dry etch = plasma etch, reactive species are generated in a plasma (like arc
discharge). E.g F is generated in CF4 plasma. Atomic F is extremely reactive.
Si3N4 + 12F  3SiF4 (gas/volatile, pumped away) + 2N2 13
 LOCOS isolation
LOCOS: LOCal Oxidation of Silicon
Remove resist, thermal oxidation

Si3N4 is very dense material and prevents/blocks H2O or

O2 from diffusion to the Si surface, thus no oxidation
under nitride.

Remove photoresist. Field oxide is partially recessed into the surface

Field oxide is grown using a (oxidation consume some of the silicon)
LOCOS process. Field oxides forms a lateral extension under
the nitride layer – bird’s beak region
Typically 90min @ 1000˚C in
Bird’s beak region limits device scaling and
H2O grows SiO2 ≈ 0.5 µm.
device density in VLSI circuits!

http://en.wikipedia.org/wiki/LOCOS 14
 Alternative process to LOCOS isolation:
shallow trench isolation with filled implants (here P+)

LOCOS:
Bird’s Beak
problem,
unsuitable for
small device.

• Growth of pad silicon dioxide and deposition of silicon nitride as in LOCOS

• Implant trench to increase field threshold (for better device isolation) and
growth of liner oxide for passivation and smoothing
• Trench fill with deposited oxide (not thermally grown oxide)
• CMP (chemical mechanical polishing) for planarization.
Note: this process added P+ impanation, slightly different from the process in textbook.
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 P-well formation
Wet etch away Si3N4, spin photoresist, lithography, B+ implantation.

In ion implantation, positive B+ ions are formed by exposing the

source gas containing B to an arc discharge.
Only B + is selected by a bending magnet to pass through a slit.
B + energy is high enough to pass through the field (LOCOS)
oxide. But photoresist is thick enough to block the ions.

Mask #2 blocks a B+ implant to form the wells for the NMOS devices.
Typically dose 1013cm-2 @ 150-200 KeV (very high energy).
(Implant dose is in cm-2, doping concentration is in cm-3)
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 N-well formation
Strip photoresist, spin resist and photolithography, ion implantation

Mask #3 blocks a P+ implant to form the wells for the PMOS devices.
Typically 1013 cm-2 @ 300-400 KeV.
(P is heavier than B, so higher energy needed)

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 N- and P- well formation
Remove resist and anneal

Ion energy is 100keV, much higher than energy needed to

break 4 Si bonds (total 12eV), so ion implantation induces
many damages.
B and P have similar diffusion coefficient, so similar final well
depth.

A high temperature drive-in produces the “final” well depths and

repairs implant damage.
Typically 4-6 hours @ 1000˚C - 1100˚C or equivalent Dt.
(here D is diffusion coefficient, t is time)

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 Threshold voltage (VTH) adjustment
Spin photoresist, photolithography, B+ ion implantation

Implant dose

2 S qN A 2 f  qQI
VTH VFB  2 f  
COX COX
Figure 2-22

Mask #4 is used to mask the PMOS devices.

A VTH adjust implant is done on the NMOS devices.
Typically 1-5 x 1012cm-2 B+ implant @ 50 - 75 KeV.

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Note: section 2.2.5 is skipped
 Threshold voltage (VTH) adjustment
Remove resist, then spin photoresist, photolithography, As+ ion implantation

Again, adjust VTH by controlling implant dose QI.

Mask #5 is used to mask the NMOS devices.

A VTH adjust implant is done on the PMOS devices.
Typically 1-5 x 1012 cm-2 As+ implant @ 75 - 100 KeV.

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 Gate oxide growth
Remove resist, etch oxide, re-grow thermal oxide

The ‘old’ oxide (to compensate stress of Si3N4) is too thick,

and may be damaged during the several implantation
steps.
Figure 2-24

The thin oxide over the active regions is stripped and a new gate oxide
grown, typically 3 - 5nm, which could be grown in 0.5 - 1 hrs @ 800˚C in O 2.

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 Poly-crystalline silicon deposition

MOSFET: metal oxide semiconductor field effect transistor

But actually metal is no longer used, instead, low resistance heavily
doped poly-Si is used.

LPCVD poly-Si: SiH4  Si + 2H2.

Poly-silicon is deposited by LPCVD ( ≈ 0.5 µm).

An unmasked P+ or As+ implant dopes the poly (typically 5 x 1015 cm-2,
high doping to reduce gate resistance).
Both P and As have high solubility in Si, good for heavy doping.
When heated, they will diffuse quickly through grain boundary (now
that poly) to achieve uniform doping. 22
 Gate formation
Spin resist, photolithography, selective anisotropic etch of poly-Si.
Poly: poly-crystalline
(not single crystal)

Poly-Si can also be used for local wiring. But not

for long wiring as it is resistance is still much
higher than metal.

Mask #6 is used to protect

The photolithography in this step is the most
the MOS gates.
demanding since it requires the finest
The poly-Si is plasma etched resolution to create the narrow MOS channels.
using an anisotropic etch. 23
 Tip or extension/LDD (lightly doped drain) formation
Strip resist, spin resist, photolithography, ion implantation

When channel length shrinks more

than drive voltage, electric field in
the channel may become very
high, creating “hot electrons” that
may create additional hole-
electron pair or inject into gate
oxide.
LDD (graded doping) allows drain
voltage to be dropped over larger
distance, thus reducing peak
Figure 2-27
electric field/hot electron effect.

Mask #7 protects the PMOS devices.

A P+ implant forms the LDD regions in The polysilicon gate acts like a barrier for
the NMOS devices. this implant to protect the channel region.
This is thus a self-aligned process.
Typically 5 x 1013cm-2 @ 50 KeV.
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Tip or extension/LDD (lightly doped drain) formation
Remove resist, spin resist, photolithography, B+ ion implantation

As LDD is shallower than N+ and P+

source/drain doping, it also reduces “short
channel effect” due to the shallower channel.

Mask #8 protects the NMOS devices.

A B+ implant forms the LDD regions in the PMOS devices.
Typically 5 x 1013cm-2 @ 50 KeV.

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 Sidewall spacer formation

Deposit conformal SiO2 (or nitride)

LPCVD: SiH4 + O2  SiO2 + 2H2 at 400oC

SiH2Cl2 + N2O  SiO2 + 2N2 + 2HCl at 900oC

Conformal layer of SiO2 is deposited using LPCVD (typically 0.5 µm).

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 Sidewall spacer formation

Selective anisotropic dry etching

This works because deposition is conformal (isotropic),

whereas etching is anisotropic (faster etching along
vertical direction, little along horizontal direction).

Anisotropic etching leaves “sidewall spacers”

along the edges of the poly gates.

Timed etch of oxide/nitride using very directional etch (RIE).

Just enough time to remove oxide from the source, drain and gate regions.
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 Source/drain formation for NMOS
Thermal oxidization, spin resist, photolithography, As+ ion implantation

Grow a thin oxide to reduce “channeling effect” during ion

implantation, as well as protect the Si surface from
contaminants.
As atom has low diffusion coefficient, good for shallow junction.

Mask #9 protects the PMOS devices.

An As+ implant forms the NMOS source and drain regions.
Typically 2-4 x 1015cm-2 @ 75 KeV.
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 Source/drain formation for PMOS
Strip resist, spin resist, photolithography, B+ ion implantation

Again, high dose implant to reduce parasitic

resistance in the source/drain region.
Figure 2-32
Mask #10 protects the NMOS devices.
A B+ implant forms the PMOS source and drain regions.
Typically 1-3 x 1015cm-2 @ 50 KeV.

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 Drive-in anneal
Remove resist and anneal (diffusion, damage repair and dopant activation)

Anneal is always needed after ion implantation to repair Si lattice

damage caused by energetic ion, and active dopant (bring it to
crystalline sites).

A final high temperature anneal drives-in the junctions and

repairs implant damage.
Typically 30 min @ 900˚C or 1 min RTA @ 1000˚C.
(RTA: rapid thermal annealing)

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Contact and local interconnect formation
Etch away oxide, deposit Ti

Figure 2-35

An unmasked oxide etch allows contacts to Si and poly regions.

Ti is deposited by sputtering (typically 100nm).

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 Contact and local interconnect formation
TiN
(conductive
TiSi2 Anneal in nitrogen
)

TiSi2 is an excellent conductor.

TiN is also conductive, good enough for local interconnects.

The Ti is reacted in an N2 ambient, forming TiSi2 and TiN.

Typically RTP 1 min @ 600 - 700˚C. (RTP: rapid thermal processing)
This process is called self-aligned silicide (salicide), since TiSi2 is formed only
on the Si surface at source, drain and gate. TiN is formed at SiO2 surface.
Salicide reduces gate resistance, source/drain contact resistance. 32
 Contact and local interconnect formation
Spin resist, photolithography, TiN selective etching

Mask #11 is used to etch the TiN, forming local interconnects.

TiN etched by NH4OH:H2O2:H2O (1:1:5)
Then an anneal at 800oC in Ar for 1 minute to reduce the
resistivity of TiN and TiSi2 to their final values.
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 Multi-level metal formation
Remove resist, deposit SiO2

The SiO2 layer is often doped with P (PSG – phosphosilicate glass) that
protects the device against mobile ions like Na+.
B may also be added (BPSG – borophosphosilicate glass) to reduce
the flowing temperature of the glass (flow to smooth out the surface,
good for planarization).

A conformal layer of SiO2 is deposited by LPCVD (typically 1 µm).

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 Surface planarization
Chemical mechanical polishing (CMP)

In CMP, besides mechanical polishing (by nanoparticles in the slurry),

chemical reaction (e.g. by adjusting pH) is also important.
The total polishing rate is much higher than mechanical polishing rate
and chemical reaction rate alone.

Besides CMP, planarization can also be done by spinning resist and etching
back, using a recipe where etching rates for resist and glass are the same.

35
 Multi-level metal formation
Spin resist, photolithography, oxide etching

Figure 2-40

Mask #12 is used to define the contact holes.

The SiO2 is plasma etched (reactive ion etching).

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 W stud (via) formation
Remove resist, deposit TiN diffusion barrier/adhesion layer and W

W CVD (chemical vapor deposition):

WF6 (gas) + 3H2  W + 6HF (gas)

A thin TiN barrier layer is deposited by sputtering (typically a few

tens of nm), followed by W CVD deposition.

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 W stud (via) formation
Polishing

Damascene process: the process where contact holes are

etched, filled, and planarized.

CMP is used to planarize the wafer surface,

completing the “damascene process”.

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 Multi-level metal formation
Deposit Al, spin resist, photolithography, selectively etch Al

Usually small percentage of Si and Cu is added to Al.

Add Si because Si is soluble in Al up to a few percent, and if
not added now, Al will take/corrode Si from device region.
Add Cu to prevent eletromigration in Al thin films (Al atoms
move around, leaving behind voids)

Al is deposited on the wafer by sputtering.

Mask #13 is used to pattern the Al and plasma etching is used to etch it.
(Al is one of the few metals that can be etched by plasma)
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 Multi-level metal formation
Strip resist, deposit insulator layer, W stud and Al wire formation,Si3N4 passivation layer
deposition.

P
Inter-metal dielectric and second level metal are deposited and defined in the same way
as level #1.
Mask #14 is used to define contact via-holes.
Mask #15 is used to define metal 2.
Passivation/protection layer of Si3N4 is deposited by PECVD and patterned with Mask #16.
Final anneal (400-500oC, 30min, in forming gas – 10% H2 in N2) to alloy the metal contacts
and reduce electrical charges in the Si/SiO2 interfaces. 40
 Finish the device
Wire bonding and packaging

(source gate drain)

41
Top view of an inverter

42
 90 nm
generation
transistor and
interconnect Carrier
moves faster
in strained Si
Ni silicide (not Ti silicide).
Only 1.2nm gate oxide.
Strained silicon.
Low-k dielectric (lower ,
than SiO2,) to reduce
capacitance and RC delay
for faster circuit.
Copper interconnect (not
Al) by electroplating and
chemical mechanical
polishing (see next slide).

43
 Advanced metallization: Cu based
Dual damascene IC process

44
 CMOS interconnects

Modern processes use

several levels of metal,
separated by layers of
deposited oxide or
other low-k materials.

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