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Lec02 Address Space

The document discusses memory chips, addressing, and interfacing I/O devices with microprocessors. It explains the concepts of memory-mapped I/O and I/O-mapped I/O, highlighting their differences in addressing and data transfer methods. Additionally, it covers bus contention issues and the advantages and disadvantages of partially and fully decoded addressing methods.

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10 views14 pages

Lec02 Address Space

The document discusses memory chips, addressing, and interfacing I/O devices with microprocessors. It explains the concepts of memory-mapped I/O and I/O-mapped I/O, highlighting their differences in addressing and data transfer methods. Additionally, it covers bus contention issues and the advantages and disadvantages of partially and fully decoded addressing methods.

Uploaded by

heymarufa
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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Memory Chip

‘k’ data input lines


‘n’ address lines
Memory Chip select
read
write ‘k’ bits per word

‘k’ data output lines


Address Space

 Depends on the number of address lines of the CPU.


 Set of all possible addresses, called the address space of the CPU
 EX: 8086 has 20 address lines, thus can address up to 1 MB of
memory. So its address space is 1 MB
Interfacing I/O Devices

 Using I/O devices data can be transferred between the


microprocessor and the outside world.
 This can be done in groups of 8 bits using the entire data bus.
This is called parallel I/O.
 The other method is serial I/O where one bit is transferred at a
time using the SID (serial input data) and SOD pins on the
Microprocessor.
Types of Parallel Interface

 There are two ways to interface mpu with I/O devices in parallel
data transfer mode:
 Memory Mapped IO
 IO Mapped IO (Isolated IO)
Parallel Interface
Memory Mapped IO

 It considers them like any other memory location.


 They are assigned a 16-bit address within the address range of the
8085.
 The exchange of data with these devices follows the transfer of
data with memory. The user uses the same instructions used for
memory.
I/O Mapped I/O

 It treats them separately from memory.


 I/O devices are assigned a “port number” within the 8-bit address
range of 00H to FFH.
 The user in this case would access these devices using the IN and
OUT instructions only.
I/O mapped I/O V/s Memory Mapped I/O

Memory Mapped I/O I/O Mapped I/O

• IO is treated as memory. • IO is treated IO.


• 16-bit addressing. • 8-bit addressing.
• More Decoder Hardware. • Less Decoder Hardware.
• Can address 2^16 =64k • Can address 2^8=256
locations. locations.
• Less memory is available • Whole memory address
space is available.
IO mapped IO V/s Memory Mapped IO

Memory Mapped IO IO Mapped IO

• Memory Instructions are • Special Instructions are used


used. like IN, OUT.
• Memory control signals are • Special control signals are
used. used.
• Arithmetic and logic • Arithmetic and logic
operations can be performed operations can not be
on data. performed on data.
• Data transfer b/w register and • Data transfer b/w
IO. accumulator and IO
Bus Contention

 Bus contention is a condition in which more than one memory


device is attempting to interact with the data bus
 This condition will cause:
 Overloading of the data bus
 Incorrect data being read or written
Partially Decoded Addressing
Partially Decoded Addressing

 The main advantage of linear select decoding is its


simplified decoding circuit. This reduces the hardware design
cost.
 But there are many disadvantages in this decoding.
i) Multiple addresses are provided for the same location
ii) Complete memory space of the microprocessor is not efficiently
used
iii) Adding or interfacing ICs with already existing circuitry is
difficult.
Fully Decoded Addressing
Fully Decoded Addressing

 There are many advantages in absolute address decoding.


i) Each memory location has only one address, there is no
duplication in the address
ii) Memory can be placed contiguously in the address space of
the microprocessor
iii) Future expansion can be made easily without disturbing the
existing circuitry
 There are few disadvantages in this method
i) Extra decoders are necessary
ii) Some delay will be produced by these extra decoders.

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