+

William Stallings
Computer Organization
and Architecture
10th Edition

© 2016 Pearson Education, Inc., Hoboken,

NJ. All rights reserved.
+ Chapter 4
Cache Memory
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 Table 4.1
Key Characteristics of Computer Memory Systems

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+
Characteristics of Memory
Systems
 Location
 Refers to whether memory is internal and external to the
computer
 Internal memory is often equated with main memory
 Processor requires its own local memory, in the form of registers
 Cache is another form of internal memory
 External memory consists of peripheral storage devices that are
accessible to the processor via I/O controllers

 Capacity
 Memory is typically expressed in terms of bytes

 Unit of transfer
 For internal memory the unit of transfer is equal to the number of
electrical lines into and out of the memory module

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 Method of Accessing Units of
Data
Sequential Direct Random Associativ
access access access e

Each addressable
A word is retrieved
Memory is organized location in memory has
Involves a shared read- based on a portion of
into units of data a unique, physically
write mechanism its contents rather
called records wired-in addressing
than its address
mechanism

Each location has its

The time to access a
own addressing
Individual blocks or given location is
Access must be made mechanism and
records have a unique independent of the
in a specific linear retrieval time is
address based on sequence of prior
sequence constant independent
physical location accesses and is
of location or prior
constant
access patterns

Any location can be

Cache memories may
selected at random
Access time is variable Access time is variable employ associative
and directly addressed
access
and accessed

Main memory and

some cache systems
are random access

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Capacity and Performance:

The two most important characteristics

of memory

Three performance parameters are

used:
Memory cycle time
Access time (latency) • Access time plus any additional
Transfer rate
• For random-access memory it is time required before second • The rate at which data can be
the time it takes to perform a access can commence transferred into or out of a
read or write operation • Additional time may be required memory unit
• For non-random-access memory for transients to die out on • For random-access memory it is
it is the time it takes to position signal lines or to regenerate equal to 1/(cycle time)
the read-write mechanism at the data if they are read
desired location destructively
• Concerned with the system bus,
not the processor

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+ Memory
 The most common forms are:
 Semiconductor memory
 Magnetic surface memory
 Optical
 Magneto-optical

 Several physical characteristics of data storage are important:

 Volatile memory
 Information decays naturally or is lost when electrical power is switched off
 Nonvolatile memory
 Once recorded, information remains without deterioration until deliberately changed
 No electrical power is needed to retain information
 Magnetic-surface memories
 Are nonvolatile
 Semiconductor memory
 May be either volatile or nonvolatile
 Nonerasable memory
 Cannot be altered, except by destroying the storage unit
 Semiconductor memory of this type is known as read-only memory (ROM)

 For random-access memory the organization is a key design issue

 Organization refers to the physical arrangement of bits to form words

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+
Memory Hierarchy

 Design constraints on a computer’s memory can be

summed up by three questions:
 How much, how fast, how expensive

 There is a trade-off among capacity, access time, and

cost
 Faster access time, greater cost per bit
 Greater capacity, smaller cost per bit
 Greater capacity, slower access time

 The way out of the memory dilemma is not to rely on a

single memory component or technology, but to
employ a memory hierarchy

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© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
+
Memory
 The use of three levels exploits the fact that
semiconductor memory comes in a variety of types
which differ in speed and cost
 Data are stored more permanently on external mass
storage devices
 External, nonvolatile memory is also referred to as
secondary memory or auxiliary memory
 Disk cache
 A portion of main memory can be used as a buffer to hold
data temporarily that is to be read out to disk
 A few large transfers of data can be used instead of many
small transfers of data
 Data can be retrieved rapidly from the software cache rather
than slowly from the disk
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© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
 Table 4.2
Elements of Cache Design
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+
Cache Addresses
Virtual Memory
 Virtual memory
 Facility that allows programs to address memory from a
logical point of view, without regard to the amount of main
memory physically available
 When used, the address fields of machine instructions
contain virtual addresses
 For reads to and writes from main memory, a hardware
memory management unit (MMU) translates each virtual
address into a physical address in main memory

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© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
Mapping Function
 Because there are fewer cache lines than main
memory blocks, an algorithm is needed for mapping
main memory blocks into cache lines
 Three techniques can be used:

Direct Associative Set Associative

• The simplest technique • Permits each main • A compromise that
• Maps each block of memory block to be exhibits the strengths
main memory into only loaded into any line of of both the direct and
one possible cache line the cache associative approaches
• The cache control logic while reducing their
disadvantages
interprets a memory
address simply as a Tag
and a Word field
• To determine whether a
block is in the cache,
the cache control logic
must simultaneously
examine every line’s
Tag for a match

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© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
+
Direct Mapping Summary

 Address length = (s + w) bits

 Number of addressable units = 2s+w words or bytes
 Block size = line size = 2w words or bytes
 Number of blocks in main memory = 2s+ w/2w = 2s
 Number of lines in cache = m = 2r
 Size of tag = (s – r) bits

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+
Victim Cache

 Originally proposed as an approach to reduce the

conflict misses of direct mapped caches without
affecting its fast access time
 Fully associative cache
 Typical size is 4 to 16 cache lines
 Residing between direct mapped L1 cache and the next
level of memory

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+
Associative Mapping Summary

 Address length = (s + w) bits

 Number of addressable units = 2s+w words or bytes
 Block size = line size = 2w words or bytes
 Number of blocks in main memory = 2s+ w/2w = 2s
 Number of lines in cache = undetermined
 Size of tag = s bits

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+
Set Associative Mapping

 Compromise that exhibits the strengths of both the

direct and associative approaches while reducing their
disadvantages
 Cache consists of a number of sets
 Each set contains a number of lines
 A given block maps to any line in a given set
 e.g. 2 lines per set
 2 way associative mapping
 A given block can be in one of 2 lines in only one set

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© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
+
Set Associative Mapping
Summary
 Address length = (s + w) bits
 Number of addressable units = 2s+w words or bytes
 Block size = line size = 2w words or bytes
 Number of blocks in main memory = 2 s+w/2w=2s
 Number of lines in set = k
 Number of sets = v = 2d
 Number of lines in cache = m=kv = k * 2d
 Size of cache = k * 2d+w words or bytes
 Size of tag = (s – d) bits
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© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
+
Main Memory (128 byte)

0000

0001

0010

0011
Cache (32 byte)
0100
00
..
Block (8 byte)
01
..
10
..
11
..

..

..

..

..

..

1111

By: Hanan Nadeem

+
Main Memory (128 byte)

0000

0001
To overcome the
0010
disadvantage of
direct mapping, Cache (32 byte)
0011

Associative mapping 00
0100

arise 01
..

..
10
..
11
1000

..

..

1100

..

..

1111

By: Hanan Nadeem

+
Main Memory (128 byte)

0000

0001
Memory block can be
0010
placed in ANY cache
line Cache (32 byte)
0011

0100
00
..
01
..
10
..
11
1000

..

..

1100

..

..

1111

By: Hanan Nadeem

+
Main Memory (128 byte)

0000

0001
Tag bits holds the whole
0010
block index bits
0011
Tag bits size = Block Tag bits Cache (32 byte)
0100
Index 00
..
0100 01
..
10
..
11
1000

..

..

1100

..

..

1111

By: Hanan Nadeem

+
Main Memory (128 byte)

BK 1 0000

Example BK 2 0001

BK 3 0010

BK 4 0011
Tag bits Cache (32 byte)
BK 5 0100
BK 2 00
BK 6 ..
BK 4 01
BK 7 ..
BK 5 10
BK 8 ..
BK 15 11
BK 9 1000

BK 10 ..

BK 11 ..

BK 12 1100

BK 13 ..

BK 14 ..

BK 15 1111

By: Hanan Nadeem

+
Main Memory (128 byte)

BK 1 0000

Example BK 2 0001

BK 3 0010

BK 4 0011
Tag bits Cache (32 byte)
BK 5 0100
0001 BK 2 00
BK 6 ..
BK 4 01
BK 7 ..
BK 5 10
BK 8 ..
BK 15 11
BK 9 1000

BK 10 ..

BK 11 ..

BK 12 1100

BK 13 ..

BK 14 ..

BK 15 1111

By: Hanan Nadeem

+
Main Memory (128 byte)

BK 1 0000

Example BK 2 0001

BK 3 0010

BK 4 0011
Tag bits Cache (32 byte)
BK 5 0100
0001 BK 2 00
BK 6 ..
0011 BK 4 01
BK 7 ..
BK 5 10
BK 8 ..
BK 15 11
BK 9 1000

BK 10 ..

BK 11 ..

BK 12 1100

BK 13 ..

BK 14 ..

BK 15 1111

By: Hanan Nadeem

+
Main Memory (128 byte)

BK 1 0000

Example BK 2 0001

BK 3 0010

BK 4 0011
Tag bits Cache (32 byte)
BK 5 0100
0001 BK 2 00
BK 6 ..
0011 BK 4 01
BK 7 ..
0100 BK 5 10
BK 8 ..
1111 BK 15 11
BK 9 1000

BK 10 ..

BK 11 ..

BK 12 1100

BK 13 ..

BK 14 ..

BK 15 1111

By: Hanan Nadeem

+
Main Memory (128 byte)

BK 1 0000

Example BK 2 0001

BK 3 0010

BK 4 0011
CPU Tag bits Cache (32 byte)
Requests: BK 5 0100
0001 BK 2 00
BK 6 ..
0100010 0011 BK 4 01
BK 7 ..
7 bits physical 0100 BK 5 10
BK 8 ..
Address (Why?) 1111 BK 15 11
BK 9 1000
What is W size?? BK 10 ..

BK 11 ..

BK 12 1100

BK 13 ..

BK 14 ..

BK 15 1111

By: Hanan Nadeem

+
Main Memory (128 byte)

BK 1 0000

Example BK 2 0001

BK 3 0010

BK 4 0011
CPU Tag bits Cache (32 byte)
Requests: BK 5 0100
0001 BK 2 00
BK 6 ..
0100010 0011 BK 4 01
BK 7 ..
0100 BK 5 10
BK 8 ..
1111 BK 15 11
BK 9 1000

BK 10 ..

BK 11 ..
Physical address
BK 12 1100
0 1 0 0 0 1 0
BK 13 ..
Tag W 3bits
BK 14 ..

BK 15 1111

By: Hanan Nadeem

+
Main Memory (128 byte)

BK 1 0000

Example BK 2 0001

BK 3 0010

BK 4 0011
Tag bits Cache (32 byte)
BK 5 0100
Comparator
0001 BK 2 00
BK 6 ..
0011 BK 4 01
BK 7 ..
0100 BK 5 10
BK 8 ..
1111 BK 15 11
BK 9 1000

BK 10 ..

BK 11 ..
Physical address
BK 12 1100
0 1 0 0 0 1 0
BK 13 ..
Tag W 3bits
BK 14 ..

BK 15 1111

By: Hanan Nadeem

+
Main Memory (128 byte)

BK 1 0000

Example BK 2 0001

BK 3 0010

BK 4 0011
Tag bits Cache (32 byte)
BK 5 0100
Comparator
X 0001 BK 2 00
BK 6 ..
Comparator 0011 BK 4 01
BK 7 ..
Comparator
0100 BK 5 10
BK 8 ..
Comparator
1111 BK 15 11
BK 9 1000

BK 10 ..

BK 11 ..
Physical address
BK 12 1100
0 1 0 0 0 1 0
BK 13 ..
Tag W 3bits
BK 14 ..

BK 15 1111

By: Hanan Nadeem

+
Main Memory (128 byte)

BK 1 0000

Example BK 2 0001

BK 3 0010

BK 4 0011
Tag bits Cache (32 byte)
BK 5 0100
Comparator
X 0001 BK 2 00
BK 6 ..
Comparator 0011 BK 4 01
X
BK 7 ..
Comparator
0100 BK 5 10
BK 8 ..
Comparator
1111 BK 15 11
BK 9 1000

BK 10 ..

BK 11 ..
Physical address
BK 12 1100
0 1 0 0 0 1 0
BK 13 ..
Tag W 3bits
BK 14 ..

BK 15 1111

By: Hanan Nadeem

+
Main Memory (128 byte)

BK 1 0000

Example BK 2 0001

BK 3 0010

BK 4 0011
Tag bits Cache (32 byte)
BK 5 0100
Comparator
X 0001 BK 2 00
BK 6 ..
Comparator 0011 BK 4 01
X
BK 7 ..
Comparator Hit 0100 BK 5 10
BK 8 ..
Comparator
1111 BK 15 11
BK 9 1000

BK 10 ..

BK 11 ..
Physical address
BK 12 1100
0 1 0 0 0 1 0
BK 13 ..
Tag W 3bits
BK 14 ..

BK 15 1111

By: Hanan Nadeem

+
Main Memory (128 byte)

BK 1 0000

Example BK 2 0001

BK 3 0010

BK 4 0011
Tag bits Cache (32 byte)
BK 5 0100
Comparator
0001 BK 2 00
BK 6 ..
Comparator 0011 BK 4 01
BK 7 ..
Comparator
0100 BK 5 10
BK 8 ..
Comparator
1111 BK 15 11
BK 9 1000

BK 10 ..

BK 11 ..
Physical address
BK 12 1100
1 1 0 0 0 1 1
BK 13 ..
Tag W 3bits
BK 14 ..

BK 15 1111

By: Hanan Nadeem

+
Main Memory (128 byte)

BK 1 0000

Example BK 2 0001

BK 3 0010

BK 4 0011
Tag bits Cache (32 byte)
BK 5 0100
Comparator
X 0001 BK 2 00
BK 6 ..
Comparator X 0011 BK 4 01
BK 7 ..
Comparator X 0100 BK 5 10
BK 8 ..
Comparator X 1111 BK 15 11
BK 9 1000

BK 10 ..

BK 11 ..
Physical address
BK 12 1100
1 1 0 0 0 1 1
BK 13 ..
Tag W 3bits
BK 14 ..

BK 15 1111

By: Hanan Nadeem

+
Main Memory (128 byte)

BK 1 0000

Example BK 2 0001

BK 3 0010

BK 4 0011
Tag bits Cache (32 byte)
BK 5 0100
Comparator
X 0001 BK 2 00
BK 6 ..
Comparator X 0011 BK 4 01
BK 7 ..
Comparator X 0100 full BK 5 10
BK 8 ..
Comparator X 1111 BK 15 11
BK 9 1000

BK 10 ..

BK 11 ..
Physical address
BK 12 1100
1 1 0 0 0 1 1
BK 13 ..
Tag W 3bits
BK 14 ..

BK 15 1111

By: Hanan Nadeem

Set+Associative Mapping
+
Main Memory (128 byte)

0000

0001
To overcome the
0010
Comparators overhead, we
group the cache lines into k- Cache (32 byte)
0011

way in set-Associative 00
0100

mapping 01
..

..
10
..
k is simply the number of 11
1000
lines in a set ..

..

1100

..

..

1111

By: Hanan Nadeem

+
Main Memory (128 byte)

0000

0001
Example: 2-way sets
0010

0011
Cache (32 byte)
0100
00
Main memory blocks assigns Set 0
..
01
into cache sets using Direct ..
10
Mapping Set 1 ..
11
Inside the set, Associative 1000

Mapping are used ..

..
Thus, set-Associative Mapping is a
1100
combination of both
..
How many number of comparators?? ..

1111

By: Hanan Nadeem

+
Main Memory (128 byte)

BK 1 0000

Example BK 2 0001
2-way set associative cache
BK 3 0010

BK 4 0011
Tag bits Cache (32 byte)
BK 5 0100
To find the number of sets: 00
0 BK 6 ..
01
no. set = no. Lines / k 10
BK 7 ..

=4/2 1
11
BK 8 ..

= 2 sets BK 9 1000

BK 10 ..

= 21 BK 11 ..

BK 12 1100

BK 13 ..

BK 14 ..

BK 15 1111

By: Hanan Nadeem

+
Main Memory (128 byte)

BK 1 0000

Example BK 2 0001
2-way set associative cache
BK 3 0010

BK 4 0011
Tag bits Cache (32 byte)
BK 5 0100
BK 3 00
0 BK 6 ..
BK 5 01
BK 7 ..
BK 4 10
1 BK 8 ..
BK 2 11
BK 9 1000

BK 10 ..

BK 11 ..

BK 12 1100

BK 13 ..

BK 14 ..

BK 15 1111

By: Hanan Nadeem

+
Main Memory (128 byte)

BK 1 0000

Example BK 2 0001
2-way set associative cache
BK 3 0010

BK 4 0011
Tag bits Cache (32 byte)
BK 5 0100
001 BK 3 00
0 BK 6 ..
BK 5 01
BK 7 ..
BK 4 10
1 BK 8 ..
BK 2 11
BK 9 1000

BK 10 ..

BK 11 ..

BK 12 1100

BK 13 ..

BK 14 ..

BK 15 1111

By: Hanan Nadeem

+
Main Memory (128 byte)

BK 1 0000

Example BK 2 0001
2-way set associative cache
BK 3 0010

BK 4 0011
Tag bits Cache (32 byte)
BK 5 0100
001 BK 3 00
0 BK 6 ..
010 BK 5 01
BK 7 ..
BK 4 10
1 BK 8 ..
BK 2 11
BK 9 1000

BK 10 ..

BK 11 ..

BK 12 1100

BK 13 ..

BK 14 ..

BK 15 1111

By: Hanan Nadeem

+
Main Memory (128 byte)

BK 1 0000

Example BK 2 0001
2-way set associative cache
BK 3 0010

BK 4 0011
Tag bits Cache (32 byte)
BK 5 0100
001 BK 3 00
0 BK 6 ..
010 BK 5 01
BK 7 ..
001 BK 4 10
1 BK 8 ..
000 BK 2 11
BK 9 1000

BK 10 ..

BK 11 ..

BK 12 1100

BK 13 ..

BK 14 ..

BK 15 1111

By: Hanan Nadeem

+
Main Memory (128 byte)

BK 1 0000

Example BK 2 0001
2-way set associative cache
BK 3 0010

BK 4 0011
CPU Tag bits Cache (32 byte)
Requests: BK 5 0100
001 BK 3 00
0 BK 6 ..
0001010 010 BK 5 01
BK 7 ..
001 BK 4 10
1 BK 8 ..
000 BK 2 11
BK 9 1000

BK 10 ..

BK 11 ..
Physical address
BK 12 1100
0 1 0 1 0 0 0
BK 13 ..

Ta S W BK 14 ..
g I
BK 15 1111

By: Hanan Nadeem

+
Main Memory (128 byte)

BK 1 0000

Example BK 2 0001
2-way set associative cache
BK 3 0010

BK 4 0011
CPU Tag bits Cache (32 byte)
Requests: BK 5 0100
001 BK 3 00
0 BK 6 ..
0001010 010 BK 5 01
BK 7 ..
Comparator
001 BK 4 10
1 BK 8 ..
Comparator 000 BK 2 11
BK 9 1000

BK 10 ..

BK 11 ..
Physical address
BK 12 1100
0 1 0 1 0 0 0
BK 13 ..

Ta S W BK 14 ..
g I
BK 15 1111

By: Hanan Nadeem

+
Main Memory (128 byte)

BK 1 0000

Example BK 2 0001
2-way set associative cache
BK 3 0010

BK 4 0011
CPU Tag bits Cache (32 byte)
Requests: BK 5 0100
001 BK 3 00
0 BK 6 ..
0001010 010 BK 5 01
BK 7 ..
Comparator X 001 BK 4 10
1 BK 8 ..
Comparator Hit 000 BK 2 11
BK 9 1000

BK 10 ..

BK 11 ..
Physical address
BK 12 1100
0 1 0 1 0 0 0
BK 13 ..

Ta S W BK 14 ..
g I
BK 15 1111

By: Hanan Nadeem

+
Replacement Algorithms

 Once the cache has been filled, when a new block is

brought into the cache, one of the existing blocks must
be replaced
 For direct mapping there is only one possible line for
any particular block and no choice is possible
 For the associative and set-associative techniques a
replacement algorithm is needed
 To achieve high speed, an algorithm must be
implemented in hardware

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+ The most common replacement
algorithms are:
 Least recently used (LRU)
 Most effective
 Replace that block in the set that has been in the cache longest
with no reference to it
 Because of its simplicity of implementation, LRU is the most
popular replacement algorithm

 First-in-first-out (FIFO)
 Replace that block in the set that has been in the cache longest
 Easily implemented as a round-robin or circular buffer technique

 Least frequently used (LFU)

 Replace that block in the set that has experienced the fewest
references
 Could be implemented by associating a counter with each line

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 Write Policy
When a block that is resident
in the cache is to be There are two problems to
replaced there are two cases contend with:
to consider:

If the old block in the cache has not

been altered then it may be More than one device may have
overwritten with a new block without access to main memory
first writing out the old block

A more complex problem occurs

If at least one write operation has when multiple processors are
been performed on a word in that line attached to the same bus and each
of the cache then main memory must processor has its own local cache - if
be updated by writing the line of a word is altered in one cache it could
cache out to the block of memory conceivably invalidate a word in
before bringing in the new block other caches

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+
Write Through
and Write Back
 Write through
 Simplest technique
 All write operations are made to main memory as well as to the
cache
 The main disadvantage of this technique is that it generates
substantial memory traffic and may create a bottleneck

 Write back
 Minimizes memory writes
 Updates are made only in the cache
 Portions of main memory are invalid and hence accesses by I/O
modules can be allowed only through the cache
 This makes for complex circuitry and a potential bottleneck

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 Line Size
When a block of
data is retrieved Two specific effects
and placed in the come into play:
cache not only • Larger blocks reduce the
the desired word As the block size number of blocks that fit
but also some increases more into a cache
number of useful data are • As a block becomes
larger each additional
adjacent words brought into the word is farther from the
are retrieved cache requested word

As the block size The hit ratio will

increases the hit begin to
ratio will at first decrease as the
increase because block becomes
of the principle bigger and the
of locality probability of
using the newly
fetched
information
becomes less
than the
probability of
reusing the
information that
has to be
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+
Multilevel Caches
 As logic density has increased it has become possible to have a
cache on the same chip as the processor
 The on-chip cache reduces the processor’s external bus activity and
speeds up execution time and increases overall system performance
 When the requested instruction or data is found in the on-chip cache, the
bus access is eliminated
 On-chip cache accesses will complete appreciably faster than would even
zero-wait state bus cycles
 During this period the bus is free to support other transfers

 Two-level cache:
 Internal cache designated as level 1 (L1)
 External cache designated as level 2 (L2)

 Potential savings due to the use of an L2 cache depends on the hit

rates in both the L1 and L2 caches
 The use of multilevel caches complicates all of the design issues
related to caches, including size, replacement algorithm, and write
policy
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© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
+
Unified Versus Split Caches
 Has become common to split cache:
 One dedicated to instructions
 One dedicated to data
 Both exist at the same level, typically as two L1 caches

 Advantages of unified cache:

 Higher hit rate
 Balances load of instruction and data fetches automatically
 Only one cache needs to be designed and implemented

 Trend is toward split caches at the L1 and unified caches for

higher levels
 Advantages of split cache:
 Eliminates cache contention between instruction fetch/decode unit
and execution unit
 Important in pipelining
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+ Summary Cache
Memory
Chapter 4
 Elements of cache
 Computer memory
system overview design
 Cache addresses
 Characteristics of
 Cache size
Memory Systems
 Memory Hierarchy  Mapping function

 Cache  Replacement
memory
principles algorithms
 Write policy
 Line size
 Number of caches

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