+

William Stallings
Computer Organization
and Architecture
10th Edition

© 2016 Pearson Education, Inc., Hoboken,

NJ. All rights reserved.
+ Chapter 3
A Top-Level View of Computer
Function and Interconnection
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
+
Computer Components
 Contemporary computer designs are based on concepts
developed by John von Neumann at the Institute for
Advanced Studies, Princeton
 Referred to as the von Neumann architecture and is
based on three key concepts:
 Data and instructions are stored in a single read-write
memory
 The contents of this memory are addressable by location,
without regard to the type of data contained there
 Execution occurs in a sequential fashion (unless explicitly
modified) from one instruction to the next

 Hardwired program
 The result of the process of connecting the various
components in the desired configuration
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
+
Hardware
and Software
Approaches

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

 Software
• A sequence of codes or instructions
• Part of the hardware interprets each Software
instruction and generates control signals
• Provide a new sequence of codes for each new
program instead of rewiring the hardware
Major components:
• CPU I/O
• Instruction interpreter
Components
• Module of general-purpose arithmetic and
logic functions
• I/O Components
• Input module
+ • Contains basic components for accepting
data and instructions and converting them
into an internal form of signals usable by
the system
• Output module
• Means of reporting results
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
 Memory Memory buffer
address register (MBR) MEMORY
register (MAR) • Contains the data
• Specifies the to be written into
address in memory or
memory for the receives the data
next read or write read from
memory

MAR
I/O address I/O buffer
register register
(I/OAR) (I/OBR)
• Specifies a • Used for the
+ particular I/O exchange of data
device between an I/O
module and the
CPU MBR

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
+
Fetch Cycle
 At the beginning of each instruction cycle the
processor fetches an instruction from memory
 The program counter (PC) holds the address of the
instruction to be fetched next
 The processor increments the PC after each
instruction fetch so that it will fetch the next
instruction in sequence
 The fetched instruction is loaded into the instruction
register (IR)
 The processor interprets the instruction and performs
the required action

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

 Action Categories
• Data transferred • Data transferred to
from processor to or from a peripheral
memory or from device by
memory to transferring
processor between the
processor and an
I/O module

Processor Processor
-memory -I/O

Data
Control processin
g
• An instruction may • The processor may
specify that the perform some
sequence of arithmetic or logic
execution be operation on data
altered

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
 Table 3.1

Classes of Interrupts

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
+
I/O Function
 I/O module can exchange data directly with the processor
 Processor can read data from or write data to an I/O
module
 Processor identifies a specific device that is controlled by a
particular I/O module
 I/O instructions rather than memory referencing instructions

 In some cases it is desirable to allow I/O exchanges to

occur directly with memory
 The processor grants to an I/O module the authority to read
from or write to memory so that the I/O memory transfer can
occur without tying up the processor
 The I/O module issues read or write commands to memory
relieving the processor of responsibility for the exchange
 This operation is known as direct memory access (DMA)

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

Interconnection
Structures

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

 The interconnection structure must support the
following types of transfers:

Memory
Processo I/O to I/O to or
to Processo
r to processo from
processo r to I/O
memory r memory
r
An I/O
module is
allowed to
exchange
data
Processor Processor directly
reads an Processor reads Processor with
instructio writes a data from sends memory
n or a unit unit of an I/O data to without
of data data to device via the I/O going
from memory an I/O device through
memory module the
processor
using
direct
memory
access

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

 A communication pathway Signals transmitted by
connecting two or more any one device are
devices available for reception by
• Key characteristic is that it is a
shared transmission medium
all other devices attached
to the bus
Bus
• If two devices transmit during
the same time period their
signals will overlap and
Inte
rcon
become garbled

Typically consists of
multiple communication
Computer systems
contain a number of nect
different buses that
lines
• Each line is capable of
transmitting signals
provide pathways
between components at
ion
representing binary 1 and various levels of the
binary 0 computer system
hierarchy

System bus
• A bus that connects major The most common
computer components computer interconnection
(processor, memory, I/O) structures are based on
the use of one or more
system buses

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

 Data Bus
 Data lines that provide a path for moving data among
system modules
 May consist of 32, 64, 128, or more separate lines
 The number of lines is referred to as the width of the
data bus
 The number of lines determines how many bits can be
transferred at a time
 The width of the data bus
is a key factor in
determining overall
system performance

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

+ Address Bus Control Bus

 Used to designate the source or

destination of the data on the
 Used to control the access and
data bus the use of the data and address
lines
 If the processor wishes to read
a word of data from memory it  Because the data and address
puts the address of the lines are shared by all
desired word on the address components there must be a
lines means of controlling their use
 Width determines the maximum  Control signals transmit both
possible memory capacity of the command and timing information
system among system modules
 Also used to address I/O ports  Timing signals indicate the
 The higher order bits are used validity of data and address
to select a particular module information
on the bus and the lower order
bits select a memory location
 Command signals specify
or I/O port within the module operations to be performed
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
+
Point-to-Point Interconnect
At higher and higher data
Principal reason for
rates it becomes
change was the electrical
increasingly difficult to
constraints encountered
perform the
with increasing the
synchronization and
frequency of wide
arbitration functions in a
synchronous buses
timely fashion

A conventional shared
bus on the same chip
magnified the difficulties Has lower latency, higher
of increasing bus data data rate, and better
rate and reducing bus scalability
latency to keep up with
the processors

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

 +Quick Path Interconnect
QPI
 Introduced in 2008
 Multiple direct connections
 Direct pairwise connections to other components
eliminating the need for arbitration found in shared
transmission systems

 Layered protocol architecture

 These processor level interconnects use a layered
protocol architecture rather than the simple use of
control signals found in shared bus arrangements

 Packetized data transfer

 Data are sent as a sequence of packets each of
which includes control headers and error control
codes
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
+
Peripheral Component
Interconnect (PCI)
 A popular high bandwidth, processor independent bus that
can function as a mezzanine or peripheral bus
 Delivers better system performance for high speed I/O
subsystems
 PCI Special Interest Group (SIG)
 Created to develop further and maintain the compatibility of the
PCI specifications

 PCI Express (PCIe)

 Point-to-point interconnect scheme intended to replace bus-based
schemes such as PCI
 Key requirement is high capacity to support the needs of higher
data rate I/O devices, such as Gigabit Ethernet
 Another requirement deals with the need to support time
dependent data streams
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
+ Receives read and write requests

from the software above the TL and
creates request packets for
transmission to a destination via
the link layer
PCIe
 Most transactions use a split
transaction technique
Transaction Layer (TL)
 A request packet is sent out by a
source PCIe device which then
waits for a response called a
completion packet
 TL messages and some write
transactions are posted
transactions (meaning that no
response is expected)

 TL packet format supports 32-bit

memory addressing and
extended 64-bit memory
addressing

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

+
The TL supports four address
spaces:
 Memory  I/O
 The memory space includes  This address space is
system main memory and used for legacy PCI
PCIe I/O devices
devices, with reserved
 Certain ranges of memory address ranges used to
addresses map into I/O address legacy I/O
devices
devices
 Configuration  Message
 This address space  This address space is for
enables the TL to control signals related to
read/write configuration interrupts, error handling,
registers associated with and power management
I/O devices

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

+ A Top-Level View of
Summary Computer Function
and
Interconnection
Chapter 3
 Point-to-point interconnect
 QPI physical layer
 Computer components
 QPI link layer
 Computer function
 QPI routing layer
 Instruction fetch and
execute
 QPI protocol layer
 Interrupts  PCI express
 I/O function  PCI physical and logical
 Interconnection structures architecture
 Bus interconnection  PCIe physical layer
 PCIe transaction layer
 PCIe data link layer
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.