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Randomization of System Verilog: Hussain Shaikh 2AB22EC400

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7 views8 pages

Randomization of System Verilog: Hussain Shaikh 2AB22EC400

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hussainshaikh8431
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RANDOMIZATION OF SYSTEM

VERILOG
HUSSAIN SHAIKH
2AB22EC400
SIMPLE CLASS WITH RANDOM
VARIABLES
This class has four random variables. The first three use the rand modifier, so that
every time you randomize the class, the variables are assigned a value. Think of rolling
dice: each roll could be a new value or repeat the current one. The kind variable
is randc, which means random cyclic, so that the random solver does not repeat a
random value until every possible value has been assigned. Think of dealing cards
from a deck: you deal out every card in the deck in random order, then shuffle the
deck, and deal out the cards in a different order. Note that the cyclic pattern is for a
single variable. A randc array with eight elements has eight different patterns.
The randomize() function returns 0 if a problem is found with the constraints. The
procedural assertion is used to check the result, as shown in Section 4.8. This example
uses a $fatal to stop simulation, but the rest of the book leaves out this extra code.
You need to find the tool-specific switches to force the assertion to terminate simulation.
This book uses assert to test the result from randomize(), but you may want
to test the result, call your special routine that prints any useful information and then
gracefully shut down the simulation .
RANDOMIZING AN OBJECT IN CLASS
CONSTRUCTOR
You should not randomize an object in the class
constructor. Your testmay need to turn constraints on or
off, change weights, or even addnew constraints before
randomization. The constructor is forinitializing the
object’s variables, and if you called randomize() at
thisearly stage, you might end up throwing away the
results.
All variables in your classes should be random and
public. This givesyour test the maximum control over the
DUT’s stimulus and control.
If you forget to make a variable random, you must edit
the environment,
which you want to avoid.
CHECKING THE RESULT FROM
RANDOMIZATION

• The randomize() function assigns random values to any variable in


• the class that has been labeled as rand or randc, and also makes sure
• that all active constraints are obeyed. Randomization can fail if your
• code has conflicting constraints (see next section), and so you should
• always check the status. If you don’t check, the variables may get
• unexpected values, causing your simulation to fail.
THE CONSTRAINT SOLVER

The process of solving constraint expressions is handled by the SystemVerilog


constraintsolver.
The solver chooses values that satisfy the constraints. The values come from
SystemVerilog’sPRNG, which is started with an initial seed.
If you give a SystemVerilogsimulator the same seed and the same testbench, it
always produces the same results.
WHAT CAN BE RANDOMIZED?

SystemVerilog allows you to randomize integral variables, that is, variables


that containa simple set of bits.
This includes 2-state and 4-state types, though randomization
only works with 2-state values.
You can have integers, bit vectors, etc. You cannot
have a random string, or refer to a handle in a constraint.1
THANK YOU

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