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Introduction Verilog Simple FSM Coding Style

Syntax Example Implementation for RTL
s

Digital VLSI Design

Verilog HDL
 What is a hardware description
language?
•HDL is NOT another programming language:
• Textual representation of Hardware constructs
• All statements are executed in parallel
• Code ordering is
flexible. Example:
• a=1;b=2;c=a+b 
c==3
• c=a+b;a=1;b=2 
c==3
• Execution of code is
triggered by Events
• Sensitivity lists are
used to define when 2
Abstraction
levels
• Three coding styles:
• Structural code (GTL (Gate Level), Netlist)
• RTL (Register Transfer Level)
• Behavioral (Testbench)
• DUT (Device Under Test)
• Represents Hardware
• Usually RTL or GTL
• Testbench
• Represents System
• Usually Behavioral
• Using higher order languages (“e”/SystemVerilog)

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 1 2 3 4 5
Introduction Verilog Simple FSM Coding Style
Syntax Example Implementation for RTL
s

Verilog Syntax
Basic Constructs
• Primitives:
• not, and, or,
etc. or(out, in1, in2);

• Signals:
• 4 states: 0,1,X,Z
• Wires: do not keep states
• Registers: keep states (i.e.,
outputs)
• Can represent buses or group of
signalswire in1,in2;
reg out;
wire [7:0] data;
reg [31:0] mem [0:7]; //width (bits)=32, depth
(words)=8 5
Basic Constructs
• Operators:
• Similar to primitives
• &, |, ~, &&, ||,
out = in1 | in2;
etc.

• Constants:
• The format is: W’Bval
• Examples:
• 1’b0 – single bit binary 0 (or decimal
0)
• 4’b0011 - 4 bit binary 0011 (or
decimal 3)
• 8’hff = 8 bit hexadecimal ff (or
decimal 255) 6
• 8’d255= 8 bit decimal 255
Procedural Blocks
initial begin
• Initial block a = 1’b0;
• Will be executed only once, at first timeb = 1’b0;
• the unit is called (Only in testbench) end
always @(posedge clock)
if (!nreset)
• Always block q <= 1’b0;
Statements will be evaluated else
q <= d;
when
a change in sensitivity list always @(posedge clock or negedge
occurs nreset) if (!nreset)
• Example1 - sync reset, q <= 1’b0;
else if
rising edge triggered (load_enable) q
7
flop: <= d;
Procedural Blocks
• There are two types of always
always @(posedge clock or negedge
blocks nreset)
if (!
• Sequential nreset) q
• Asserted by a clock in the <= 1’b0;
else if
sensitivity list. (load_enable) q
• Translates into flip-flops/latches. <= d;
always @(a or b or c)
• Combinational out = a & b & c;
• Describes purely combinational
logic, and therefore, the
sensitivity list always @(*)
has (non-clock) signals. out = a & b & c;

• The Verilog 2001

standard allows using * 8
Assignments
Verilog has three types of assign muxout = (sel&in1) |
assignments: (~sel&in0);
assign muxout = sel ? in1 : in0;
• Continuous assignment // assume initially a=1;
• Outside of always blocks a = 2;
• RHS isprocedural
• Blocking assignment
executed and “= is
assignment b = a;
// a=2; b=2;
” completed
executed.
before the next statement is

• Non-blocking procedural assignment “<= ” // assume initially a=1;

a <= 2;
• RHS is executed and assignment takes b <= a;
place // a=2; b=1;
at the end of the current time step (not
• clock cycle)
Combinational always block: Use blocking assignments (=)
• To• eliminate
Sequentialmistakes,
always follow these
block: Userules:
non-blocking assignments (<=)
• Do not mix blocking and non-blocking in the same always block
• Do not assign to the same variable from more than one 9
 Hierarchy
• Modules • Instances
• Used to define a hardware • Referencing a block at a
block different
module mux4 (out, in,
sel); input [3:0] in; level
input [1:0] sel; Modul mux4 M0 (.out(outa),.in(a),.sel(sel))
output out; e ;
reg out; Heade mux4 M1 (.out(outb),.in(b),.sel(sel))
r ;
always @*
case
(sel)
2’b00: Modul
out = e
in[0]; Body
2’b01:
out =
in[1];
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2’b10:
 System Tasks
• System tasks are used to provide interface to simulation data
• Identified by a $name syntax
• Printing tasks:
• $display, $strobe: Print once the statement is executed
• $monitor: Print every time there is a change in one of the
parameters
• All take the “c” style printf format
$display(“At %t Value of out is %b\n”,$time,out);

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 1 2 3 4 5
Introduction Verilog Simple FSM Coding Style
Syntax Example Implementation for RTL
s

Simple
Examples
Hello World
• Your first Verilog
module:
module
main;
initial
begin
$disp
lay(“
Hello
world
!”);
$finish
; end
endmodule

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 Combinatorial Logic
• Three ways to make a Mux
• Using an assign • Using a case
Statement:
wire out; statement:
reg out;
assign out = sel ? a : b; always @ (a or b or
sel) begin
case (sel)
• Using an always 1’b0: out=b;
Block: 1’b1:
reg out; out=a;
always @ (a or b or endcas
sel) if (sel) e end
out=a;
else
out=b;

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Sequential Logic
• A simple D-Flip • Be careful not to infer
Flop: latches!!!:
reg q; reg q;
always @(posedge always
clk) q<= d; @(en)
if (en)
q<=
• An asynch reset D-Flip d;
Flop:
reg q;
always @(posedge clk or negedge
reset_)
if
(~reset_)
q<= 0;
else
q<= d;
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 Arithmetic
• Verilog supports standard arithmetic operators:
• +, -, *, << (shift left), >> (shift right), etc.
• Be careful about division… (not synthesizable!)
• Concatenate signals with the {,} operatorassign a = 4’b1100;
assign b = 4’b1010;
assign c = {a,b};
• But… //c=8’b11001010
• By default, Verilog treats all vectors as unsigned binary
• numbers.
To do signed (two’s complement) wire signed [9:0] a,b;
operations, declare the reg/wire as wire signed [19:0] result =
a*b;
signed:
• To make a constant signed, add an s:
10’sh37C

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 reg vs. wire
• Oh no… Don’t go there!
• A reg is not necessarily an actual register, but rather a “driving signal”…
(huh?)
• This is truly the most ridiculous thing in Verilog…
• But, the compiler will complain, so here is what you have to remember:

1. Inside always blocks (both sequential and combinational) only reg can be used as
LHS.
2. For an assign statement, only wire can be used as LHS.
3. Inside an initial block (Testbench) only reg can be used on the LHS.
4. The output of an instantiated module can only connect to a wire.
5. Inputs
reg r; of a module cannot
reg r;be a reg. module m1 module m2
always initia (out) output (in) input
@* l out; in; reg in;
r = a begi endmodule endmodule
& b;w;
wire n
assign w = a & b; r = reg r;
1’b0; #1 m1
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r = m1_instance(.
 Testbench constructs
• Create a
clock: `define CLK_PERIOD 10

initial
begin //begins executing at
time 0 clk = 0;
end

always //begins executing at time 0 and never

stops #(CLK_PERIOD/2) clk = ~clk;

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 1 2 3 4 5
Introduction Verilog Simple FSM Coding Style
Syntax Example Implementation for RTL
s

Verilog FSM
Implementation
A simple 4-bit counter example

19
 FSM Example
• A 4-bit counter module sm
#(parameter COUNTER_WIDTH = 4)
• Receives 4 inputs: (clk,rst_n,act,up_dwn_n,count,ovf
• clk – the system clock lw);
• rst_n – an active low reset input clk;
• act – the activate signal input rst_n;
• up_dwn_n – count up input act;
(positive) input
or count down up_dwn_n;
(negative) output [COUNTER_WIDTH-1:0]
count; reg [COUNTER_WIDTH-1:0]
• Outputs 2 signals: count; output ovflw;
• count: the current counted reg ovflw;
value reg [3:0] state, next_state;
• ovflw: an overflow signal

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 FSM
Example act==1
up_dwn_n==
1
• Draw the state act==1
up_dwn_n==
machine: 1
Coun
t
reset
act== Up
0 act== act==1
count
up_dwn_n== up_dwn_n==
IDL 1
act== 1 ++ 0 Overflo
0 E act== w
0 ovflw=
Count 1
act==1
up_dwn_n== Down
0 count-
-

• Define (Enumerate) names for each act==1

up_dwn_n==
state:
localparam IDLE = 0
4'b0001; localparam
CNTUP = 4'b0010;
localparam CNTDN =
2
4'b0100; localparam
 FSM Example
• Combinational block
• Compute the next state:CNTUP:
begin if
• always @* case (act)
(state) if
(up_dwn_
• IDLE: begin if n)
(act) if
• if (up_dwn_n) (count
==(1<<
•next_state = CNTUP; else
COUNTE
•next_state = CNTDN; else
R_WIDT
• next_state = IDLE; H)-1)
next_state =
• end
OVFLW; else
next_state =
2 CNTUP; else
 FSM Example
• Combinational block
• compute the next
state:
CNTDN:
begin if
(act)
if
(up_dwn
_n) OVFLW: begin
if next_state=OVFL
(coun W;
t==(1 end
<<COU
NTER_ default: begin
WIDTH next_state =
)-1) ’bx;
next_state = $display(“%t: State machine
OVFLW; else not
next_state = initialized\n”,$time);
2
CNTUP;
 FSM Example
• Sequential block
• Define the state
registers:
always @(posedge clk or negedge
rst_n) if (!rst_n)
state <=
IDLE; else
state <=
next_state;
• Define the counter
• Finally assign the output
registers:
always @(posedge clk or negedge
rst_n) if (!rst_n) (Moore):
assign ovflw = (state==OVFLW) ? 1'b1 :
count <= 1'b0;
’b0; else
if (state==CNTUP) endmodule
count <=
count+1'b1;
else if
2
(state==CNTDN)
Testbench Example
• Definition of signals and
parameters
module sm_tb;
parameter WIDTH =
5; reg clk;
reg rst_n;
reg act;
reg
up_dwn_n;
wire [WIDTH-1:0] count;
wire ovflw;

• Instantiate the state

machine: sm #(WIDTH) DUT
(.clk(clk),.rst_n(rst_n),
.act(act),.up_dwn_n(up_dwn_n),
.count( count),.ovflw(ovflw));
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Testbench Example • Define a
• Set initial values, value clock:
always
#5 clk = ~clk;
monitoring and reset sequence: • Set
initial stimuli:
initial begin
// @100, Start counting up
begin clk
= 1'b1; // until
rst_n = overflow #100 act =
1'b0; // 1'b1;
Activate up_dwn_n =
reset 1'b1;
act = 1'b0; // Reset (10 cycles
up_dwn_n = pulse)
1'b1; #1000 rst_n = 1'b0;
act = 1'b0;
// Monitor #100 rst_n =
changes 1'b1;
$monitor("%t: // Do a
rst_n=%b act= count-up to 4 and
%b up_dwn_n=%b // then count-down to
count=%d ovflw #100 act = 1'b1;
up_dwn_n = 1'b1; 26
ovflw=%b\
 1 2 3 4 5
Introduction Verilog Simple FSM Coding Style
Syntax Example Implementation for RTL
s

Coding Style for RTL – Part

1
 HDL is NOT another programming
language!
• Well, at least it shouldn’t be…
• Verilog is a relatively “rich” programming language, with
commands
and constructs that let you do many things.
• In fact, it was originally designed exclusively as a verification
language.
• However, when designing hardware,
you cannot actually do whatever you
want!
• Therefore, it is important to follow some simple (but strict!)
rules
and adhere to a coding style.
• In the following slides:
 Organizing your code
• Each module should be in a separate file
• Name the file <modulename>.v
• Always connect modules by name (the .dot()
form).
• Write each input/output on a separate line
• Comment what each signal is used for.

• Separate sequential and combinational logic

module
fsm(...) fsm.
input ... ;
...
v
always@(pose
dge clk or
negedge
rst_)
... //
3 sequential
 Assignment
Just to make sure you got the rules I mentioned before…
• In a combinational (always@*) block:
• Always use blocking (=) assignment.
• Recommended to use (*) in your sensitivity list.
• Always use full case statements. Use default to
propagate X.
• In a sequential (always@posedge) block:
• Always use non-blocking (<=) assignment.
• Prefer each flip-flop in a separate always block.
• Prefer to data enable all sampling.
• Never assign a signal (LHS) from more than one always
3
block.
 Be careful not to infer
latches
• A very bad mistake made by rookie HDL
designers is to describe latches by mistake.
• If an output is not explicitly assigned by every
signal
latch in
willthebesensitivity
inferredlist,
to a save the
module mux4to1 (out, a, b, c, d,
previous state of the signal. sel);
output out;
• For example, what happens if input a, b, c,
d; input [1:0]
sel==11 ? sel; reg out;
always @(sel or a or b or c or
• The same will happen if an output is d)
2‘b00:
case (sel)out = a;
not assigned in all branches of an 2‘b01: out = b;
if-else block. 2‘b10: out = d;
endcas
• An if must have an else !!! e
endmodule
3
 Stick with one reset type
• The purpose of reset is to bring your design into a well-known
state.
• It
We is usually
desirable
usetoasynchronous
have every flip-flop resettable, whether
always @(posedge clk oror not
negedge
rst_) if (!rst_)
required.
reset: state <=
idle; else
state <=
next_state;
• But synchronous reset is also always @(posedge clk)
okay: if (!rst_)
state <=
idle; else
• Just make sure you don’t mix state <=
next_state;
them in your design! assign something = a && reset ;

always@*
case (state)

3
• And do not put logic on your reset 1’b1011: if (b || reset )
next_state =Adam
idle; Teman, 20 1
Parameterize your
design
• “Pretty code” is code that is completely parametrized
• Two approaches to parameterization:
• Compiler directives: `define, `include, and `ifdef
• put all `define statements in external define files.
• Parameters or localparam
• parameters can be overridden through instantiation
• localparam is better for constants, such as FSM encoding

• You can also use generate statements, but be careful of these.

• Always encode FSM states with hard coded values

• You can choose various methods, such as binary, gray code, one-
hot, etc.
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