DEPARTMENT OF INFORMATION SCIENCE & ENGINEERING

Course Name: COMPUTER ORGANIZATION AND

ARCHITECTURE
Course Code:PCC22IS42
Credits: 3:0:0
Faculty:
Dr. Radhika T V
Assistant Professor
 Module 2

Input / Output Organization: Accessing I/O Devices,

Interrupts – Interrupt Hardware, Enabling and Disabling
Interrupts, Handling Multiple Devices, Controlling Device
Requests, Exceptions
INPUT/OUTPUT
ORGANIZATION
Accessing I/O Devices
 Accessing I/O devices

Processor Memory

Bus

I/O device 1 I/O device n

•Multiple I/O devices may be connected to the processor and the memory via a bus.
•Bus consists of three sets of lines to carry address, data and control signals.
•Each I/O device is assigned an unique address.
•To access an I/O device, the processor places the address on the address lines.
•The device recognizes the address, and responds to the control signals.
 Accessing I/O devices (contd..)

There are 2 ways of addressing I/O devices

1) Memory Mapped I/O

2) I/O Mapped I/O or Standard I/O

 Accessing I/O devices (contd..)
I/O devices and the memory may share the same address space:
 Memory-mapped I/O.
 Any machine instruction that can access memory can be used to transfer data to or from an I/O device.
 Simpler software.
 For Example: if DATAIN is the address of input buffer register associated with keyboard then the instruction
Move DATAIN, R0

Similarly if DATAOUT is the address of output buffer register of display unit or printer.
Then the instruction
Move R0, DATAOUT

I/O devices and the memory may have different address spaces:
 Special instructions to transfer data to and from I/O devices.
 I/O devices may have to deal with fewer address lines.
 I/O address lines need not be physically separate from memory address lines.
 In fact, address lines may be shared between I/O devices and memory, with a control signal to indicate
whether it is a memory address or an I/O address.
7
 Accessing I/O devices (contd..)
Address lines
Bus Data lines
Control lines

Address Control Data and I/O

decoder circuits status registers interface

Input device

•I/O device is connected to the bus using an I/O interface circuit which has:
- Address decoder, control circuit, and data and status registers.
•Address decoder decodes the address placed on the address lines thus enabling the
device to recognize its address.
•Data register holds the data being transferred to or from the processor.
•Status register holds information necessary for the operation of the I/O device.
•Data and status registers are connected to the data lines, and have unique addresses.
•I/O interface circuit coordinates I/O transfers.
Cntd..
 Accessing I/O devices (contd..)

Recall that the rate of transfer to and from I/O devices is slower than
the speed of the processor. This creates the need for mechanisms to
synchronize data transfers between them.
Program-controlled I/O:
 Processor repeatedly monitors a status flag to achieve the necessary synchronization.
 Processor polls the I/O device.

Two other mechanisms used for synchronizing data transfers

between the processor and memory:
 Interrupts.
 Direct Memory Access.
Interrupts
 Interrupts

• In program-controlled I/O, when the processor continuously monitors

the status of the device, it does not perform any useful tasks.
• An alternate approach would be for the I/O device to alert the processor
when it becomes ready.
• Do so by sending a hardware signal called an interrupt to the processor.
• At least one of the bus control lines, called an interrupt-request line is dedicated for this purpose.

• Processor can perform other useful tasks while it is waiting for the device
to be ready.
 Example
• For example let us take a task that involves two activities
• Perform some computation
• Print the result

• Repeat the above two steps several times in the program, let the program contain 2
routines COMPUTE and PRINT routine.
• Method #1 :
• The COMPUTE routine passes N lines to the PRINT routine and the PRINT routine then
prints the N lines one by one on a printer.
• All this time the COMPUTE routine keeps on waiting and does not do anything useful.
• Method #2 :
• The COMPUTE routine passes N lines to the PRINT routine.
• The PRINT routine then sends one line to the printer and instead of printing that line it
execute itself and passes the control to the COMPUTE routine .
• The COMPUTE routine continuous it activity, once the line has been printed the printers
sends an interrupt to the processor of the computer.
• At this point the COMPUTE routine is suspended and the PRINT routine is activated and the
PRINT routine send second line to the printer so that the printer can keep on printing the lines
and the process continues.
 Interrupts (contd..)
Program 1 Interrupt Service routine

1
2

Interrupt
occurs i
here
i + 1

•Processor is executing the instruction located at address i when an interrupt occurs.

•Routine executed in response to an interrupt request is called the interrupt-service routine.
•When an interrupt occurs, control must be transferred to the interrupt service routine.
•But before transferring control, the current contents of the PC (i+1), must be saved in a known
location.
•This will enable the return-from-interrupt instruction to resume execution at i+1.
•Return address, or the contents of the PC are usually stored on the processor stack.
 Cntd..
• Interrupt Acknowledgement signal- A special control signal.
• Interrupt Service routine is similar to subroutine call.
• The task of saving and restoring information can be done automatically
by processor or program instructions.
• Interrupt Latency-Time delay between the time an interrupt request
received and start of execution of service routine
Interrupt Hardware
 Interrupts (contd..)

Treatment of an interrupt-service routine is very similar to that of a

subroutine.
However there are significant differences:
 A subroutine performs a task that is required by the calling program.
 Interrupt-service routine may not have anything in common with the program it interrupts.
 Interrupt-service routine and the program that it interrupts may belong to different users.
 As a result, before branching to the interrupt-service routine, not only the PC, but other information
such as condition code flags, and processor registers used by both the interrupted program and the
interrupt service routine must be stored.
 This will enable the interrupted program to resume execution upon return from interrupt service
routine.
 Interrupts (contd..)
Saving and restoring information can be done automatically by the
processor or explicitly by program instructions.
Saving and restoring registers involves memory transfers:
 Increases the total execution time.
 Increases the delay between the time an interrupt request is received, and the start of execution of the
interrupt-service routine. This delay is called interrupt latency.
In order to reduce the interrupt latency, most processors save only the
minimal amount of information:
 This minimal amount of information includes Program Counter and processor status registers.

Any additional information that must be saved, must be saved explicitly

by the program instructions at the beginning of the interrupt service
routine.
 Interrupts (contd..)

• When a processor receives an interrupt-request, it must branch to the

interrupt service routine.
• It must also inform the device that it has recognized the interrupt
request.
• This can be accomplished in two ways:
• Some processors have an explicit interrupt-acknowledge control signal for this purpose.
• In other cases, the data transfer that takes place between the device and the processor can be used to
inform the device.
 Enabling and disabling of
Interrupt
 Interrupt-requests interrupt the execution of a program, and may alter the intended sequence of events:
Sometimes such alterations may be undesirable, and must not be allowed.
For example, the processor may not want to be interrupted by the same device while executing its
interrupt-service routine.
 Processors generally provide the ability to enable and disable such interruptions as desired.
 One simple way is to provide machine instructions such as Interrupt-enable and Interrupt-disable for
this purpose.
 To avoid interruption by the same device during the execution of an interrupt service routine:
First instruction of an interrupt service routine can be Interrupt-disable.
Last instruction of an interrupt service routine can be Interrupt-enable.
 Enabling and disabling of
Interrupt
• Several Mechanism are there to handle interrupt request from single device, we will consider three
possibilities
• Using Interrupt Disable instruction as the first instruction in interrupt service routine, programmer can
ensure no further interruption can happen.
• Typically Interrupt Enable will be last instruction in the interrupt service routine.
• Processor after saving the PC contents and Processor status Register(PS), it check whether IE (Interrupt
enable bit is set or not. Interrupt request received while this bit is set is accepted.
• In the third option, processor has a special interrupt request line for which interrupt-handling hardware
responds only during leading edge of the signal. Such a line is called edge-triggered.
Interrupt Disable
----------------
-----------------
------------------
Interrupt Enable
Return
 Handling Multiple Devices

Multiple I/O devices may be connected to the processor and the memory
via a bus. Some or all of these devices may be capable of generating
interrupt requests.
 Each device operates independently, and hence no definite order can be imposed on how the devices
generate interrupt requests?
How does the processor know which device has generated an interrupt?
How does the processor know which interrupt service routine needs to
be executed?
When the processor is executing an interrupt service routine for one
device, can other device interrupt the processor?
If two interrupt-requests are received simultaneously, then how to break
the tie?
 contd..

Consider a simple arrangement where all devices send their interrupt-

requests over a single control line in the bus.
When the processor receives an interrupt request over this control line,
how does it know which device is requesting an interrupt?
This information is available in the status register of the device
requesting an interrupt:
 The status register of each device has an IRQ bit which it sets to 1 when it requests an interrupt.

Interrupt service routine can poll the I/O devices connected to the bus.
The first device with IRQ equal to 1 is the one that is serviced.
Polling mechanism is easy, but time consuming to query the status bits
of all the I/O devices connected to the bus.
 1.Vectored Interrupt

• The device requesting an interrupt may identify itself directly to the

processor.
• Device can do so by sending a special code (4 to 8 bits) the processor over the bus.
• Code supplied by the device may represent a part of the starting address of the interrupt-service routine.
• The remainder of the starting address is obtained by the processor based on other information such as the
range of memory addresses where interrupt service routines are located.

• Usually the location pointed to by the interrupting device is used to store

the starting address of the interrupt-service routine.
 contd..

Previously, before the processor started executing the interrupt

service routine for a device, it disabled the interrupts from the
device.
In general, same arrangement is used when multiple devices can
send interrupt requests to the processor.
 During the execution of an interrupt service routine of device, the processor does not accept interrupt
requests from any other device.
 Since the interrupt service routines are usually short, the delay that this causes is generally acceptable.

However, for certain devices this delay may not be acceptable.

 Which devices can be allowed to interrupt a processor when it is executing an interrupt service routine
of another device?
 2.Interrupt Nesting

• I/O devices are organized in a priority structure:

• An interrupt request from a high-priority device is accepted while the processor is executing the
interrupt service routine of a low priority device.

• A priority level is assigned to a processor that can be changed under

program control.
• Priority level of a processor is the priority of the program that is currently being executed.
• When the processor starts executing the interrupt service routine of a device, its priority is raised to
that of the device.
• If the device sending an interrupt request has a higher priority than the processor, the processor
accepts the interrupt request.
 contd..

• Processor’s priority is encoded in a few bits of the processor status

register.
• Priority can be changed by instructions that write into the processor status register.
• Usually, these are privileged instructions, or instructions that can be executed only in the supervisor
mode.
• Privileged instructions cannot be executed in the user mode.
• Prevents a user program from accidentally or intentionally changing the priority of the processor.

• If there is an attempt to execute a privileged instruction in the user

mode, it causes a special type of interrupt called as privilege
exception.
 Interrupt Nesting contd..

IN T R 1 IN T R p
Processor
Device 1 Device 2 Device p

INTA1 INTA p

Priority arbitration

•Each device has a separate interrupt-request and interrupt-acknowledge line.

•Each interrupt-request line is assigned a different priority level.
•Interrupt requests received over these lines are sent to a priority arbitration circuit
in the processor.
•If the interrupt request has a higher priority level than the priority of the processor,
then the request is accepted.
 cntd..

Which interrupt request does the processor accept if it receives

interrupt requests from two or more devices simultaneously?.
If the I/O devices are organized in a priority structure, the processor
accepts the interrupt request from a device with higher priority.
 Each device has its own interrupt request and interrupt acknowledge line.
 A different priority level is assigned to the interrupt request line of each device.

However, if the devices share an interrupt request line, then how

does the processor decide which interrupt request to accept?
 Simultaneous Request
Polling scheme:
•If the processor uses a polling mechanism to poll the status registers of I/O devices
to determine which device is requesting an interrupt.
•In this case the priority is determined by the order in which the devices are polled.
•The first device with status bit set to 1 is the device whose interrupt request is
accepted.
Daisy chain scheme:
IN TR
Processor

Device 1 Device 2 Device n

INTA

•Devices are connected to form a daisy chain.

•Devices share the interrupt-request line, and interrupt-acknowledge line is connected
to form a daisy chain.
•When devices raise an interrupt request, the interrupt-request line is activated.
•The processor in response activates interrupt-acknowledge.
•Received by device 1, if device 1 does not need service, it passes the signal to device 2.
•Device that is electrically closest to the processor has the highest priority.
 Interrupts (contd..)
•When I/O devices were organized into a priority structure, each device had its own
interrupt-request and interrupt-acknowledge line.
•When I/O devices were organized in a daisy chain fashion, the devices shared an
interrupt-request line, and the interrupt-acknowledge propagated through the devices.
•A combination of priority structure and daisy chain scheme can also used.
IN T R 1

Device Device
INTA1
Processor

IN T R p

Device Device
INTA p
Priority arbitration
circuit
•Devices are organized into groups.
•Each group is assigned a different priority level.
•All the devices within a single group share an interrupt-request line, and are
connected to form a daisy chain.
Controlling Device Request
Only those devices that are being used in a program should be allowed to generate
interrupt requests.
To control which devices are allowed to generate interrupt requests, the interface
circuit of each I/O device has an interrupt-enable bit.
 If the interrupt-enable bit in the device interface is set to 1, then the device is allowed to generate an interrupt-
request.

Interrupt-enable bit in the device’s interface circuit determines whether the device
is allowed to generate an interrupt request.
Interrupt-enable bit in the processor status register or the priority structure of the
interrupts determines whether a given interrupt will be accepted.
Cntd..
Cntd..
 Exceptions

Interrupts caused by interrupt-requests sent by I/O devices.

Interrupts could be used in many other situations where the execution of
one program needs to be suspended and execution of another program
needs to be started.
In general, the term exception is used to refer to any event that causes an
interruption.
 Interrupt-requests from I/O devices is one type of an exception .

Other types of exceptions are:

 Recovery from errors
 Debugging
 Privilege exception
 Exceptions (contd..)
Many sources of errors in a processor. For example:
 Error in the data stored.
 Error during the execution of an instruction.

When such errors are detected, exception processing is initiated.

 Processor takes the same steps as in the case of I/O interrupt-request.
 It suspends the execution of the current program, and starts executing an exception-service routine.

Difference between handling I/O interrupt-request and handling

exceptions due to errors:
 In case of I/O interrupt-request, the processor usually completes the execution of an instruction in
progress before branching to the interrupt-service routine.
 In case of exception processing however, the execution of an instruction in progress usually cannot be
completed.
 Exceptions (contd..)
• Debugger uses exceptions to provide important features:
• Trace,
• Breakpoints.

• Trace mode:
• Exception occurs after the execution of every instruction.
• Debugging program is used as the exception-service routine.

• Breakpoints:
• Exception occurs only at specific points selected by the user.
• Debugging program is used as the exception-service routine.
 Exceptions (contd..)

• Certain instructions can be executed only when the processor is in the

supervisor mode. These are called privileged instructions.
• If an attempt is made to execute a privileged instruction in the user mode,
a privilege exception occurs.
• Privilege exception causes:
• Processor to switch to the supervisor mode,
• Execution of an appropriate exception-servicing routine.
 References

[1] Carl Hamacher, Zvonko Vranesic, SafwatZaky: Computer Organization, 5th Edition,
Tata McGraw Hill, 2017

17/01/2025 Department of Information Science & Engineering 42

 THANK YOU

17/01/2025 Department of Information Science & Engineering 43