CHAPTER 2: Verilog Syntax,

Structural Verilog and Timing

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 Syllabus

Week Content Notes

1 Chapter 0: Course Introduction (1)
Chapter 1: Introduction of Verilog and FPGA (2)
2 Chapter 2: Verilog Syntax, Structural Verilog and Timing (3)
3, 4 Chapter 3: Testbench, Dataflow and Behavioral Verilog (6)
5 Chapter 4: Counters, Shifters/Rotators, Parameters (3)
6 Chapter 5: Handy Testbench Constructs (3)
7 Midterm Exam Practice (3)
8 Midterm Exam (3)
9, 10 Chapter 6: Finite State Machine (FSM) in Verilog (6)

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 Administrative Matters
 Reading
• [2] Chapter 3 (Basic Concepts – Verilog HDL)
• [2] Chapter 4 (module and port declaration, hierarchical naming)
• [2] Chapter 5 (structural module, gate primitives, delays)
• Slides Chapter 2 (Canvas)
 Homework
• Homework 1
 Project
• Team up and topic selection after Chapter 3

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 Content
1.Comments
2.Numbers
3.Signals
4.Data Types
5.Parameters and Define
6.Structural Verilog
7.Module Ports
8.Timing and Delay
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 1. Comments
 Commenting is important
• In industry many other peoples are going to read your code
• Some people (perhaps you many years later) are going to have to
reference your code when a customer discovers a bug.

 The best comments document why you are doing what you are
doing, not what you are doing
• Any people who knows Verilog can tell what the code is doing
• Comment why (motivation/thought process) you are doing that
thing

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 1. Comments

 Not recommend! You comment what the code did!

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 1. Comments

 This is better commenting. It tells you why stuff was done!

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 2. Numbers
 General format is: <size>’<base><number>
 Examples:
• 4’b1101 // This is a 4-bit binary number equal to 13
• 10’h2e7 // This is a 10-bit wide number specified in hex

 Available base:
• d = decimal (please only use in test benches)
• h = hex (use this frequently)
• b = binary (use this frequently for smaller #’s)
• o = octal (rarely, please avoid)

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 2. Numbers
 Numbers can have x or z characters as values
• x = unknown, z = High Impedance
• 12’h13x // 12-bit number with lower 4-bits unknown
 If size is not specified then it depends on simulator/machine (must be
at least 32 bits).
• Always size the number for the Design Under Test (DUT) Verilog
 Supports negative numbers as well
• -16’h3A // this would be -3A in hex (i.e. FFC6 in 2’s complement)
 Underscore and question marks
• Underscore “_” is allowed anywhere except the first character. Example:
12’b1011_0011_0110
• Question mark “?” substitutes for x in the context of number.
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 3. Signals
 Identifiers are the names you choose for your signal
 Some Rules
• Case sensitivity
• Start with alphabetic character or an underscore
• Can not start with a digit or a $
 You should choose descriptive variable names and signal names.
• Use mixed case and/or _ to delimit descriptive names
• Have a convention for signals that active low
 Many errors occur on the interface between blocks written by 2 or more different
people. One assumed a signal was active low, and the other assumed it was active high.
 Use _n at the end of a signal to indicate active low
 For example: rst_n = 1’b0 // active low reset signal 10
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 3. Signals
 Signals can have 1 of 4 values

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 3. Signals
 Resolving 4-Value Logic

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 4. Data Types
 Nets
• Represent the connection between hardware element.
• Have values continuously driven on the outputs of the device they are
connected to.
• Declared primarily with keyword wire
• Default values are z.
b a
c
a=b&c

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 4. Data Types
 Registers are storage nodes
• A variable that can hold a value until another value is place on it.
• Can be changed in simulation by assigning a new value
• Declared by the keyword reg.
• Default value is x.

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 4. Data Types
 Registers are not necessarily flip-flops
• Do not confuse the term registers in Verilog with hardware registers.
• Verilog register do not need a clock as hardware register do.
• In your Design Unit Test (DUT) Verilog registers are typically flip-flops
• Anything assigned in an always or initial block must be assigned to a
register.
• A wire can connect with a reg, but a reg cannot.
• You will use registers in your testbenches, but they will not be flip-flops

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 4. Data Types
 Vectors are a collection of wire or reg data types (i.e. 16-bit wide of
nets of reg data types)
 Vector can be declared at [high# : low#] or [low# : high#], but the left
number is always the most significant bit (MSB) of the vectors

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 4. Data Types
 Can be select parts of a vector (single bit or a range)

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 4. Data Types
 Array
• Allows in Verilog for reg, integer, time, and vector register data types
and does not allow for real variables.
• <array_name>[<subscript>]
• Multidimensional arrays is not permitted.
• A vector is a single element that is n-bits wide, whereas arrays are
multiple elements that are 1-bit or n-bit wide.

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 4. Data Types
 Integer
• General purpose register data type with the keyword integer
• Default width depends on the machine (usually al least 32-bit)
• reg can only stores unsigned values, whereas integer stores signed values
 String
• Can be stored in reg. The width of the reg variables must be large enough to
hold the string
• Each character in the string takes up 8 bits (1 byte).
 Time
• It is the simulation time with the keyword time.
• The system function $time get the current simulation time.

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 4. Data Types
 Can have multi-dimensional arrays
• reg [7:0] mem[0:99][0:3]; // what is this?
 Often have a model memories
• SRAM, ROM, Flash, Cache
• Memories can be useful in your test bench

ALU: Arithmetic Logic Unit

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 5. Parameters and Define
 Parameters are useful to make your code more generic/flexible.
Read about it in text.
 `define statement can make code more readable

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 5. Parameters and Define

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 Useful System Tasks
 $display : Like printf in C. Useful for testbenches and debug

 $monitor: Monitor the variable and whenever the value changes

it will print it
 $stop: Stops simulation and allows you to still probe signals and
debugs
 $finish: completely stops simulation, simulator relinquishes
control of thread
 Also useful is `include for including code from another file (like
a header file)
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 Primitives
 Build design up from the gate/flip-flop/latch level
• Structural Verilog is netlist of blocks and connectivity

 Verilog provides a set of gate primitives

• and, or, not, nand, nor, xor, xnor, buf, bufifl, etc
• Combination building blocks for structural design
• Know “behavior”
• Cannot access “inside” description

 Can also model at the transistor level

• Too complicated! We won’t.

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 Primitives

 No declarations – can only be instantiated

 Output port appears before input ports
 Optionally specify: instance name and/or delay (discuss delay later)

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 6. Structural Verilog
 Any Verilog design you do will be a module
 This includes testbenches!

 Interface (“black box” representation)

• Module name, ports
 Definition
• Describe functionality of the block
 Instantiation
• Use the module inside another module

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 6. Structural Verilog
 Build up a module from smaller pieces
 Design: typically top-down
 Verification: typically bottom-up

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 6. Structural Verilog
 Build up a module from smaller pieces

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 6. Structural Verilog

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 6. Structural Verilog

 You can use other types of Verilog modules to build the structure
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 6. Structural Verilog
 Verilog Module Hierarchy
• Every module instance, signal, or variable is defined with an identifier.
The identifier can be declared only one time.
• A hierarchical name is a list identifiers separated by dots (“.”) for each
level of hierarchy.
• This is useful generally in testbench coding, in a somewhat backdoor way,
in a different module within your testbench.

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 6. Structural Verilog
 Parent cannot access “internal” signals of child
 Can have all modules in a single file
• Module order doesn’t matter!
• Good for small designs
• Not so good for bigger ones
• Not so good for module reuse (cut & paste)
 Can break up modules into multiple files
• Helps with organization
• Let’s you find a specific module easily
• Good for module reuse (add file to project)

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 6. Structural Verilog
 Connection: Positional or Connect by Order
• Can be okay in some situations
 Designs with very few ports
 Interchangeable input ports (and/or/xor gate inputs)
• Get confusing for large numbers of ports

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 6. Structural Verilog
 Connection: Explicit or Connect by name method
• Help avoid “misconnections”
• Don’t have to remember port order
• Can be easier to read
• .<port name>(signal name)

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 7. Module Ports
 Ports provide the interface by which a module can communicate with
other modules.
 List of ports is an optional in a module. If the module does not exchange
signals with any, there are no ports in the list.

 Module Top is a top-level module and module fulladd4 is instantiated

below Top.
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 7. Module Ports
 Multiple ways to declare the ports of a module

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 7. Module Ports
 All ports declarations are implicitly declared as wire.
 Ports of the type input and inout cannot be declared as reg because
input ports should not store value.

 input ports only reflect the changes in the external signals they are
connected to.
 However, if output ports hold a value, they must be declared as reg.

 Example: in the definition of D Filp-flop (DFF), we want to the

output q to remain its values until the next clock edge.
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 7. Module Ports
 input ports can be connected to a variable which is a reg or a net.
 output ports must always be connected to a net, cannot be connected
to a reg.

 inout ports must always be of the type wire and connected to a net.
 Two items with different sizes can be connected but there is a
warning.
 Verilog allows ports to remain unconnected.

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 7. Module Ports
 Example of illegal port connection

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 8. Timing and Delay
 Can put “delay” in a Verilog design
• Gates, wires, and behavior statements
 Delays are useful for Simulation only!
• Used to approximate ”real” operation while simulating
• Used to control testbench
 SYSTHESIS
• Systhesis tool IGNORES these timing controls
 Cannot tell a gate to wait 1.5 nanoseconds
 Delay is a results of physical properties

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 8. Timing and Delay
 When no timing controls specified: zeros delay
• Unrealistic – even electrons take time to move
• OUT is updated same time A and/or B change:
and A0(OUT, A, B);
 Unit delay often used
• No accurate either, but closer ...
• “Depth” of circuit does affect speed!
• Easier to see how changes propagate through circuit
• OUT is updated 1 “unit” timing after A and/or B change:
and #1 A0(OUT, A, B);

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 8. Timing and Delay
 Example

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 8. Timing and Delay
 Types Of Delays: Inertial Delay (Gates)
• Suppresses pulses shorter than delay amount
• In reality, gates need to have inputs held a certain time before output
is accurate (hold time).
 Types Of Delays: Transport Delay (Nets)
• “Time of flight” from source to sink
• Short pulses transmitted
 Not critical for our project, however, in industry

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 8. Timing and Delay
 wire #5 net_1; // 5 unit transport delay

 and #4 (z_out, x_in, y_in); // 4 unit inertial delay

 assign #3 z_out = a & b; // 3 unit inertial delay

 wire #2 z_out; // 2 unit transport delay

 and #3 (z_out, x_in. y_in); // 3 for gate, 2 for wire

 wire #3 c; // 3 unit transport delay

 assign #5 c = a & b; // 5 for assign, 3 for wire

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 Summary
 Comments should show why you are doing what you are
doing, not what you are doing
 <size>’<base><number>. Available base: d, h, b, o
 Identify the components of a Verilog module definition such
as module names, port lists, comments, numbers, signals, and
parameter declaration.
 Understand how to connect ports to external signals, by
ordered list, and by name
 Hierarchy: design (top-down), verification (bottom-up)

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