INSTRUCTIO

N SETS
INSTRUCTIONS
Instructions: Language of the Machine
Instruction set architecture - the attributes of
a computer system seen by the programmer
Attributes
🢝organization of programmable storage
🢝data types and data structures, encodings, representations
🢝instruction format, operands
🢝instruction set (operation code set)
🢝addressing modes, accessing data items and instructions
🢝exceptional (interrupt) conditions
THE ISA

Instruction Set Architecture

🢝The ISA defines the CPU, or a CPU family (e.g.
x86)
🢝not only a collection of instructions,
🢝includes the CPU view of memory, registers number and roles, etc.
🢝The ISA is the contact between s/w and h/w

ISA ≠ CPU architecture (μ-architecture)

🢝E.g x86: Xeon ≠ Celeron, same ISA
RISC VS CISC
RISC (reduced instruction set computer)
instructions
🢝only load/store instructions access memory
🢝data (i.e., operands) must be in registers to perform operation
🢝each instruction roughly taking same amount of time
🢝simple addressing modes
🢝etc.

CISC (complex instruction set computer)

instructions
🢝alu/logic instructions access memory to fetch operands
🢝load/store instructions access memory
🢝some instructions’ execution time is much longer than other
instructions
🢝complex addressing modes
🢝etc.
INSTRUCTION SETS

MIPS/MIPS-like ISA (RISC)

Simple, sensible, regular, easy to design
CPU
Most common: x86 and ARM (CISC)
x86: Intel Pentium/Core i7, AMD Athlon, etc.
ARM: cell phones, embedded systems
Others:
PowerPC (IBM servers)
SPARC (Sun)

5
PROCEDURE CALLING

Steps required
1. Place parameters in registers
2. Transfer control to procedure
3. Acquire storage for procedure
4. Perform procedure’s operations
5. Place result in register for caller
6. Return to place of call
TRANSLATION AND
STARTUP
Many compilers produce
object modules directly

Static linking
 STARTING JAVA
APPLICATIONS
Simple
portable
instruction set
for the JVM

Compiles
Interprets
bytecodes of
bytecodes
“hot”
methods into
native code
for host
machine
MIPS ISA
MIPS ARCHITECTURE
MIPS – semiconductor
company that built
one of the first
commercial RISC
architectures
MIPS widely used in
embedded apps
Almost 100 million MIPS
processors manufactured in
2002
Used by NEC, Nintendo,
Cisco, Silicon Graphics, Sony,
…
MIPS ARCHITECTURE
32-bit RISC Processor
32-bit Registers, $0..$31
Pipelined Execution of Instructions
All instructions are 32-bits
Most Instructions executed in one clock cycle
230 32-bit memory words
Byte addressable memory
🢝A 32-bit word contains four bytes
🢝To address the next word of memory add 4
ARM & MIPS ISA
ARM & MIPS SIMILARITIES
ARM: the most popular embedded core
Similar basic set of instructions to MIPS

ARM MIPS
Date announced 1985 1985
Instruction size 32 bits 32 bits
Address space 32-bit flat 32-bit flat
Data alignment Aligned Aligned
Data addressing modes 9 3
Registers 15 × 32-bit 31 × 32-bit
Input/output Memory Memory
mapped mapped
ISA COMPARISON
COMPARE AND BRANCH
IN ARM
Uses condition codes for result of an
arithmetic/logical instruction
🢝Negative, zero, carry, overflow
🢝Compare instructions to set condition codes
without keeping the result

Each instruction can be conditional

🢝Top 4 bits of instruction word: condition value
🢝Can avoid branches over single instructions
INSTRUCTION ENCODING
ARM & MIPS
ADDRESSING MODES
ARM ARITHMETIC NOT IN
MIPS
INTEL X86 ISA
THE INTEL X86 ISA
Evolution with backward compatibility
🢝8080 (1974): 8-bit microprocessor
🢝Accumulator, plus 3 index-register pairs
🢝8086 (1978): 16-bit extension to 8080
🢝Complex instruction set (CISC)
🢝8087 (1980): floating-point coprocessor
🢝Adds FP instructions and register stack
🢝80286 (1982): 24-bit addresses, MMU
🢝Segmented memory mapping and protection
🢝80386 (1985): 32-bit extension (now IA-32)
🢝Additional addressing modes and operations
🢝Paged memory mapping as well as segments
THE INTEL X86 ISA
Further evolution…
🢝i486 (1989): pipelined, on-chip caches and FPU
🢝Compatible competitors: AMD, Cyrix, …
🢝Pentium (1993): superscalar, 64-bit datapath
🢝Later versions added MMX (Multi-Media eXtension) instructions
🢝The infamous FDIV bug
🢝Pentium Pro (1995), Pentium II (1997)
🢝New microarchitecture (see Colwell, The Pentium Chronicles)
🢝Pentium III (1999)
🢝Added SSE (Streaming SIMD Extensions) and associated registers
🢝Pentium 4 (2001)
🢝New microarchitecture
🢝Added SSE2 instructions
THE INTEL X86 ISA
And further…
🢝AMD64 (2003): extended architecture to 64 bits
🢝EM64T – Extended Memory 64 Technology (2004)
🢝AMD64 adopted by Intel (with refinements)
🢝Added SSE3 instructions
🢝Intel Core (2006)
🢝Added SSE4 instructions, virtual machine support
🢝AMD64 (announced 2007): SSE5 instructions
🢝Intel declined to follow, instead…
🢝Advanced Vector Extension (announced 2008)
🢝Longer SSE registers, more instructions

If Intel didn’t extend with compatibility, its competitors

would!
🢝Technical elegance ≠ market success
BASIC X86 REGISTERS
BASIC X86 ADDRESSING
MODES
Two operands per instruction
Source/dest operand Second source operand
Register Register
Register Immediate
Register Memory
Memory Register
Memory Immediate

■Memory addressing modes

■Address in register
■Address = Rbase + displacement
■Address = Rbase + 2scale × Rindex (scale = 0, 1, 2,
or 3)
X86 INSTRUCTION
ENCODING
Variable length
encoding
🢝Postfix bytes specify
addressing mode
🢝Prefix bytes modify
operation
🢝Operand length, repetition,
locking, …
MIPS ISA
MIPS ISA

Design principles
🢝small, regular & simple design 🡺 fast
🢝make the common case fast
🢝good design requires good compromises

Features
🢝32 32-bit registers, r0 = 0 always
🢝only load and store instructions access memory
🢝32-bit instructions, fixed size opcode, leftmost 6 bits
🢝 fixed-field decoding
🢝all ALU operations are 3 address register operations
🢝 add r1, r2, r3, meaning: r1 🡸 r2 + r3
REGISTERS

32 general-purpose registers.
Registers all begin with a dollar-
symbol ($)
32 floating-point registers. The
floating-point registers are named
$f0, $f1, ..., $f31.
When programming in MIPS
assembly, it is usually best to use
the register names.
28
REGISTERS
Number Name Comments
$0 $zero Always zero
$1 $at Reserved for assembler
$2, $3 $v0, $v1 First and second return values, respectively
$4, ..., $7 $a0, ..., $a3 First four arguments to functions
$8, ..., $15 $t0, ..., $t7 Temporary registers
$16, ..., $23 $s0, ..., $s7 Saved registers
$24, $25 $t8, $t9 More temporary registers
$26, $27 $k0, $k1 Reserved for kernel (operating system)
$28 $gp Global pointer
$29 $sp Stack pointer
$30 $fp Frame pointer
$31 $ra Return address
29
MIPS POLICY

Only Load instruction can read an

operand from memory
Only Store instruction can write an
operand to memory
Typcial RISC calculations require
🢝Load(s) to get operands from memory into registers
🢝Calculations performed only on values in registers
🢝Store(s) to write result from register back to
memory
MIPS INSTRUCTION
FORMATS
R format - Uses three register
operands
🢝Used by all arithmetic and logical instructions

I format - Uses two register operands

and an address/immediate value
🢝Used by load and store instructions
🢝Used by arithmetic and logical instructions with a
constant

J format - Contains a jump address

🢝Used by Jump instructions
MIPS INSTRUCTION
FORMATS
32-bit Instruction Formats R, I
and op
J rs rt rd shamt funct

R 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

op rs rt immediate or offset

I 6 bits 5 bits 5 bits 16 bits

op address

J 6 bits 26 bits
MIPS R-FORMAT
INSTRUCTIONS
op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

R(register)-format Instruction fields

🢝op: operation code (opcode) is always zero
🢝rs: first source register number
🢝rt: second source register number
🢝rd: destination register number
🢝shamt: shift amount (00000 for now)
🢝funct: function code (extends opcode)

Used only for ALU instructions

R-FORMAT EXAMPLE
op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

add $r8, $r17, $r18 #$r8=$r17+$r18

special $r17 $r18 $r8 0 add

0 17 18 8 0 32

000000 10001 10010 01000 00000 100000

000000100011001001000000001000002 =
0232402016
MIPS I-FORMAT
INSTRUCTIONS
op rs rt immediate or offset
6 bits 5 bits 5 bits 16 bits

I(immediate)-format Instructions
Immediate arithmetic and load/store instructions
🢝rs: source register number
🢝rt: destination register number
🢝Constant: –215 to +(215 – 1), used as immediate
🢝Address: offset added to base address in rs
I-FORMAT EXAMPLE:
ADDI
op rs rt immediate or offset
6 bits 5 bits 5 bits 16 bits

addi $r8,$r17, 8 #$r8🡸8+$r17

addi $r17 $r8 constant or address

810 17 8 8

001000 10001 01000 0000000000001000

001000100010100000000000000010002 =
22280008
I-FORMAT EXAMPLE:
LOAD
op rs rt immediate or offset
6 bits 5 bits 5 bits 16 bits

lw $r8, 8($r17) #$r8🡸Mem[8+$r17]

lw $r17 $r8 constant or address

3510 17 8 8

100011 10001 01000 0000000000001000

100011100010100000000000000010002 =
8E28000816
I-FORMAT EXAMPLE:
STORE
op rs rt immediate or offset
6 bits 5 bits 5 bits 16 bits

sw $r8, 8($r17) #Mem[8+$r17]🡸$r8

sw $r17 $r8 constant or address

4310 17 8 8

101011 10001 01000 0000000000001000

101011100010100000000000000010002 =
I-FORMAT EXAMPLE:
BEQ
op rs rt offset
6 bits 5 bits 5 bits 16 bits

beq $r8,$r17, 8 if ($r8==$r17) PC 🡸 PC+4+8

beq $r17 $r8 offset

410 17 8 8

000100 10001 01000 0000000000001000

000100100010100000000000000010002 =
1228000816
MIPS J-FORMAT
INSTRUCTIONS
op address
6 bits 26 bits

J(jump)-format instructions are used to transfer

program flow to a given hardcoded absolute
address within the 256MB region
J instructions are almost always written with labels:
the assembler and linker will convert the label into
a numerical value.
A J instruction takes only one argument: the
address to jump to.
JUMP ADDRESSING
Jump (j and jal) targets could be anywhere
in text segment
🢝Encode full address in instruction

op address
6 bits 26 bits

■(Pseudo)Direct jump addressing

■Target address = PC31…28 : (address ×
4)
TARGET ADDRESSING
EXAMPLE
Loop code from earlier example
🢝Assume Loop at location 80000

Loop: sll $t1, $s3, 2 80000 0 0 19 9 4 0

add $t1, $t1, $s6 80004 0 9 22 9 0 32
lw $t0, 0($t1) 80008 35 9 8 0
bne $t0, $s5, Exit 80012 5 8 21 2
addi $s3, $s3, 1 80016 8 19 19 1
j Loop 80020 2 20000
Exit: … 80024
MIPS ADDRESSING
MODES
Register - Uses value in register as operand
🢝Example $2 - Uses register 2 as operand

Direct Address - Uses value stored in memory at given

address
🢝Example 100 - Uses value stored at location 100 in memory as operand

Register Indirect Address - Uses value in register as

address of operand in memory
🢝Example ($3) - Uses value in register 3 as address of memory operand

Indexed Address - Adds address field and register

value and uses this as address of operand in memory
🢝Example 100($2) - Adds 100 to the value in register 2 and reads the
operand from the resulting memory address
🢝Used for array X[I] operations, the array index is normally in the register
and the address field is the first location in the array
MIPS ADDRESSING
MODES
Immediate Addressing - Uses constant
value contained in instruction
🢝Example addi $1,$2,4 - adds constant 4 to
register 2 and stores result in register 1
🢝Used for constants in programs

PC relative - Address from instruction

is added to the current value in the
Program Counter
🢝Example J 4 - Jumps to address PC+4
🢝Saves address bits in jump instructions
ADDRESSING MODES

There are many ways of accessing

operands
Register addressing:
add $1, $2, $3
op r r r ... func
s t d t

register
 ADDRESSING MODES
Base addressing (aka displacement)
lw $1, 100($2) # $2 == 400, M[500]
op== 42
r r Offset/
s t displacement
registe 10
r 0
40 Memor
0 y
Effective
4
addres 2
s
ADDRESSING MODES

Immediate addressing
addi $1, $2, 100
op r r immediate
s t
 ADDRESSING MODES
PC relative addressing
beq $1, $2, 100 # if ($1==$2) PC = PC + 100
op r r addres
s t s
PC
Memor
y
Effective
addres
s
4
MIPS ARITHMETIC AND
LOGICAL INSTRUCTIONS

ADD $1,$2,$3
🢝Register 1 = Register 2 + Register 3

SUB $1,$2,$3
🢝Register 1 = Register 2 - Register 3

AND $1,$2,$3
🢝Register 1 = Register 2 AND Register 3

ADDI $1,$2,10
🢝Register 1 = Register 2 + 10

SLL $1, $2, 10

🢝Register 1 = Register 2 shifted left 10 bits
MIPS LOAD/STORE
INSTRUCTIONS
LW $1,100
🢝Register 1 = Contents of memory location 100
🢝Used to load registers

SW $1,100
🢝Contents of memory location 100 = Register 1
🢝Used to save registers

LUI $1,100
🢝Register 1 upper 16-bits = 100
🢝Lower 16-bits are set to all 0’s
🢝Used to load a constant in the upper 16-bits
🢝Other constants in instructions are only 16-bits, so this
instruction is used when a constant larger than 16-bits is
required for the operation
MIPS JUMP
INSTRUCTIONS
J 100
🢝Jumps to PC+100

JAL 100
🢝Save PC in $31 ($ra: Return address) and
Jumps to PC+100
🢝Used for subroutine calls

JR $31
🢝Jumps to address in register 31
🢝Used for subroutine returns
MIPS BRANCH
INSTRUCTIONS
BEQ $1, $2, 100
🢝If register 1 equal to register 2 jump to
PC+100
🢝Used for Assembly Language If statements

BNE $1, $2, 100

🢝If register 1 not equal to register 2 jump to
PC+100
🢝Used for Assembly Language If statements
MIPS CONDITION
INSTRUCTIONS
SLT $1,$2,$3
🢝If register 2 is less than register 3 then
register 1=1 else register 1=0
🢝In an assembly language flag a “1” means
true and a “0” means false
🢝Used in conjunction with Bxx instruction to
implement any arithmetic comparision
🢝Required for more complex assembly
language If statements
SYSTEM CALL: SYSCALL
I/O Call Code Arguments or Result
print int $v0=1 $a0 = integer
print float $v0=2 $f12 = float
print double $v0=3 $f12 = double
print string $v0=4 $a0 = string address
read int $v0=5 Integer (in $v0 )
read float $v0=6 float (in $f0 )
read double $v0=7 double (in $f0 )
read string $v0=8 $a0 = buffer, $a1 = length
sbrk $v0=9 $a0 = amount, address in
$v0
exit $v0= 10
EXAMPLE

1. Write a program to print on the

screen number from 1-9.
2. Write a program, using the MIPS
32 assembly language,
🢝To calculate the sum of the first 100
numbers. The result must be stored in
register $v0.
🢝Print the result.

55
MIPS LABELS

Instead of absolute memory addresses

symbolic labels are used to indicate
memory addresses in assembly language
Assembly Language Programs are easier
to modify and are easier to understand
when labels are used
🢝Examples
🢝Variable X is stored a location 123 in memory - Use
label X instead of 123 in programs.
🢝Location LOOP_TOP is address 250 in a program - Use
label LOOP_TOP instead of jump address 250 in
programs
MIPS ASSEMBLER
DIRECTIVES
Assembler directives are
commands for the assembler that
do not generate machine
instructions
Assembler directives are also
called pseudo ops
Used to set up data and
instruction areas
MIPS ASSEMBLER
DIRECTIVE EXAMPLES
.DATA
🢝The following lines are constant or data values

.WORD
🢝Reserve a 32-bit word in memory for a variable

.ASCII
🢝Place a string in memory using the ASCII
character code

.TEXT
🢝The following lines are instructions
 MIPS EXAMPLES
main: lw $t0, size
.data # "data section" global, static
la $t1, arr1
modifiable data
Loop: beq $0, $t0, Exit
la $a0, msg1
arr1: .word 100, 101, 102 li $v0, 4 # "print string" system call
syscall
size: .word 3
nl: .asciiz "\n" lw $a0, ($t1)
li $v0, 1 #Print int
msg1: .asciiz "Hello, World "
syscall
.text # "text section" code and read-
la $a0, nl
only data
li $v0, 4 # "print string" system call
syscall

.globl main # declare `main' as a

add $t0, $t0, -1
global symbol addi $t1, $t1, 4 # advance array pointer
j Loop

Exit:
60
MIPS EXAMPLES

#A = B + C;
LW $2, B #Register 2 = value of
B
LW $3, C #Register 3 = value of
C
ADD $4, $2, $3 #Register 4 =
B+C
SW $4, A #A = B + C
MIPS EXAMPLES

# f=(g+h)-(i+j);
# compiler puts f,g,h,i in
# $16,$17,$18,$19,$20
add $8,$17,$18 # $8 =g+h
add $9,$19,$20 #9=i+j
sub $16,$8,$9 # $16=(g+h)-(i+j)
MIPS EXAMPLES

#if (i==j) f=g+h; else f=g-h;

Bne $19,$20,Else
Add $16,$17,$18
J Exit
Else: sub $16,$17,$18
Exit:
MIPS EXAMPLES

#for loop
ADDI $5,$0,10
Loop: …
…
…
ADDI $5,$5,-1
BNE $5,$0,Loop
C SORT EXAMPLE

Illustrates use of assembly instructions

for a C bubble sort function
Swap procedure (leaf)
void swap(int v[], int k)
{
int temp;
temp = v[k];
v[k] = v[k+1];
v[k+1] = temp;
}
🢝v in $a0, k in $a1, temp in $t0
THE PROCEDURE SWAP

MIPS code:
swap: sll $t1, $a1, 2 # $t1 = k * 4
add $t1, $a0, $t1 # $t1 = v+(k*4)
# (address of v[k])
lw $t0, 0($t1) # $t0 (temp) = v[k]
lw $t2, 4($t1) # $t2 = v[k+1]
sw $t2, 0($t1) # v[k] = $t2 (v[k+1])
sw $t0, 4($t1) # v[k+1] = $t0 (temp)
jr $ra # return to calling routine
THE SORT PROCEDURE
IN C
Non-leaf (calls swap)
void sort (int v[], int n)
{
int i, j;
for (i = 0; i < n; i += 1) {
for (j = i – 1;
j >= 0 && v[j] > v[j + 1];
j -= 1) {
swap(v,j);
}
}
}
🢝v in $a0, n in $a1, i in $s0, j in $s1
THE PROCEDURE BODY
move $s2, $a0 # save $a0 into $s2
move $s3, $a1 # save $a1 into $s3
move $s0, $zero #i=0
for1tst: slt $t0, $s0, $s3 # $t0 = 0 if $s0 ≥ $s3 (i ≥ n)
beq $t0, $zero, exit1 # go to exit1 if $s0 ≥ $s3 (i ≥ n)
addi $s1, $s0, –1 #j=i–1
for2tst: slti $t0, $s1, 0 # $t0 = 1 if $s1 < 0 (j < 0)
bne $t0, $zero, exit2 # go to exit2 if $s1 < 0 (j < 0)
sll $t1, $s1, 2 # $t1 = j * 4
add $t2, $s2, $t1 # $t2 = v + (j * 4)
lw $t3, 0($t2) # $t3 = v[j]
lw $t4, 4($t2) # $t4 = v[j + 1]
slt $t0, $t4, $t3 # $t0 = 0 if $t4 ≥ $t3
beq $t0, $zero, exit2 # go to exit2 if $t4 ≥ $t3
move $a0, $s2 # 1st param of swap is v (old $a0)
move $a1, $s1 # 2nd param of swap is j
jal swap # call swap procedure
addi $s1, $s1, –1 # j –= 1
j for2tst # jump to test of inner loop
exit2: addi $s0, $s0, 1 # i += 1
j for1tst # jump to test of outer loop
THE FULL PROCEDURE
sort: addi $sp,$sp, –20 # make room on stack for 5
registers
sw $ra, 16($sp) # save $ra on stack
sw $s3,12($sp) # save $s3 on stack
sw $s2, 8($sp) # save $s2 on stack
sw $s1, 4($sp) # save $s1 on stack
sw $s0, 0($sp) # save $s0 on stack
… # procedure body
…
exit1: lw $s0, 0($sp) # restore $s0 from stack
lw $s1, 4($sp) # restore $s1 from stack
lw $s2, 8($sp) # restore $s2 from stack
lw $s3,12($sp) # restore $s3 from stack
lw $ra,16($sp) # restore $ra from stack
addi $sp,$sp, 20 # restore stack pointer
jr $ra # return to calling routine
ARRAYS VS. POINTERS

Array indexing involves

🢝Multiplying index by element size
🢝Adding to array base address

Pointers correspond directly to memory

addresses
🢝Can avoid indexing complexity
 EXAMPLE: CLEARING AN
ARRAY
clear1(int array[], int size) { clear2(int *array, int size) {
int i; int *p;
for (i = 0; i < size; i += 1) for (p = &array[0]; p < &array[size];
array[i] = 0; p = p + 1)
} *p = 0;
}

move $t0,$zero # i = 0 move $t0,$a0 # p = & array[0]

loop1: sll $t1,$t0,2 # $t1 = i * 4 sll $t1,$a1,2 # $t1 = size * 4
add $t2,$a0,$t1 # $t2 = add $t2,$a0,$t1 # $t2 =
# &array[i] # &array[size]
sw $zero, 0($t2) # array[i] = 0 loop2: sw $zero,0($t0) # Memory[p] = 0
addi $t0,$t0,1 # i = i + 1 addi $t0,$t0,4 # p = p + 4
slt $t3,$t0,$a1 # $t3 = slt $t3,$t0,$t2 # $t3 =
# (i < size) #(p<&array[size])
bne $t3,$zero,loop1 # if (…) bne $t3,$zero,loop2 # if (…)
# goto loop1 # goto loop2
COMPARISON OF ARRAY
VS. PTR
Multiply “strength reduced” to shift
Array version requires shift to be inside
loop
🢝Part of index calculation for incremented i
🢝c.f. incrementing pointer

Compiler can achieve same effect as

manual use of pointers
🢝Induction variable elimination
🢝Better to make program clearer and safer
PITFALLS

Sequential words are not at sequential

addresses
🢝Increment by 4, not by 1!

Keeping a pointer to an automatic

variable after procedure returns
🢝e.g., passing pointer back via an argument
🢝Pointer becomes invalid when stack popped
 CONCLUDING REMARKS
Measure MIPS instruction executions in benchmark
programs
🢝Consider making the common case fast
🢝Consider compromises
Instruction class MIPS examples SPEC2006 Int SPEC2006 FP
Arithmetic add, sub, addi 16% 48%
Data transfer lw, sw, lb, lbu, lh, lhu, 35% 36%
sb, lui
Logical and, or, nor, andi, ori, 12% 4%
sll, srl
Cond. Branch beq, bne, slt, slti, sltiu 34% 8%
Jump j, jr, jal 2% 0%
75
CONCLUDING REMARKS

Design principles
1. Simplicity favors regularity
2. Smaller is faster
3. Make the common case fast
4. Good design demands good compromises

Layers of software/hardware
🢝Compiler, assembler, hardware

MIPS: typical of RISC ISAs

🢝c.f. x86