UNIT-III

Digital Design with Verilog Hardware description Language

(VHDL)

Digital Design with Verilog HDL: Modules –

instances – Data types – Arrays – System tasks
– directives – Modules and Ports – Gate-Level
Modeling – Dataflow Modeling – Behavioral
Modeling - Design of Multiplexers, counters
and full adders – Introduction - Hierarchical
Modeling concepts – 4-bit ripple carry counter.

1
HDL – Hardware Description Language
 HDL stands for Hardware Description
Language. It is a programming
language that is used to describe,
simulate, and create hardware like digital
circuits (ICS). HDL is mainly used to discover
the faults in the design before implementing
it in the hardware.
 The main advantage of HDLs is that it
provides flexible modeling capabilities and
can express the large complex designs
(>107 gates).
VHDL
 VHDL stands for Very High-Speed Integration Circuit HDL (Hardware
Description Language). It is an IEEE (Institute of Electrical and
Electronics Engineers) standard hardware description language that is
used to describe and simulate the behavior of complex digital circuits.
 The most popular examples of VHDL are Odd Parity Generator, Pulse
Generator, Priority Encoder, Behavioral Model for 16 words, 8bit
RAM, etc.

VHDL supports the following features:

 Design methodologies and their features.

 Sequential and concurrent activities.

 Design exchange

 Standardization

 Documentation

 Readability

 Large-scale design

 A wide range of descriptive capability

VHDL is used for the following purposes:

For Describing hardware

As a modeling language
For a simulation of hardware
For early performance estimation of system
architecture
For the synthesis of hardware
Advantages of VHDL
A list of advantages of VHDL is given below:
It supports various design methodologies like
Top-down approach and Bottom-up approach.
It provides a flexible design language.
It allows better design management.
It allows detailed implementations.
It supports a multi-level abstraction.
It provides tight coupling to lower levels of
design.
It supports all CAD tools.
It strongly supports code reusability and code
sharing.
Disadvantages of VHDL

A list of disadvantages of VHDL is given below:

It requires specific knowledge of the structure
and syntax of the language.
It is more difficult to visualize and troubleshoot
a design.
Some VHDL programs cannot be synthesized.
VHDL is more difficult to learn.
VHDL objects
1. Constants
 Constant is an object which can only hold a single value that
cannot be changed during the whole code.
Example: constant number_of_bytes integer:=8;
2. Variables
 A variable also holds a single value of a given type. The value of
the variable may be changed during the simulation by using
variable assignment operator.
 Variables are used in the processes and subprograms.
 Variables are assigned by the assignment operator ":=".
Example: variable index: integer :=0;
3. Signals
 Signals can be declared in architecture and used anywhere
within the architecture. Signals are assigned by the assignment
operator "<=".
Example: Signal sig1: std_logic; Sig1 <= '1'
Data Types in VHDL
1. Scalar Types
Integer
Integer data types are the set of positive and
negative whole numbers.
Floating point
Floating point data types are the set of positive
and negative numbers that contain a decimal point.
Enumeration
Enumeration data type is used to increase the
readability of the code.
Physical
Physical data type describes objects in terms of
a base unit, multiples of base unit, and a specified
range.
2. Composite Types
Arrays
Arrays are used to hold multiple values
of the same types under a single identifier
Record
Records are used to specify one or more
elements, and each element has a different
name and different type.
VHDL Operators
1. Logical Operators
Logical Operators are used to control the
program flow. When the logical operators
combined with signals or variables, then it is
used to create combinational logic.
VHDL supports the following logical operators:
and
or
nand
nor
xor
xnor
not
2. Relational Operators
In VHDL, relational operators are used to
compare two operands of the same data type,
and the received result is always of the
Boolean type.
VHDL supports the following Relational
Operators:
= Equal to
 /= Not Equal to

 < Less than

 > Greater than

 <= Less than or equal to

 >= Greater than or equal to

3. Arithmetic Operators
Arithmetic Operators are used to perform
arithmetic operations. These operators
are numeric types, such as integer and real.
VHDL uses the following Arithmetic Operators:
 + Addition
 - Subtraction
 * Multiplication

 / Division
 & Concatenation

 mod Modulus

 rem Remainder
 abs Absolute Value

 ** Exponentiation
4. Shift Operators
In VHDL, shift operator is used to perform
the bit manipulation on the data by shifting
and rotating the bits of its first operand right
or left.
VHDL supports the following Miscellaneous
Operators:
 Sll shift logical left
 Srl shift logical right
 Sla shift arithmetic left
 Sra shift arithmetic right
 Rol rotate left
 Ror rotate right
Basic Structure of VHDL
module <module name> <optional list of I/O
parameters>;
<input/output declarations>;
<local variable declarations>;
<program statement>;
<program statement>; // Comments
endmodule
Module bg-circuit(a,b,c,d,e)
Input a,b,c;
Output d,e;
Wire w;
And G1(w,a,b);
Not G3(e,c);
Or G2(d,w,e);
End module;
Array
In VHDL (VHSIC Hardware Description
Language), arrays are used to define
collections of elements of the same type, such
as a group of signals or a memory block.
Arrays can be one-dimensional or multi-
dimensional. Below is a basic explanation of
how to define and use arrays in VHDL.
 Defining an Array Type
type int_array is array (0 to 7) of integer;
Declaring an Array Signal or Variable
signal my_array : int_array;
signal my_array : int_array := (0, 1, 2, 3, 4, 5, 6, 7);
Accessing Array Elements
my_array(0) <= 10; -- Set the first element to 10
variable temp : integer;
temp := my_array(3); -- Read the fourth element into a variable
Multi-Dimensional Arrays
type matrix is array (0 to 3, 0 to 3) of integer;
signal my_matrix : matrix := ((1, 2, 3, 4),
(5, 6, 7, 8),
(9, 10, 11, 12),
(13, 14, 15, 16));

my_matrix(0, 0) <= 99;

Array Aggregates
my_array <= (others => 0); -- Set all elements to 0
Examples in a VHDL Architecture
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity array_example is
end array_example;

architecture Behavioral of array_example is

type int_array is array (0 to 7) of integer;
signal my_array : int_array := (0, 1, 2, 3, 4, 5, 6, 7);
begin
process
begin
my_array(3) <= my_array(0) + my_array(1); -- Example operation on the array
wait;
end process;
end Behavioral;
System Task
In VHDL, the term "system task" isn't
commonly used as it is in languages like
Verilog. However, VHDL has similar concepts,
such as procedures, functions, and
processes, which can be used to encapsulate
reusable code, perform tasks, and operate on
data within a design.
Key Concepts Similar to "System Tasks"
in VHDL
Procedures:
Procedures in VHDL are similar to tasks in
Verilog. They are used to group together a
sequence of statements that can be invoked
from various places in your VHDL code.
Procedures can take input, output, and inout
parameters, and they do not return a value.
procedure my_procedure(signal a, b : in integer; signal result : out
integer) is
begin
result <= a + b;
end procedure;

process
variable sum : integer;
begin
my_procedure(5, 10, sum);
wait;
end process;
Functions:

Functions are similar to procedures but they

return a value and only take input
parameters.Functions are used when you
need to perform a calculation or an operation
that returns a single result.
function add_values(a, b : integer) return integer is
begin
return a + b;
end function;

signal result : integer;

result <= add_values(5, 10);
Processes:
A process in VHDL is a concurrent statement
used to model sequential logic. Inside a
process, you can write code that looks like
sequential code, but the process as a whole
executes concurrently with other processes in
the design.
Processes are often used for clocked logic
(like flip-flops and state machines) and for
describing complex combinational logic.
process(clk)
begin
if rising_edge(clk) then
-- Sequential logic here
end if;
end process;
Procedural Blocks (Simulation Tasks):
While VHDL does not have built-in system
tasks like $display in Verilog, it does provide
standard packages such as textio for file I/O
and printing during simulation.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
use STD.TEXTIO.ALL;

process
variable L: line;
begin
write(L, string'("Hello, VHDL!"));
writeline(output, L); -- Output to
console
wait;
end process;
Modules and Ports
In VHDL, the concept of "modules" and
"ports" aligns closely with entities and
architectures. Entities define the interface
(similar to a module in Verilog or a function in
programming languages), and ports within
entities define the inputs and outputs.
1. Entity (Module)
The entity in VHDL is equivalent to a module
in Verilog. It defines the interface of the
hardware block, specifying the input and
output ports.
Example:

entity my_module is
port (
clk : in std_logic; -- Input clock signal
reset : in std_logic; -- Input reset signal
data_in : in std_logic_vector(7 downto 0); -- 8-bit input
data
data_out : out std_logic_vector(7 downto 0) -- 8-bit
output data
);
end my_module;
Ports
Ports are the input and output signals that allow the
entity to communicate with other entities or with
external signals in the design.
in: Input port, receives data from the external
environment.
out: Output port, sends data to the external
environment.
inout: Bidirectional port, can act as both input and
output.
buffer: Similar to out but can also read back the
current value within the architecture.
Port Types:
std_logic: Represents a single-bit signal that can
have multiple values (0, 1, Z, X, etc.).
std_logic_vector: Represents a bus or a group of
std_logic signals.
Architecture
The architecture in VHDL describes the
internal implementation of the entity. It
defines how the inputs are processed to
generate the outputs.
architecture Behavioral of my_module is
begin
process(clk, reset)
begin
if reset = '1' then
data_out <= (others => '0'); -- Reset output
to 0
elsif rising_edge(clk) then
data_out <= data_in; -- Pass input data to
output on clock edge
end if;
end process;
end Behavioral;
Hierarchical Design
Types of Modeling styles in VHDL
1. Data flow modeling (Design Equations)
 Data flow modeling can be described based on the Boolean expression.
It shows how the data flows from input to output. It works on
Concurrent execution.
2. Behavioral modeling (Explains Behaviour)
 Behavioral modeling is used to execute statements sequentially. It
shows that how the system performs according to the current statement.
 Behavioral modeling may contain Process statements, Sequential
statements, Signal assignment statements, and wait statements.
3. Structural modeling (Connection of sub modules)
 Structural modeling is used to specify the functionality and structure of
the circuit.
 Structural modeling contain signal declarations, component instances,
and port maps in component instance.
1. Data flow modeling (Design Equations)
Data flow modeling can be described based on the Boolean
expression. It shows how the data flows from input to
output. It works on Concurrent execution.
2. Behavioral modeling (Explains Behaviour)
 Behavioral modeling is used to execute statements sequentially. It shows that
how the system performs according to the current statement.
 Behavioral modeling may contain Process statements, Sequential statements,
Signal assignment statements, and wait statements.

module mux4x1_bh
(i0,i1,i2,i3,select,y);
input i0,i1,i2,i3;
input [1:0] select;
output y;
reg y;
always @(i0 or i1 or i2 or i3 or
select)
case (select)
2'b00: y = i0;
2'b01: y = i1;
2'b10: y = i2;
2'b11: y = i3;
endcase
endmodule
3. Structural modeling or gate level modeling
(Connection of sub modules)
 Structural modeling is used to specify the functionality and structure of the
circuit.
 Structural modeling contain signal declarations, component instances, and port
maps in component instance.

module decoder_gl (A,B,E,D);

input A,B,E;
output[0:3]D;
wire Anot,Bnot,Enot;
not
n1 (Anot,A),
n2 (Bnot,B),
n3 (Enot,E);
nand
n4 (D[0],Anot,Bnot,Enot),
n5 (D[1],Anot,B,Enot),
n6 (D[2],A,Bnot,Enot),
n7 (D[3],A,B,Enot);
endmodule
4-Bit Ripple Counter

A ripple counter is an asynchronous counter

in which the preceding flop's output clocks all
the flops except the first.
Asynchronous means all the elements of the
circuits do not have a common clock.
For example, a 4 bit counter will count from
0000 to 1111.
module dff (input d, dff dff0 ( .d (qn0),
input clk, .clk (clk),
input rstn, .rstn (rstn),
output reg q,
output qn);
.q (q0),
always @ (posedge clk o .qn (qn0));
r negedge rstn)
if (!rstn) dff dff1 ( .d (qn1),
q <= 0; .clk (q0),
else .rstn (rstn),
q <= d; .q (q1),
.qn (qn1));
assign qn = ~q;
endmodule
dff dff2 ( .d (qn2),
.clk (q1),
module ripple ( input clk, .rstn (rstn),
input rstn, .q (q2),
output [3:0] out) .qn (qn2));
; dff dff3 ( .d (qn3),
wire q0; .clk (q2),
wire qn0;
.rstn (rstn),
wire q1;
wire qn1;
.q (q3),
wire q2; .qn (qn3));
wire qn2; assign out = {qn3, qn2, qn1, qn0};
wire q3;