CMOS VLSI Design

Lecture 6:
DC & Transient Response
Learning Objectives
At the end of this lecture, you should be able to:
• Explain threshold drop in pass transistor circuits.
• Graphically derive the DC response of a CMOS logic gate.
• Estimate the delay of logic gates using RC delay models.

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Outline
• Pass Transistors
• DC Response
• Logic Levels and Noise Margins
• Transient Response
• RC Delay Models
• Delay Estimation

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Pass Transistors
• We have assumed source is grounded
• What if source is >0?
• e.g., pass transistor passing VDD
• Vg = VDD VDD
• If Vs > VDD-Vt, then Vgs < Vt VDD
• Hence, transistor would turn itself off
• nMOS pass transistors pull no higher than VDD-Vtn
• Called a degraded “1”
• Approach degraded value slowly (low Ids)
• pMOS pass transistors pull no lower than Vtp
• Transmission gates are needed to pass both 0 and 1

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Pass Transistor Ckts

VDD VDD VDD

VDD VDD
VDD
Vs = VDD-Vtn VDD-Vtn
VDD-Vtn VDD-Vtn

VDD
VDD-Vtn
Vs = |Vtp|
VDD VDD-2Vtn
VSS

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DC Response
• DC Response: Vout vs. Vin for a gate
• E.g., Inverter
• When Vin = 0 -> Vout = VDD
• When Vin = VDD -> Vout = 0
• In between, Vout depends on
transistor size and current
VDD
• By KCL, must settle such that
Idsn = |Idsp| Idsp
• We could solve equations Vin Vout
• But graphical solution gives more insight Idsn

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Transistor Operation
• Current depends on region of transistor behavior
• For what Vin and Vout are nMOS and pMOS in
• Cutoff?
• Linear?
• Saturation?

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nMOS Operation

Cutoff Linear Saturated

Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn
Vin < Vtn Vin > Vtn Vin > Vtn
Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn
Vout < Vin - Vtn Vout > Vin - Vtn

VDD
Vgsn = Vin Idsp
Vin Vout
Vdsn = Vout Idsn

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pMOS Operation

Cutoff Linear Saturated

Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp
Vin > VDD + Vtp Vin < VDD + Vtp Vin < VDD + Vtp
Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp
Vout > Vin - Vtp Vout < Vin - Vtp

VDD
Vgsp = Vin - VDD Vtp < 0 Idsp
Vin Vout
Vdsp = Vout - VDD Idsn

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I-V Characteristics
• Make pMOS wider than nMOS such that bn = bp

Vgsn5

Idsn Vgsn4

-Vdsp Vgsn3
-VDD Vgsn2
Vgsp1 Vgsn1
Vgsp2 0 VDD
Vgsp3 Vdsn

Vgsp4 -Idsp

Vgsp5

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Current vs. Vout, Vin

Vin0 Vin5

Vin1 Vin4
Idsn, |Idsp|

Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
VDD
Vout

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Load Line Analysis
• For a given Vin:
• Plot Idsn, Idsp vs. Vout
• Vout must be where |currents| are equal in

Vin0 Vin5

Vin1 Vin4
Idsn, |Idsp|
VDD
Vin2 Vin3
Idsp
Vin3 Vin2 Vin Vout
Vin4 Vin1 Idsn

VDD
Vout

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 Load Line Analysis
• Vin = 0  Vin = 00.2V
V
0.4V
0.6V
0.8V
DD DD
DD

Vin0 Vin5
in5

Vin1 Vin4
dsn, |Idsp
Idsn dsp
|

Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
in0
VDD
DD
Vout
out

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DC Transfer Curve
• Transcribe points onto Vin vs. Vout plot

Vin0 Vin1
VDD Vin2
Vin0 Vin5
A B

Vout
Vin1 Vin4
C

Vin2 Vin3
Vin3
Vin3 Vin2 D Vin4 Vin5
Vin4 Vin1 E
0 Vtn VDD/2 VDD+Vtp
VDD VDD
Vout Vin

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 Operating Regions
• Revisit transistor operating regions
VDD

Vin Vout

Region nMOS pMOS

A Cutoff Linear
VDD
B Saturation Linear A B

C Saturation Saturation Vout

C
D Linear Saturation
E Linear Cutoff
D
E
0 Vtn VDD/2 VDD+Vtp
VDD
Vin

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Beta Ratio
• If βp / βn ≈ 1, switching point will move from VDD/2
• Called skewed gate
• Other gates: collapse into equivalent inverter

VDD
p
10
n
Vout 2
1
0.5
p
0.1
n

0
VDD
Vin

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Noise Margins
• How much noise can a gate input see before it does not recognize the input?

Output Characteristics Input Characteristics

VDD
Logical High
Output Range VOH Logical High
Input Range
NMH
VIH
Indeterminate
VIL Region
NML
Logical Low
Logical Low VOL Input Range
Output Range
GND

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 Logic Levels
• To maximize noise margins, select logic levels at
• unity gain point of DC transfer characteristic

Vout

Unity Gain Points

VDD
Slope = -1
VOH

 p/ n > 1

Vin Vout

VOL
Vin
0
Vtn VIL VIH VDD- VDD
|Vtp|

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Transient Response
• DC analysis tells us Vout if Vin is constant
• Transient analysis tells us Vout(t) if Vin(t) changes
• Requires solving differential equations
• Input is usually considered to be a step or ramp
• From 0 to VDD or vice versa

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Inverter Step Response
• E.g., find step response of inverter driving load cap

Vin (t ) u(t  t0 )VDD

Vin(t)
Vout (t  t0 ) VDD Vout(t)
Cload
dVout (t ) I dsn (t )
 Idsn(t)
dt Cload
Vin(t)

 0 t t0

 
 2
I dsn (t )  2 VDD  V Vout  VDD  Vt Vout(t)
 V (t ) t
   VDD  Vt  out  V (t ) V  V  V
 out t0
  2 
out DD t

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Delay Definitions
• tpdr: rising propagation delay
• From input to rising output
crossing VDD/2
• tpdf: falling propagation delay
• From input to falling output
crossing VDD/2
• tpd: average propagation delay
• t = (t + t )/2
pd pdr pdf

• tr: rise time

• From output crossing 0.2 V to
DD
0.8 VDD
• tf: fall time
• From output crossing 0.8 V to
DD
0.2 VDD
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Delay Definitions
• tcdr: rising contamination delay
• From input to rising output crossing VDD/2
• tcdf: falling contamination delay
• From input to falling output crossing VDD/2
• tcd: average contamination delay
• tpd = (tcdr + tcdf)/2

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Simulated Inverter Delay
• Solving differential equations by hand is too hard
• SPICE simulator solves the equations numerically
• Uses more accurate I-V models too!
• But simulations take time to write, may hide insight

2.0

1.5

1.0
(V)
tpdf = 66ps tpdr = 83ps
Vin
Vout
0.5

0.0

0.0 200p 400p 600p 800p 1n

t(s)

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Delay Estimation
• We would like to be able to easily estimate delay
• Not as accurate as simulation
• But easier to ask “What if?”
• The step response usually looks like a 1st order RC response with a decaying
exponential.
• Use RC delay models to estimate delay
• C = total capacitance on output node
• Use effective resistance R
• So that tpd = RC
• Characterize transistors by finding their effective R
• Depends on average current as gate switches

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Effective Resistance
• Shockley models have limited value
• Not accurate enough for modern transistors
• Too complicated for much hand analysis
• Simplification: treat transistor as resistor
• Replace Ids(Vds, Vgs) with effective resistance R
– Ids = Vds/R
• R averaged across switching of digital gate
• Too inaccurate to predict current at any given time
• But good enough to predict RC delay

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RC Delay Model
• Use equivalent circuits for MOS transistors
• Ideal switch + capacitance and ON resistance
• Unit nMOS has resistance R, capacitance C
• Unit pMOS has resistance 2R, capacitance C
• Capacitance proportional to width
• Resistance inversely proportional to width

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RC Values
• Capacitance
• C = Cg = Cs = Cd = 2 fF/mm of gate width in 0.6 mm
• Gradually decline to 1 fF/mm in nanometer techs.
• Resistance
• R ≈ 6 kΩ*mm in 0.6 mm process
• Reduces with shorter channel lengths
• Unit transistors
• May refer to minimum contacted device (4/2 l)
• Or maybe 1 mm wide device
• Doesn’t matter as long as you are consistent

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Inverter Delay Estimate
• Estimate the delay of a fanout-of-1 inverter

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Delay Model Comparison

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 Example: 3-input NAND
• Sketch a 3-input NAND with transistor widths chosen to achieve
effective rise and fall resistances equal to a unit inverter (R).

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 3-input NAND Caps
• Annotate the 3-input NAND gate with gate and diffusion capacitance.

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Elmore Delay
• ON transistors look like resistors
• Pullup or pulldown network modeled as RC ladder
• Elmore delay of RC ladder

t pd  
nodes i
Ri  to  sourceCi

 R1C1  R1  R2 C2  ...  R1  R2  ...  RN C N

R1 R2 R3 RN

C1 C2 C3 CN

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 Example: 3-input NAND
• Estimate worst-case rising and falling delay of 3-input NAND driving h
identical gates.

t pdf 3C  R3   3C  R3  R3    9  5h C   R3  R3  R3 

t pdr 9  5h  RC
11  5h  RC

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Delay Components
• Delay has two parts
• Parasitic delay
– 9 or 11 RC
– Independent of load
• Effort delay
– 5h RC
– Proportional to load capacitance

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 Contamination Delay
• Best-case (contamination) delay can be substantially less
than propagation delay.
• E.g., if all three inputs fall simultaneously

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Diffusion Capacitance
• We assumed contacted diffusion on every s/d.
• Good layout minimizes diffusion area
• E.g., NAND3 layout shares one diffusion contact
• Reduces output capacitance by 2C
• Merged uncontacted diffusion might help too

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Layout Comparison
• Which layout is better?
• Left has less diffusion capacitance on Y

VDD VDD
A B A B

Y Y

GND GND

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