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12 views

Module_4_transistors

Uploaded by

rajashekar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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CMOS VLSI Design

Lecture 4:
CMOS Transistor Theory
Learning Objectives
At the end of this lecture, you should be able to:
• Use cross section diagrams to describe the characteristics of MOS transistors when
operating in cut off, linear and saturation regions.
• Derive the relationship between current and voltage (I-V) of the MOS device at cut off,
linear and saturation modes.
• Mathematically estimate the MOS gate capacitance.
• Describe the effect of diffusion capacitance on the terminals

2 © 2020 Arm Limited


Introduction
• So far, we have treated transistors as ideal switches
• An ON transistor passes a finite amount of current
• Depends on terminal voltages
• Derive current-voltage (I-V) relationships
• Transistor gate, source, drain all have capacitance
• I = C (DV/Dt) -> Dt = (C/I) DV
• Capacitance and current determine speed

3 © 2020 Arm Limited


MOS Capacitor
• Gate and body form MOS capacitor
• Operating modes
• Accumulation
• Depletion
• Inversion
• Threshold voltage
is when inversion
begins

4 © 2020 Arm Limited


Terminal Voltages
• Mode of operation depends on Vg, Vd, Vs
• Vgs = Vg – Vs Vg
• Vgd = Vg – Vd + +
Vgs Vgd
• Vds = Vd – Vs = Vgs - Vgd
- -
• Source and drain are symmetric diffusion terminals Vs
- +
Vd
• By convention, source is terminal at lower voltage Vds

• Hence, Vds ≥ 0

• nMOS body is grounded. First, assume source is 0 too.


• Three regions of operation
• Cutoff
• Linear
• Saturation

5 © 2020 Arm Limited


nMOS Cutoff
• Vgs < Vt
• No inversion, no channel
• Ids ≈ 0

6 © 2020 Arm Limited


nMOS Linear
• Vgs > Vt
• But Vds small
• Channel forms
• Current flows from d to s
• e- from s to d
• Ids increases with Vds
• Similar to linear resistor

7 © 2020 Arm Limited


nMOS Saturation
• Vgs > Vt
• Vds > Vgs - Vt
• Channel pinches off
• Ids independent of Vds
• We say current saturates
• Similar to current source

8 © 2020 Arm Limited


I-V Characteristics
• In Linear region, Ids depends on
• How much charge is in the channel?
• How fast is the charge moving?

9 © 2020 Arm Limited


Channel Charge
• MOS structure looks like a parallel plate capacitor while operating in inversions
• Gate – oxide – channel
• Qchannel = CV
• C = Cg = eoxWL/tox = CoxWL Cox = eox / tox
• V = Vgc – Vt = (Vgs – Vds/2) – Vt
Cox = εox / tox

10 © 2020 Arm Limited


Carrier velocity
• Charge is carried by e-
• Electrons are propelled by the lateral electric field between source and drain
• E = Vds/L
• Carrier velocity v proportional to lateral E-field
• v=µE µ called mobility
• Time for carrier to cross channel:
• t=L/v

11 © 2020 Arm Limited


nMOS Linear I-V
• Now we know
• How much charge Qchannel is in the channel
• How much time (t) each carrier takes to cross

Qchannel
I ds 
t
W  V  V  Vds V
Cox  gs  ds
L
t 2 
V W
  Vgs  Vt  ds  Vds  = Cox
 2 L

12 © 2020 Arm Limited


nMOS Saturation I-V
• If Vgd < Vt, channel pinches off near drain
• When Vds > Vdsat = Vgs – Vt
• Now drain voltage no longer increases current

V
I ds   Vgs  Vt  dsat V
 dsat
 2 

  Vt 
2
 Vgs
2

13 © 2020 Arm Limited


nMOS I-V Summary
• Shockley 1st order transistor models


 0 Vgs  Vt cutoff

  Vds V V  V
I ds    Vgs  Vt   ds linear
 2 
ds dsat

 
Vgs  Vt 
2
 Vds  Vdsat saturation
2

14 © 2020 Arm Limited


Example
• We will be using a 0.6 mm process for your project
• From AMI Semiconductor
• tox = 100 Å 2.5
Vgs = 5
• µ = 350 cm2/V*s
2
• Vt = 0.7 V
1.5
• Plot Ids vs. Vds Vgs = 4

Ids (mA)
• Vgs = 0, 1, 2, 3, 4, 5 1
• Use W/L = 4/2 l Vgs = 3
0.5
Vgs = 2
Vgs = 1
0
0 1 2 3 4 5
W  3.9 8.85 10 14   W W Vds

  Cox 350  8   120 μA/V 2
L  100 10  L  L

15 © 2020 Arm Limited


pMOS I-V
• All dopings and voltages are inverted for pMOS
• Source is the more positive terminal
• Mobility µp is determined by holes 0
Vgs = -1
• Typically 2-3x lower than that of electrons µn Vgs = -2
• 120 cm2/V•s in AMI 0.6 µm process -0.2
• In advanced nodes, µp ≈ µn Vgs = -3

• Thus, pMOS must be wider to

Ids (mA)
-0.4
provide same current Vgs = -4
•In this class, assume
-0.6
µn / µ p = 2

Vgs = -5
-0.8
-5 -4 -3 -2 -1 0
Vds

16 © 2020 Arm Limited


Capacitance
• Any two conductors separated by an insulator have capacitance
• Gate to channel capacitor is very important
• Creates channel charge necessary for operation
• Source and drain have capacitance to body
• Across reverse-biased diodes
• Called diffusion capacitance because it is associated with source/drain diffusion

17 © 2020 Arm Limited


Gate Capacitance
• Approximate channel as connected to source
• Cgs = eoxWL/tox = CoxWL = CpermicronW
• Cpermicron is typically about 2 fF/mm

polysilicon
gate
W
tox
L SiO2 gate oxide
n+ n+ (good insulator, ox = 3.90)
p-type body

18 © 2020 Arm Limited


Diffusion Capacitance
• Source/drain diffusion to body Csb, Cdb
• Undesirable, called parasitic capacitance
• Capacitance depends on area and perimeter
• Use small diffusion nodes
• Comparable to Cg
for contacted diff
• ½ Cg for uncontacted
• Varies with process

19 © 2020 Arm Limited

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