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Computer Organization
& Assembly Language
Week_9 Memory-2 Dr. Abdul Hameed Pitafi Cache Mapping • CPU always generates the address of main memory. Cache Memory • The cache contains a copy of portions of main memory. When the processor attempts to read a word of memory, a check is made to determine if the word is in the cache. If so, the word is delivered to the processor. If not, a block of main memory, consisting of some fixed number of words, is read into the cache and then the word is delivered to the processor. • Because of the phenomenon of locality of reference, when a block of data is fetched into the cache to satisfy a single memory reference, it is likely that there will be future references to that same memory location or to other words in the block. Mapping Function • Because there are fewer cache lines than main memory blocks, an algorithm is needed for mapping main memory blocks into cache lines • Three techniques can be used:
Direct Associative Set Associative
• The simplest technique • Permits each main memory block • A compromise that • Maps each block of main to be loaded into any line of the exhibits the strengths of cache both the direct and memory into only one possible cache line • The cache control logic interprets associative approaches a memory address simply as a Tag while reducing their and a Word field disadvantages • To determine whether a block is in the cache, the cache control logic must simultaneously examine every line’s Tag for a match
Direct Mapping: Pros and Cons • The direct mapping technique is simple and inexpensive to implement. Its main disadvantage is that there is a fixed cache location for any given block. Thus, if a program happens to reference words repeatedly from two different blocks that map into the same line, then the blocks will be continually swapped in the cache, and the hit ratio will be low (a phenomenon known as thrashing). Direct Mapping • The mapping is expressed as • i = j modulo m where • i = cache line number • j = main memory block number • m = number of lines in the cache Q:1 Solution