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Digital Electronics II Lecture 7-1

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17 views16 pages

Digital Electronics II Lecture 7-1

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varc1510hr
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DIGITAL ELECTRONICS II

COURSE
LECTURE 7
SIMPLE PROGRAMMABLE LOGIC
DEVICES (SPLDS)

Hanan Busedra
 Two major types of simple
programmable logic devices (SPLDs) are
the PAL and the GAL. PAL stands for
programmable array logic, and GAL
stands for generic array logic. Generally,
a PAL is one-time programmable (OTP),
and a GAL is a type of PAL that is
reprogrammable.
 SPLD: The PAL
A PAL (programmable array logic) consists
of a programmable array of AND gates that
connects to a fixed array of OR gates.
Generally, PALs are implemented with fuse
process technology and are, therefore,
one-time programmable (OTP).
The PAL structure allows any sum-of-
products (SOP) logic expression with a
defined number of variables to be
implemented.
 any combinational logic function can be expressed in
SOP form. A simple PAL structure is shown in next
figure for two input variables and one output; most
PALs have many inputs and many outputs.
 a programmable array is essentially a grid or matrix
of conductors that form rows and columns with a
programmable link at each cross point. Each program
mable link, which is a fuse in the case of a PAL, is
called a cell. Each row is connected to the input of an
AND gate, and each column is connected to an input
variable or its comple ment. By programming the
presence or absence of a fuse connection, any
combination of input variables or complements can
be applied to an AND gate to form any desired
product term. The AND gates are connected to an OR
gate, creating a sum-of-products (SOP) output.
Implementing a Sum-of-Products
Expression
 An example of a simple PAL is programmed as
shown in next Figure . so that the product term
AB is produced by the top AND gate, AB is
produced by the middle AND gate, and A B is
produced by the bottom AND gate. As you can
see, the fuses are left intact to connect the
desired variables or their complements to the
appropriate AND gate inputs. The fuses are
opened where a variable or its complement is
not used in a given product term. The final
output from the OR gate is the SOP expression.
SPLD: The GAL
 The GAL is essentially a PAL that can be
reprogrammed. It has the same type of
AND/ OR organization that the PAL does.
The basic difference is that a GAL uses a
repro grammable process technology,
such as EEPROM (E2CMOS),instead of
fuses, as shown in next Figure
Simplified Notation for PAL/GAL
Diagrams

 Actual PAL and GAL devices have many


AND and OR gates in addition to other
elements and are capable of handling
many variables and their complements.
Most PAL and GAL diagrams that you
may see on a data sheet use simplified
notation, as illustrated in next Figure
 The input variables to a PAL or GAL are usually buffered
to prevent loading by a large number of AND gate
inputs to which they are connected. On the diagram,
the triangle symbol represents a buffer that produces
both the variable and its complement. The fixed
connections of the input variables and buffers are
shown using standard dot notation. PALs and GALs have
a large number of programmable interconnection lines,
and each AND gate has multiple inputs. Typical PAL and
GAL logic diagrams represent a multiple input AND gate
with an AND gate symbol having a single input line with
a slash and a digit representing the actual number of
inputs. Last Figure illustrates this for the case of 2-input
AND gates.
 Question
Show how a PAL is programmed for the
following 3-variable logic function:
PAL/GAL General Block
Diagram
 A block diagram of a PAL or GAL is
shown in the next Figure. Remember, the
basic difference is that a GAL has a
reprogrammable array and the PAL is
one-time programmable.
 The programmable AND array outputs go to
fixed OR gates that are connected to additional
output logic. An OR gate combined with its
associated output logic is typically called a
macrocell. The complexity of the macrocell
depends on the particular device, and in GALs it
is often reprogrammable. Generally, SPLD
package configurations range from 20 pins to
28 pins. Two factors that you can use to help
determine whether a certain PAL or GAL is
adequate for a given logic design are the
number of inputs and outputs and the number
of equivalent gates or density.
PLA (Programmable Logic Array)

 The architecture of some PLDs is based


on a PLA (programmable logic array)
structure rather than on a PAL
(programmable array logic)
 The PAL has a programmable AND array followed
by a fixed OR array and produces an SOP
expression, as shown by the example in next
Figure (a). The PLA has a programmable AND
array followed by a programmable OR array, as
shown by the example in next Figure (b).

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