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Chap 5

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8 views26 pages

Chap 5

Uploaded by

Bahubali C
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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Central Processing Unit

General Register Organization


R1 <- R2 + R3
Register Stack Organization
PUSH:

POP:
Memory Stack Organization:
PUSH:

POP:
Instruction Formats:

1. Three address instructions.


2. Two address instructions.
3. One address instructions.
4. Zero address instructions.
Three-address Instructions:
Examples:
ADD R1, R2, R3 R1 <- R2 + R3
SUB A, B, C M[A] <- m[B] – m[C]
MUL D, R1, R2 M[D] <- R1 * R2
Two-address Instructions:
Examples:
ADD R1, R2 R1 <- R1 + R2
ADD R6, B R6 <- R6 + M[B]
MUL R1, R2 R1 <- R1 * R2
MOV D, R1 M[D] <- R1
One-address Instructions:
Examples:
ADD R1 AC <- AC + R1
MUL R6 AC <- AC * R6
ADD D AC <- AC + M[D]
LOAD B AC <- M[B]
Zero-address Instructions:
Examples:
PUSH A TOS <- A
PUSH 2 TOS <- 2
POP D M[D] <- TOS
Addressing Modes:
1. Implied Mode.
2. Immediate Mode.
3. Register Mode.
4. Register-Indirect Mode.
5. Direct Address Mode.
6. Indirect Address Mode.
7. Relative Address Mode.
8. Index Addressing Mode.
9. Base Register Addressing Mode.
Data transfer and Manipulation:

• Computer instructions can be classified into


three categories:
Data transfer instructions:

M –> R
R –> M
R->R, R->M, M->M
R <-> R, R <-> M

Proc.Reg – I/O Terminal

Proc.Reg – Mem. stack


Data Manipulation instructions:
Arithmetic Instructions:
Logical and Bit manipulation Instructions:
Shift Instructions:
Program Control:
• Status Bit Conditions:

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