+

Reduced
Instruction Set
Chapter Computers (RISC)
15
William Stallings, Computer Organization and Architecture, 9th
Introduction
Two trends in CPU architecture:
■CISC: Complex Instruction Set Computing/Computer
such as IBM System/360, PDP-11, Motorola 6809,
68000, Intel 8080, x86,… CPU is set up to execute
many instructions.

■RISC: Reduced Instruction Set Computing/Computer:

Idea: All complex instruction is association of some
basic instructions. So, a smaller set of basic
instructions is needed. Examples: Sun UltraSPARC
microprocessor

■More details:

http://en.wikipedia.org/wiki/Complex_instruction_set_computing

http://en.wikipedia.org/wiki/Reduced_instruction_set_computing
 Comparing several RISC and
Non-RISC Systems

Scalar processor: CPU processes one datum at a time

Vector processor: CPU processes multiple data items at a time
Superscalar processor: Architecture implements a form of parallelism called
instruction-level parallelism within a single processor.
(Wiki)
Objectives
After studying this chapter, you should be
able to:
■Provide an overview research results on instruction
execution characteristics that motivated the
development of the RISC approach.

■Summarize the key characteristics of RISC machines.

■Understand the design and performance implications of

using a large register file. Understand the use of
compiler-based register optimization to improve
performance.

■Discuss the implication of a RISC architecture for

pipeline design and performance.

■List and explain key approaches to pipeline

optimization on a RISC machine.
Contents

■15.1- Instruction Execution Characteristics

■15.2- The Use of a Large Register File
■15.3- Compiler-Based Register
Optimization
■15.4- Reduced Instruction Set Architecture
■15.5- RISC Pipelining
■15.8- RISC Versus CISC Controversy
15.1-
Instruction Requirements

Execution
Characteristic
• High-level languages (HLLs)
s •• Allow the programmer to express algorithms more concisely
Allow the compiler to take care of details that are not important in the programmer’s expression of algorithms
• Often support naturally the use of structured programming and/or object-oriented design
• Semantic gap
• The difference between the operations provided in HLLs and those provided in computer architecture
• Operations performed
• Determine the functions to be performed by the processor and its interaction with memory
• Operands used
• The types of operands and the frequency of their use determine the memory organization for storing them and the
addressing modes for accessing them
• Execution sequencing
• Determines the control and pipeline organization

Responses from architecture

 Operations and Operands are used:
Statistic

Statement
 Procedure Call:
Arguments and Local Scalar Variables

Statistic

Scalar variable: Simple variable storing only one

value
+
Implications
■HLLs can best be supported by optimizing
performance of the most time-consuming
features of typical HLL programs
■Three elements characterize RISC
architectures:
■Use a large number of registers or use a compiler to
optimize register usage

■Careful attention needs to be paid to the design of

instruction pipelines

■Instructions should have predictable costs and be

consistent with a high-performance implementation
 +
15.2- The Use of a Large Register
FileRegisters are accessed faster than cache or memory
🡺 More registers are used

Software Solution Hardware Solution

■Requires compiler to ■More registers

allocate registers
■Thus more variables
■Allocates based on will be in registers
most used variables in
a given time
■Requires sophisticated
(complex) program
analysis
+ Overlapping Register Windows
The use of register
Register windows is a group windows is a technique to
of registers which are used to improve the performance of a
pass arguments between particularly common
procedure calls. operation, the procedure call.
This was one of the main
design features of the
original Berkeley
RISC design, which would
later be commercialized as
the SPARC, AMD Am29000,
and Intel i960 (Wiki).
 Circular
Buffer
Organizatio
n of
Overlapped
Windows
A called B; B called C; C called D
The procedure D is active
Overlapped registers are used between callings.
A curcular chain of register references is created

If the procedure F makes

preparation to call another
procedure, registers of A are
conflicted and an interrupt
must be thrown 🡺 N
windows permits N-1 calls
only
+
Global Variables

■ Variables declared as global in an HLL can be assigned

memory locations by the compiler and all machine
instructions that reference these variables will use memory
reference operands
■ However, for frequently accessed global variables this scheme is
inefficient

■ Alternative is to incorporate a set of global registers in the processor

■ These registers would be fixed in number and available to all procedures
■ A unified numbering scheme can be used to simplify the instruction format

■ There is an increased hardware burden (gánh nặng) to accommodate

(supply) the split in register addressing

■ In addition, the linker (a part of compiler) must decide which global

variables should be assigned to registers
Large-Register-File vs. Cache
+
Referencing
Very fast
a Scalar

slower
 12.5- RISC Pipelining
Instruction pipelining is often used to enhance performance.
Most instructions in RISC are register to register.

Instruction cycle: two stages:

• I: Instruction fetch.
• E: Execute, ALU operation, Input and output are registers.

Load and store operations, three stages:

I: Instruction fetch.
E: Execute. Calculates memory address.
D: (direction) Memory. Register-to-memory or memory-to-
register operation.
 The Effects of Pipelining: An
Example

NOOP: No operation 🡪 Wait

+ Optimization of Pipelining
■Delayed branch
■ Does not take effect until after execution of following
instruction
■ This location immediately following the branch is the delay slot 🡪
Insert the instruction NOOP

■Delayed Load
■ Register to be target is locked by processor
■ Continue execution of instruction stream until register required
■ Idle until load is complete
■ Re-arranging instructions can allow useful work while loading

■Loop Unrolling (mở rộng vòng lặp)

■ Replicate body of loop a number of times
■ Iterate loop fewer times
■ Reduces loop overhead
■ Increases instruction parallelism
Table 15.8: Normal and Delayed
Branch
Target of JUMP is delayed 🡪 ADD is executed
before STORE

After 102 is To regularize the Increased

executed, the pipeline, a performance is
next NOOP is achieved only if
instruction to inserted after the instructions at
be executed this branch 101 and 102 are
is 105 (previous slide) interchanged.
+Use of
the
Delaye
d
Branch

Program in the
table 15.6
Loop Unrolling Twice Example

Compiler technique to
improve instruction
parallelism is loop
unrolling .
Unrolling can improve
the performance by:
Reducing loop overhead,
increasing instruction
parallelism by improving
pipeline performance,
improving register, data
cache, or TLB locality

Number of loops
decreases 2 times
+15.8-RISC versus CISC Controversy
■Quantitative – So sánh định lượng
■ Compare program sizes and execution speeds of programs
on RISC and CISC machines that use comparable
technology

■Qualitative – so sánh chất lượng

■ Examine issues of high level language support and use of
VLSI real estate (very large scale integration chip)

■Problems with comparisons:

■ No pair of RISC and CISC machines that are comparable in
life-cycle cost, level of technology, gate complexity,
sophistication of compiler, operating system support, etc.
■ No definitive set of test programs exists
■ Difficult to separate hardware effects from complier effects
■ Most comparisons done on “toy” rather than commercial
products
■ Most commercial devices advertised as RISC possess a
mixture of RISC and CISC characteristics
Chưa biết mèo nào cắn mèo nào!
Controversy: tranh luận The battle has no end!
+
Exercises
■15.1 What are some typical distinguishing
characteristics of RISC organization?

■15.2 Briefly explain the two basic approaches used to

minimize register-memory operations on RISC
machines.

■15.3 If a circular register buffer is used to handle local

variables for nested procedures, describe two
approaches for handling global variables.

■15.4 What are some typical characteristics of a RISC

instruction set architecture?

■15.5 What is a delayed branch?

+ Summary Reduced
Instruction Set
Computers
(RISC)
Chapter 15
■ Instruction execution ■RISC pipelining
characteristics ■Pipelining with regular
■ Operations
instructions
■ Operands
■Optimization of pipelining
■ Procedure calls
■ Implications ■Compiler-based register
■ The
optimization
use of a large
register file ■RISC versus CISC
■ Register windows
controversy
■ Global variables
■ Large register file versus
cache