Objectives

• Learn the components common to every modern

computer system.
• Be able to explain how each component
contributes to program execution.
• Understand a simple architecture invented to
illuminate these basic concepts, and how it relates
to some real architectures.
• Know how the program assembly process works.

1
 CPU Basics

• The computer’s CPU fetches, decodes, and

executes program instructions.
• The two principal parts of the CPU are the
datapath and the control unit.
– The datapath consists of an arithmetic-logic unit and
storage units (registers) that are interconnected by a data
bus that is also connected to main memory.
– Various CPU components perform sequenced operations
according to signals provided by its control unit.

2
 CPU Basics

• Registers hold data that can be readily accessed by

the CPU.
• They can be implemented using D flip-flops.
– A 32-bit register requires 32 D flip-flops.
• The arithmetic-logic unit (ALU) carries out logical
and arithmetic operations as directed by the control
unit.
• The control unit determines which actions to carry
out according to the values in a program counter
register and a status register.

3
 The Bus

• The CPU shares data with other system components

by way of a data bus.
– A bus is a set of wires that simultaneously convey a single bit
along each line.
• Two types of buses are commonly found in
computer systems: point-to-point, and multipoint
buses.

This is a point-to-point
bus configuration:

4
 The Bus

• Buses consist of data lines, control lines, and

address lines.
• While the data lines convey bits from one device to
another, control lines determine the direction of
data flow, and when each device can access the
bus.
• Address lines determine the location of the source
or destination of the data.
The next slide shows a model bus configuration.

5
The Bus

6
 The Bus

• A multipoint bus is shown below.

• Because a multipoint bus is a shared resource,
access to it is controlled through protocols, which
are built into the hardware.

7
 A Simple Processor

• We can now bring together many of the ideas that

we have discussed to this point using a very simple
model computer.
• Our model computer, the Machine Architecture that
is Really Intuitive and Easy, It, was designed for the
singular purpose of illustrating basic computer
system concepts.
• While this system is too simple to do anything useful
in the real world, a deep understanding of its
functions will enable you to comprehend system
architectures that are much more complex.

8
 A Simple Processor

The architecture has the following characteristics:

• Binary, two's complement data representation.
• Stored program, fixed word length data and
instructions.
• 4K words of word-addressable main memory.
• 16-bit data words.
• 16-bit instructions, 4 for the opcode and 12 for the
address.
• A 16-bit arithmetic logic unit (ALU).
• Seven registers for control and data movement.

9
 Simple Processor

Its seven registers are:

• Accumulator, AC, a 16-bit register that holds a
conditional operator (e.g., "less than") or one operand
of a two-operand instruction.
• Memory address register, MAR, a 12-bit register that
holds the memory address of an instruction or the
operand of an instruction.
• Memory buffer register, MBR, a 16-bit register that
holds the data after its retrieval from, or before its
placement in memory.

10
 A Simple Processor

Its seven registers are:

• Program counter, PC, a 12-bit register that holds the
address of the next program instruction to be executed.
• Instruction register, IR, which holds an instruction
immediately preceding its execution.
• Input register, InREG, an 8-bit register that holds data
read from an input device.
• Output register, OutREG, an 8-bit register, that holds
data that is ready for the output device.

11
 A Simple Processor

This is the MARIE architecture shown graphically.

12
 A Simple Processor

• The registers are interconnected, and connected

with main memory through a common data bus.
• Each device on the bus is identified by a unique
number that is set on the control lines whenever
that device is required to carry out an operation.
• Separate connections are also provided between
the accumulator and the memory buffer register,
and the ALU and the accumulator and memory
buffer register.
• This permits data transfer between these devices
without use of the main data bus.

13
 A Simple Processor

This is the data path

shown graphically.

14
 A Simple Processor

• A computer’s instruction set architecture (ISA)

specifies the format of its instructions and the
primitive operations that the machine can perform.
• The ISA is an interface between a computer’s
hardware and its software.
• Some ISAs include hundreds of different instructions
for processing data and controlling program
execution.
• The MARIE ISA consists of only thirteen instructions.

15
 A Simple Processor

• This is the format

of a MARIE instruction:

• The fundamental MARIE instructions are:

16
 A Simple Processor

• This is a bit pattern for a LOAD instruction as it would

appear in the IR:

• We see that the opcode is 1 and the address from

which to load the data is 3.

17
 A Simple Processor

• This is a bit pattern for a SKIPCOND instruction as it

would appear in the IR:

• We see that the opcode is 8 and bits 11 and 10 are

10, meaning that the next instruction will be skipped
if the value in the AC is greater than zero.

What is the hexadecimal representation of this instruction?

18
 A Simple Processor

• Each of our instructions actually consists of a

sequence of smaller instructions called
microoperations.
• The exact sequence of microoperations that are
carried out by an instruction can be specified using
register transfer language (RTL).
• In the MARIE RTL, we use the notation M[X] to
indicate the actual data value stored in memory
location X, and  to indicate the transfer of bytes to a
register or memory location.

19
 A Simple Processor

• The RTL for the LOAD instruction is:

MAR  X
MBR  M[MAR]
AC  MBR

• Similarly, the RTL for the ADD instruction is:

MAR  X
MBR  M[MAR]
AC  AC + MBR

20
 A Simple Processor

• Recall that SKIPCOND skips the next instruction

according to the value of the AC.
• The RTL for the this instruction is the most complex
in our instruction set:
If IR[11 - 10] = 00 then
If AC < 0 then PC  PC + 1
else If IR[11 - 10] = 01 then
If AC = 0 then PC  PC + 1
else If IR[11 - 10] = 11 then
If AC > 0 then PC  PC + 1

21
 Instruction Processing

• The fetch-decode-execute cycle is the series of

steps that a computer carries out when it runs a
program.
• We first have to fetch an instruction from memory,
and place it into the IR.
• Once in the IR, it is decoded to determine what
needs to be done next.
• If a memory value (operand) is involved in the
operation, it is retrieved and placed into the MBR.
• With everything in place, the instruction is executed.
The next slide shows a flowchart of this process.

22
Instruction Processing

23
 A Simple Program

• Consider the simple program given below. We show

a set of mnemonic instructions stored at addresses
100 - 106 (hex):

24
 A Simple Program

• Let’s look at what happens inside the computer

when our program runs.
• This is the LOAD 104 instruction:

25
 A Simple Program

• Our second instruction is ADD 105:

26
 A Discussion on Assemblers

• Mnemonic instructions, such as LOAD 104, are easy

for humans to write and understand.
• They are impossible for computers to understand.
• Assemblers translate instructions that are
comprehensible to humans into the machine
language that is comprehensible to computers
– We note the distinction between an assembler and a compiler:
In assembly language, there is a one-to-one correspondence
between a mnemonic instruction and its machine code. With
compilers, this is not usually the case.

27
 A Discussion on Assemblers

• Assemblers create an object program file from

mnemonic source code in two passes.
• During the first pass, the assembler assembles as
much of the program is it can, while it builds a
symbol table that contains memory references for
all symbols in the program.
• During the second pass, the instructions are
completed using the values from the symbol table.

28
 A Discussion on Assemblers

• Consider our example

program (top).
– Note that we have included two
directives HEX and DEC that
specify the radix of the
constants.
• During the first pass, we
have a symbol table and the
partial instructions shown at
the bottom.

29
 A Discussion on Assemblers

• After the second pass,

the assembly is complete.

30
 Extending Our Instruction Set

• So far, all of the instructions that we have

discussed use a direct addressing mode.
• This means that the address of the operand is
explicitly stated in the instruction.
• It is often useful to employ a indirect addressing,
where the address of the address of the operand is
given in the instruction.
– If you have ever used pointers in a program, you are
already familiar with indirect addressing.

31
 Extending Our Instruction Set

• To help you see what happens at the machine

level, we have included an indirect addressing
mode instruction to the MARIE instruction set.
• The ADDI instruction specifies the address of the
address of the operand. The following RTL tells us
what is happening at the register level:

MAR  X
MBR  M[MAR]
MAR  MBR
MBR  M[MAR]
AC  AC + MBR
32
 Extending Our Instruction Set

• Another helpful programming tool is the use of

subroutines.
• The jump-and-store instruction, JNS, gives us
limited subroutine functionality. The details of the
JNS instruction are given by the following RTL:
MBR  PC
MAR  X
Does JNS permit
M[MAR]  MBR
recursive calls?
MBR  X
AC  1
AC  AC + MBR
AC  PC
33
 Extending Our Instruction Set

• Our last helpful instruction is the CLEAR instruction.

• All it does is set the contents of the accumulator to
all zeroes.
• This is the RTL for CLEAR:

AC  0
• We put our new instructions to work in the program
on the following slide.

34
Extending Our Instruction Set

100 | LOAD Addr 10E | SKIPCOND

101 | STORE Next 000
102 | LOAD Num
103 | SUBT One
10F | JUMP Loop
104 | STORE Ctr 110 | HALT
105 |Loop LOAD Sum 111 |Addr HEX 118
106 | ADDI Next 112 |Next HEX 0
107 | STORE Sum 113 |Num DEC 5
108 | LOAD Next
109 | ADD One
114 |Sum DEC 0
10A | STORE Next 115 |Ctr HEX 0
10B | LOAD Ctr 116 |One DEC 1
10C | SUBT One 117 | DEC 10
10D | STORE Ctr 118 | DEC 15
119 | DEC 2
11A | DEC 25
11B | DEC 30

35
 A Discussion on Decoding

• A computer’s control unit keeps things synchronized,

making sure that bits flow to the correct components
as the components are needed.
• There are two general ways in which a control unit
can be implemented: hardwired control and
microprogrammed control.
– With microprogrammed control, a small program is placed
into read-only memory in the microcontroller.
– Hardwired controllers implement this program using digital
logic components.

36
 A Discussion on Decoding

• Your text provides a complete list of the register

transfer language for each of MARIE’s instructions.
• The microoperations given by each RTL define the
operation of MARIE’s control unit.
• Each microoperation consists of a distinctive signal
pattern that is interpreted by the control unit and
results in the execution of an instruction.
– Recall, the RTL for the Add instruction is:

MAR  X
MBR  M[MAR]
AC  AC + MBR
37
 A Discussion on Decoding

• Each of registers and

main memory have a
unique address along
the datapath.
• The addresses take the
form of signals issued
by the control unit.

How many signal lines does

MARIE’s control unit need?

38
 Real World Architectures

• The classic Intel architecture, the 8086, was born

in 1979. It is a CISC architecture.
• It was adopted by IBM for its famed PC, which
was released in 1981.
• The 8086 operated on 16-bit data words and
supported 20-bit memory addresses.
• Later, to lower costs, the 8-bit 8088 was
introduced. Like the 8086, it used 20-bit memory
addresses.

What was the largest memory that the 8086 could address?

39
 Real World Architectures

• The 8086 had four 16-bit general-purpose

registers that could be accessed by the half-word.
• It also had a flags register, an instruction register,
and a stack accessed through the values in two
other registers, the base pointer and the stack
pointer.
• The 8086 had no built in floating-point processing.
• In 1980, Intel released the 8087 numeric
coprocessor, but few users elected to install them
because of their cost.

40
 Real World Architectures

• In 1985, Intel introduced the 32-bit 80386.

• It also had no built-in floating-point unit.
• The 80486, introduced in 1989, was an 80386 that
had built-in floating-point processing and cache
memory.
• The 80386 and 80486 offered downward
compatibility with the 8086 and 8088.
• Software written for the smaller word systems was
directed to use the lower 16 bits of the 32-bit
registers.

41
 Real World Architectures

• Currently, Intel’s most advanced 32-bit

microprocessor is the Pentium 4.
• It can run as fast as 3.8 GHz. This clock rate is
nearly 800 times faster than the 4.77 MHz of the
8086.
• Speed enhancing features include multilevel cache
and instruction pipelining.
• Intel, along with many others, is marrying many of
the ideas of RISC architectures with
microprocessors that are largely CISC.

42
 Real World Architectures

• The MIPS family of CPUs has been one of the most

successful in its class.
• In 1986 the first MIPS CPU was announced.
• It had a 32-bit word size and could address 4GB of
memory.
• Over the years, MIPS processors have been used
in general purpose computers as well as in games.
• The MIPS architecture now offers 32- and 64-bit
versions.

43
44
Fetch memory cycle and Control Signals

• MAR  PC PCToBus, MARLd, Read

• IR  M[MAR] MEMToBus , IrLd
• MAR  IR[11.. 0],PC  PC + 1
• PcInc, IRtoBus,
MARLd,Read

• 3 Cycles, Last two steps can be done in one

clock cycle.
45
 LoadX and Signals
• MBR  M[MAR] MbrLd
• AC  MBR MbrToBus,AcLd

• No of Cycles = 3+ 2 = 5
• Assuming Fetch takes 3 clock cycles

46
 Store X
• MBR  AC AcToBus, MbrLd
• M[MAR]  MBR MbrToBus, Write

• No of Cycles = 3 + 2 = 5

47
 Add X
• MBR  M[MAR] MEMtoBus,MbrLd
• AC  AC + MBR AccPlus , AcLd

• 3+2 = 5 Cycles

48
 Subt X
• MBR  M[MAR] MEtoBus, MbrLd
• AC  AC + MBR AccMinus , AcLd

• 3 + 2 Cycles

49
 Jump X
• MBR  M[MAR] MEMtoBus, MbrLd
• PC  MBR MbrToBus , PcLd

• 3 + 2 cycles

50
 Skipcond
• If IR[11 - 10] = 00 then
• If AC < 0 then PC  PC + 1
• else If IR[11 - 10] = 01 then
• If AC = 0 then PC  PC + 1
• else If IR[11 - 10] = 11 then
• If AC > 0 then PC  PC + 1
• 3 Cycles
51
 AddI x
• MBR  M[MAR] MEMtoBus, MBRLd
• MAR  MBR MBRtoBus,
MARLd ,Read
• MBR  M[MAR] MEMtoBus, MBRLd
• AC  AC + MBR Plus, AcLd

• 3+ 4 = 7 cycles
52
• A CPU is just a finite state machine, by
specifying the states and their micro-
operations,

• we specify the steps the CPU must

perform in order to fetch, decode and
execute every instruction in the instruction
set.
53
54
55
56
 States
• Fetch1 = T0
• Fetch2 = T1
• Fecth3 = T2
• Load1 = LoadX ^ T3
• Load2 = LoadX ^ T4
• Store1 = Storex ^ T3
• Store2 = StoreX ^ T4
57
states

58
 Control signals required and
states
• Read = Fetch1 v Fetch3 v AddI2
• PCtoBus = Fetch1
• MARLd = Fetch1 v Fetch3 v AddI2
• MEMtoBus = Fetch2 v Add1 v Store1 v
Jump1 v AddI1 v AddI3
• IRLd = Fetch2
• IRtoBus = Fetch3
59
 Real World Architectures

• MIPS was one of the first RISC microprocessors.

• The original MIPS architecture had only 55 different
instructions, as compared with the 8086 which had
over 100.
• MIPS was designed with performance in mind: It is
a load/store architecture, meaning that only the
load and store instructions can access memory.
• The large number of registers in the MIPS
architecture keeps bus traffic to a minimum.

How does this design affect performance?

60
 Conclusion

• The major components of a computer system

are its control unit, registers, memory, ALU,
and data path.
• A built-in clock keeps everything synchronized.
• Control units can be microprogrammed or
hardwired.
• Hardwired control units give better
performance, while microprogrammed units are
more adaptable to changes.

61
 Conclusion

• Computers run programs through iterative

fetch-decode-execute cycles.
• Computers can run programs that are in
machine language.
• An assembler converts mnemonic code to
machine language.
• The Intel architecture is an example of a CISC
architecture; MIPS is an example of a RISC
architecture.

62
End of Chapter 4

63