Microcontrollers

4th Semester
Interrupt Programming: Basics of Interrupts, 8051 Interrupts,
Programming Timer Interrupts, Programming Serial
Communication Interrupts, Interrupt Priority in 8051(Assembly
Language only) ( Text book 2- 3.6, Text book 1- 11.1,11.2,11.4,
11.5)

Dept of ECE, SJCIT

01/22/2025 1
Microcontrollers. 4th sem
 Module-5 : 8051 Interrupts and Interfacing
Applications

Contents:
• 8051 Interrupts
• 8051 Assembly language interfacing
• 8051 Assembly language programming to generate an external
interrupt using a switch
• 8051 C programming to generate a square waveform on a port pin
using a Timer interrupt
• Interfacing 8051 to ADC-0804
• Interfacing 8051 to DAC
• Interfacing 8051 to LCD
• Interfacing 8051 to Stepper motor
• 8051 Assembly language interfacing programming

01/22/2025 Dept of ECE, SJCIT 2

Microcontrollers. 4th sem
 8051 INTERRUPTS
BASICS OF INTERRUPTS:
• An interrupt is an external or internal event that interrupts the
microcontroller to inform it that a device needs its service
• During program execution if peripheral devices needs service
from microcontroller, device will generate interrupt and gets
the service from microcontroller.
• When peripheral device activate the interrupt signal, the
processor branches to a program called interrupt service
routine.
• After executing the interrupt service routine the processor
returns to the main program

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Microcontrollers. 4th sem
 INTERRUPTS VS. POLLING

• A single microcontroller can serve several devices by two ways, Interrupts and
Polling.
Interrupts:
• Whenever any device needs its service, the device notifies the microcontroller
by sending it an interrupt signal
• Upon receiving an interrupt signal, the microcontroller interrupts whatever it is
doing and serves the device
• The program which is associated with the interrupt is called the interrupt
service routine (ISR) or interrupt handler
• Advantage of interrupt: The advantage of interrupts is that the microcontroller
can serve many devices (not all at the same time)
• Each devices can get the attention of the microcontroller based on the assigned
priority
• For the polling method, it is not possible to assign priority since it checks all
devices in a round-robin fashion
• The microcontroller can also ignore (mask) a device request for service
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Microcontrollers. 4th sem
 Polling
• The microcontroller continuously monitors the status of a given
device.
• When the conditions met, it performs the service.
• After that, it moves on to monitor the next device until
everyone is serviced
• Disadvantage of polling: Polling can monitor the status of
several devices and serve each of them as certain conditions are
met
• The polling method is not efficient, since it wastes much of
the microcontrollers time by polling devices that do not
need service
• The microcontroller cannot ignore (mask) a device request
for service
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Microcontrollers. 4th sem
 INTERRUPT SERVICE ROUTINE (ISR)

• For every interrupt, there must be an interrupt service routine

(ISR), or interrupt handler
• When an interrupt is invoked, the microcontroller runs the
interrupt service routine
• For every interrupt, there is a fixed location in memory that
holds the address of its ISR

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 Steps taken by processor while processing an
interrupt
• It finishes the instruction currently executing and saves the
address of the next instruction (PC) on the stack
• It also saves the current status of all the interrupts internally
• It jumps to a fixed location in memory, called the interrupt
vector table, that holds the address of the ISR
• The microcontroller gets the address of the ISR from the
interrupt vector table and jumps to it
– It starts to execute the interrupt service subroutine until it reaches the last
instruction of the subroutine which is RETI (return from interrupt)
• Upon executing the RETI instruction, the microcontroller returns
to the place where it was interrupted
– First, it gets the program counter (PC) address from the stack by popping
the top two bytes of the stack into the PC
– Then it starts to execute from that address
01/22/2025 Dept of ECE, SJCIT 7
Microcontrollers. 4th sem
 Classification of interrupts.
External and internal interrupts.
• External interrupts are those initiated by peripheral devices through the external pins
of the microcontroller.
• Internal interrupts are those activated by the internal peripherals of the microcontroller
like timers, serial controller etc.
Maskable and non-maskable interrupts.
• The category of interrupts which can be disabled by the processor using program is
called maskable interrupts.
• Non-maskable interrupts are those category by which the programmer cannot disable
it using program.
Vectored and non-vectored interrupt.
• Starting address of the ISR is called interrupt vector. In vectored interrupts the starting
address is predefined. In non-vectored interrputs, the starting address is provided by
the peripheral as follows.
– Microcontroller receives an interrupt request from external device.
– Controller sends an acknowledgement (INTA) after completing the execution of current
instruction.
– The peripheral device sends the interrupt vector to the microcontroller.
Dept of ECE, SJCIT
01/22/2025 8
Microcontrollers. 4th sem
 8051 INTERRUPT STRUCTURE

Six interrupts are allocated as follows :

• Reset – power-up reset
• Two interrupts are set aside for the timers: one for timer 0 and
one for timer 1
• Two interrupts are set aside for hardware external interrupts
P3.2 and P3.3 are for the external hardware interrupts INT0
(or EX1), and INT1 (or EX2)
• Serial communication has a single interrupt that belongs to
both receive and transfer

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 Interrupt vector table

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 ENABLING AND DISABLING AN INTERRUPT

• Upon reset, all interrupts are disabled (masked), meaning that

none will be responded to by the microcontroller if they are
activated
• The interrupts must be enabled by software in order for the
microcontroller to respond to them
• There is a register called IE (interrupt enable) that is responsible for
enabling (unmasking) and disabling (masking) the interrupts

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 IE Register

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 Steps to enable an interrupt
To enable an interrupt, we take the following steps:
• Bit D7 of the IE register (EA) must be set to high to allow the
rest of register to take effect
• The value of EA
• If EA = 1, interrupts are enabled and will be responded to if
their corresponding bits in IE are high
• If EA = 0, no interrupt will be responded to, even if the
associated bit in the IE register is high

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 Example
Example : Show the instructions to
• enable the serial interrupt, timer 0 interrupt, and external hardware interrupt 1 (EX1),and
• disable (mask) the timer 0 interrupt, then
• show how to disable all the interrupts with a single instruction.

• Solution:
• MOV IE,#10010110B ;enable serial, timer 0, EX1
Another way to perform the same manipulation is
• SETB IE.7 ;EA=1, global enable
• SETB IE.4 ;enable serial interrupt
• SETB IE.1 ;enable Timer 0 interrupt
• SETB IE.2 ;enable EX1

• CLR IE.1 ;mask (disable) timer 0,interrupt only

• CLR IE.7 ;disable all interrupts

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 INTERRUPT PRIORITY
• When the 8051 is powered up, the priorities are assigned according to the
following
• In reality, the priority scheme is nothing but an internal polling sequence in
which the 8051 polls the interrupts in the sequence listed and responds
accordingly.

Interrupt source Type Vector address Priority

External interrupt 0 External 0003 Highest
Timer 0 interrupt Internal 000B
External interrupt 1 External 0013
Timer 1 interrupt Internal 001B
Serial interrupt Internal 0023 Lowest

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 Example
Discuss what happens if interrupts INT0, TF0, and INT1 are activated
at the same time. Assume priority levels were set by the power-up
reset and the external hardware interrupts are edge triggered.
Solution:
• If these three interrupts are activated at the same time, they are
latched and kept internally.
• Then the 8051 checks all five interrupts according to the sequence
listed in Table above .
• If any is activated, it services it in sequence. Therefore, when the
above three interrupts are activated, IE0 (external interrupt 0) is
serviced first, then timer 0 (TF0), and finally IE1 (external
interrupt 1).

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Microcontrollers. 4th sem
 INTERRUPT PRIORITY (IP) REGISTER

– We can alter the sequence of interrupt priority by assigning a higher priority

to any one of the interrupts by programming a register called IP
– To give a higher priority to any of the interrupts, we make the corresponding
bit in the IP register high
– When two or more interrupt bits in the IP register are set to high: While the
interrupts have a higher priority than others, they are serviced according to
the sequence of table above.

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Microcontrollers. 4th sem
 Example
Program the IP register to assign the highest priority to INT1(external interrupt 1), then
discuss what happens if INT0, INT1, and TF0 are activated at the same time. Assume
the interrupts are both edge-triggered.
Solution:
• MOV IP,#00000100B ;IP.2=1 assign INT1 higher priority. The instruction SETB
IP.2 also will do the same thing as the above line since IP is bit-addressable.

• The instruction in Step (a) assigned a higher priority to INT1 than the others;
• therefore, when INT0,INT1, and TF0 interrupts are activated at the same time, the
8051 services INT1 first, then it services INT0, then TF0.
• This is due to the fact that INT1 has a higher priority than the other two because of
the instruction in Step (a). The instruction in Step (a) makes both the INT0 and
• TF0 bits in the IP register 0. As a result, the sequence in Table is followed which
gives a higher priority to INT0 over TF0

01/22/2025 Dept of ECE, SJCIT 18

Microcontrollers. 4th sem
 Example

Assume that after reset, the interrupt priority is set the instruction MOV
IP,#00001100B. Discuss the sequence in which the interrupts are
serviced.

Solution:
The instruction “MOV IP #00001100B” (B is for binary) and timer 1
(TF1)to a higher priority level compared with the reset of the interrupts.
However, since they are polled according to Table,
they will have the following priority.
• Highest Priority External Interrupt 1 (INT1)
• Timer Interrupt 1 (TF1)
• External Interrupt 0 (INT0)
• Timer Interrupt 0 (TF0)
• Lowest Priority Serial Communication (RI+TI)
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Microcontrollers. 4th sem
 INTERRUPT INSIDE AN INTERRUPT

• In the 8051 a low-priority interrupt can be interrupted by a

higher-priority interrupt but not by another low priority
interrupt
• Although all the interrupts are latched and kept internally, no
low-priority interrupt can get the immediate attention of the
CPU until the 8051 has finished servicing the high-priority
interrupts

01/22/2025 Dept of ECE, SJCIT 20

Microcontrollers. 4th sem
 TRIGGERING INTERRUPT BY SOFTWARE

• To test an ISR by way of simulation can be done with simple

instructions to set the interrupts high and thereby cause the
8051 to jump to the interrupt vector table

• Example: If the IE bit for timer 1 is set, an instruction such as

SETB TF1 will interrupt the 8051 in whatever it is doing and
will force it to jump to the interrupt vector table.

• We do not need to wait for timer 1 go roll over to have an

interrupt

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Microcontrollers. 4th sem
 Example
Write a program to continuously generate a square wave of 2 kHz frequency on pin
P1.5 using timer 1. Assume the crystal oscillator frequency to be 12 MHz
The period of the square wave is T = 1/(2 kHz) = 500 ms. Each half pulse = 250 ms.
The value n for 250 ms is: 250 ms /1 ms = 250
• 65536 - 250 = FF06H.
• TL = 06H and TH = 0FFH.

MOV TMOD,#10 ;Timer 1, mode 1

AGAIN:MOV TL1,#06H ;TL0 = 06H
MOV TH1,#0FFH ;TH0 = FFH
SETB TR1 ;Start timer 1
BACK:JNB TF1,BACK ;Stay until timer rolls over
CLR TR1 ;Stop timer 1
CPL P1.5 ;Complement P1.5 to get Hi, Lo
CLR TF1 ;Clear timer flag 1
SJMP AGAIN ;Reload timer

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Microcontrollers. 4th sem
 Stepper Motor Interface

• A stepper motor is an electromechanical device it converts

electrical power into mechanical power
• The stepper motor uses the theory of operation for magnets to
make the motor shaft turn a precise distance when a pulse of
electricity is provided.
• https://www.youtube.com/watch?v=eyqwLiowZiU

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 Stepper Motor

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 DIGITAL I/O PORT AND PERIPHERALS

• The 8051 contains four 8-bit parallel ports namely PORT 0, PORT 1,
PORT 2 and PORT 3.
• Ports are used to send or receive data and each bit of port can be
configured as an input or output.
• PORT 0 is also used as low order address and data pins(AD0 – AD7)
• PORT 2 is used as high order address pins(A8-A15)
• PORT 3 is used by timers, serial ports, external interrupts and for
sending control signals(RD,WR).
• Each port is associated with port registers P0 (80 H) ,P1(90 H),P2(0A0
H) and P3(0B0 H)
• These ports supports all the three types of buses namely Address bus
(A0-A15), Data bus(D0-D7) and Control bus(RD,WR,PSEN,ALE,EA).
PERIPHERALS: TIMER 0 and TIMER 1.
• Each timer consists of two 8-bit register
01/22/2025 Dept of ECE, SJCIT 35
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 INTERFACING LCD TO 8051

LCD is finding widespread use replacing LEDs

• The declining prices of LCD
• The ability to display numbers, characters, and graphics
• Incorporation of a refreshing controller into the LCD, thereby
relieving the CPU of the task of refreshing the LCD
• Ease of programming for characters and graphics

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 PIN DESCRIPTION

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 LCD Command codes

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 Sending data and codes to LCD

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 Sending data and codes to LCD contd..

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 Sending data and codes to LCD contd..

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 Sending data and codes to LCD contd..

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 LCD data sheet

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 LCD data sheet contd..

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 Sending Information to LCD Using MOVC Instruction

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 Sending Information to LCD Using MOVC Instruction

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 Example
Write an 8051 C program to send letters ‘M’, ‘D’, and ‘E’to the LCD using the busy flag
method.
Solution: #include <reg51.h>
sfrldata= 0x90; //P1=LCD data pins
sbitrs= P2^0; sbitrw= P2^1;
sbiten = P2^2;
sbitbusy = P1^7;
void main()
{
lcdcmd(0x38);
lcdcmd(0x0E);
lcdcmd(0x01);
lcdcmd(0x06);
lcdcmd(0x86); //line 1, position 6
lcdcmd(‘M’);
lcdcmd(‘D’);
lcdcmd(‘E’);
} .....
01/22/2025 Dept of ECE, SJCIT 47
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 Example contd..
.....
void lcdcmd(unsignedchar value)
{
lcdready(); //check the LCD busy flag
ldata= value; //put the value on the pins
rs= 0;
rw= 0;
en = 1; //strobe the enable pin MSDelay(1);
en = 0;
return;
}

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 Example contd..
void lcddata(unsignedchar value)
{
lcdready(); //check the LCD busy flag
ldata= value; //put the value on the pins
rs= 1;
rw= 0;
en = 1; //strobe the enable pin
MSDelay(1);
en = 0;
return;
}
.....
01/22/2025 Dept of ECE, SJCIT 49
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 Example contd..
.... void lcdready()
{
busy = 1; //make the busy pin at input
rs= 0; rw= 1;
while(busy==1)
{ //wait here for busy flag
en = 0; //strobe the enable pin
MSDelay(1);
en = 1;
}
void lcddata(unsignedint itime)
{
unsigned int i, j;
for(i=0;i<itime;i++)
for(j=0;j<1275;j++);
}
01/22/2025 Dept of ECE, SJCIT 50
Microcontrollers. 4th sem
 INTERFACING TO ADC AND SENSORS

• ADCs (analog-to-digital converters) are among the most widely used

devices for data acquisition
• A physical quantity, like temperature, pressure, humidity, and velocity,
etc., is converted to electrical (voltage, current) signals using a device
called a transducer , or sensor
• We need an analog-to-digital converter to translate the analog signals to
digital numbers, so microcontroller can read them
• ADC804 IC is an analog-to-digital converter
• It works with +5 volts and has a resolution of 8 bits
• Conversion time is another major factor in judging an ADC
• Conversion time is defined as the time it takes the ADC to convert the
analog input to a digital (binary) number
• In ADC804 conversion time varies depending on the clocking signals
applied to CLK R and CLK IN pins, but it cannot be faster than 110 µs
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 ADC804 Chip

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 Internal memory (On-chip Memory)

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Examine the ADC804 connection to the 8051 in Figure 12-7. Write a program to monitor the
INTR pin and bring an analog input into register A. Then call a hex-to ACSII conversion and data
display subroutines. Do this continuously.
;p2.6=WR (start conversion needs to L-to-H pulse)
;p2.7 When low, end-of-conversion)
;p2.5=RD (a H-to-L will read the data from ADC chip)
;p1.0 –P1.7= D0 -D7 of the ADC804
;
MOV P1,#0FFH ;make P1 = input
BACK: CLR P2.6 ;WR = 0
SETB P2.6 ;WR = 1 L-to-H to start conversion
HERE: JB P2.7,HERE ;wait for end of conversion
CLR P2.5 ;conversion finished, enable RD
MOV A,P1 ;read the data
ACALL CONVERSION ;hex-to-ASCII conversion
ACALL DATA_DISPLAY;display the data
SETB p2.5 ;make RD=1 for next round
SJMP BACK
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 DAC

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 Example
Find the maximum output amplitude of the saw tooth waveform obtained with the
following program
a) MOV A, #00
BACK: MOV P1, A
INC A
SJMP BACK
b) MOV R0, #64H
RPT: MOV A, #00
BACK: MOV P1, A
INC A
CJNE A ,R0, BACK
SJMP RPT

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 Example2

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 Example2 contnd…

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 Sine wave generation

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 ALP to generate square wave

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 C program to generate square wave

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 Crude sine wave

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 EXTERNAL MEMORY INTERFACING

• MEMORY ADDRESS DECODING

• The CPU provides the address of the data required, but it is the job of the
decoding circuitry to locate the selected memory block.
• Memory chips have one or more pins called CS (chip select), which
must be activated for the memory’s contents to be accessed.
Sometimes the chip select is also referred to as chip enable (CE).
• In connecting a memory chip to the CPU, note the following points
• The data bus of the CPU is connected directly to the data pins of the
memory chip
• Control signals RD (read) and WR (memory write) from the CPU
are connected to the OE (output enable) and WE (write enable) pins
of the memory chip
• In the case of the address buses, while the lower bits of the address
from the CPU go directly to the memory chip address pins, the
upper ones are used to activate the CS pin of the memory chip
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 Interfacing to Large External Memory

In some applications we need a large amount of memory to

store data
The 8051 can support only 64K bytes of external data
memory since DPTR is 16-bit
To solve this problem, we connect A0 – A15 of the 8051
directly to the external memory’s A0 – A15 pins, and use
some of the P1 pins to access the 64K bytes blocks inside the
single 256K×8 memory chip

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 STACKS

• The stack is a LIFO section of RAM used by the CPU to store information
temporarily.
• This information could be data or an address
• The register used to access the stack is called the SP (stack pointer) register
• the stack pointer in the 8051 is only 8 bit wide, which means that it can
take value of 00 to FFH
• When the 8051 is powered up, the SP register contains value 07. Hence
RAM location 08 is the first location being used for the stack by the 8051
• The storing of a CPU register in the stack is called a PUSH
• SP is pointing to the last used location of the stack
• As we push data onto the stack, the SP is incremented by one

• Loading the contents of the stack back into a CPU register is called a POP
• With every pop, the top byte of the stack is copied to the register specified
by the instruction and the stack pointer is decremented once

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 STACKS
• Example:
• Show the stack and stack pointer from the following. Assume
the default stack area.
• MOV R6, #25H
• MOV R1, #12H
• MOV R4, #0F3H
• PUSH 6
• PUSH 1
• PUSH 4

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 STACKS

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