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Raising a new Generation of Leaders

CEN 513: Module 8

INPUT/OUTPUT
By Omoruyi O. & Olatimehin O.P
 Input and Output
• The input/output or I/O section allows the computer to take in
data from the outside world. Peripherals such as keyboards,
video display terminals, printers, Disk drive controller
and modems are connected to the I/O section.
• The actual physical devices used to interface the computer
buses to external systems are often called ports. An input port
allows data from a keyboard, an A/D converter, or some other
source to be read into the computer under control of the CPU.
An output port is used to send data from the computer to some
peripheral, such as a video display terminal/ Screen, a printer,
or a D/A converter.
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 Input and Output (cont’d)
• Physically, the simplest type of input or output port is just a set of
parallel D flip-flops. If they are being used as an input port, the D
inputs are connected to the external device, and the Q outputs are
connected to the data bus which runs to the CPU. Data will then be
transferred through the latches when they are enabled by a control
signal from the CPU.
• In a system where they are being used as an output port, the D
inputs of the latches are connected to the data bus, and the Q
outputs are connected to some external device. Data sent out on
the data bus by the CPU will be transferred to the external device
when the latches are enabled by a control signal from the CPU.

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 I/O Ports
• I/O devices are connected to the computer
through I/O circuits. Each of these circuits
contains several register called I/O Ports. Some
are used for data while others are used control
commands. Like memory locations, the I/O ports
have address and they are connected to the bus
system. These addresses are known as I/O
address and can only be use in input (IN) or
output (OUT) instructions.
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Input/Output Problems
• Wide variety of peripherals
– Delivering different amounts of data
– At different speeds
– In different formats
• All slower than CPU and RAM
• Need I/O modules

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Input/Output Module
• Interface to CPU and Memory
• Interface to one or more peripherals

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Generic Model of I/O Module

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External Devices
• Human readable
– Screen, printer, keyboard
• Machine readable
– Monitoring and control
• Communication
– Modem
– Network Interface Card (NIC)

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External Device Block
Diagram

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I/O Module Function
• Control & Timing
• CPU Communication
• Device Communication
• Data Buffering
• Error Detection

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I/O Steps
• CPU checks I/O module device status
• I/O module returns status
• If ready, CPU requests data transfer
• I/O module gets data from device
• I/O module transfers data to CPU
• Variations for output, DMA, etc.

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I/O Module Diagram

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I/O Module Decisions
• Hide or reveal device properties to CPU
• Support multiple or single device
• Control device functions or leave for CPU
• Also O/S decisions
– e.g. Unix treats everything it can as a file

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Input Output Techniques
• Programmed
• Interrupt driven
• Direct Memory Access (DMA)

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Three Techniques for
Input of a Block of Data

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Programmed I/O
• CPU has direct control over I/O
– Sensing status
– Read/write commands
– Transferring data
• CPU waits for I/O module to complete operation
• Wastes CPU time

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Programmed I/O - detail
• CPU requests I/O operation
• I/O module performs operation
• I/O module sets status bits
• CPU checks status bits periodically
• I/O module does not inform CPU directly
• I/O module does not interrupt CPU
• CPU may wait or come back later

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I/O Commands
• CPU issues address
– Identifies module (& device if >1 per module)
• CPU issues command
– Control - telling module what to do
• e.g. spin up disk
– Test - check status
• e.g. power? Error?
– Read/Write
• Module transfers data via buffer from/to device

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Addressing I/O Devices
• Under programmed I/O data transfer is very like memory
access
• Each device given unique identifier
• CPU commands contain identifier (address)

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I/O Mapping
• Memory mapped I/O
– Devices and memory share an address space
– I/O looks just like memory read/write
– No special commands for I/O
• Large selection of memory access commands available
• Isolated I/O
– Separate address spaces
– Need I/O or memory select lines
– Special commands for I/O
• Limited set

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Memory Mapped and Isolated
I/O

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Interrupt Driven I/O
• Overcomes CPU waiting
• No repeated CPU checking of device
• I/O module interrupts when ready

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Interrupt Driven I/O
Basic Operation
• CPU issues read command
• I/O module gets data from peripheral whilst CPU does other
work
• I/O module interrupts CPU
• CPU requests data
• I/O module transfers data

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Simple Interrupt
Processing

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CPU Viewpoint
• Issue read command
• Do other work
• Check for interrupt at end of each instruction cycle
• If interrupted:-
– Save context (registers)
– Process interrupt
• Fetch data & store

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Changes in Memory and Registers
for an Interrupt

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Design Issues
• How do you identify the module issuing the interrupt?
• How do you deal with multiple interrupts?
– i.e. an interrupt handler being interrupted

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Identifying Interrupting
Module (1)
• Different line for each module
– PC
– Limits number of devices
• Software poll
– CPU asks each module in turn
– Slow

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Identifying Interrupting
Module (2)
• Daisy Chain or Hardware poll
– Interrupt Acknowledge sent down a chain
– Module responsible places vector on bus
– CPU uses vector to identify handler routine
• Bus Master
– Module must claim the bus before it can raise interrupt
– e.g. PCI & SCSI

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Multiple Interrupts
• Each interrupt line has a priority
• Higher priority lines can interrupt lower priority lines
• If bus mastering only current master can interrupt

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Example - PC Bus
• 80x86 has one interrupt line
• 8086 based systems use one 8259A interrupt controller
• 8259A has 8 interrupt lines

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Sequence of Events
• 8259A accepts interrupts
• 8259A determines priority
• 8259A signals 8086 (raises INTR line)
• CPU Acknowledges
• 8259A puts correct vector on data bus
• CPU processes interrupt

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ISA Bus Interrupt System
• ISA bus chains two 8259As together
• Link is via interrupt 2
• Gives 15 lines
– 16 lines less one for link
• IRQ 9 is used to re-route anything trying to use IRQ 2
– Backwards compatibility
• Incorporated in chip set

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82C59A Interrupt
Controller

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Intel 82C55A
Programmable Peripheral Interface

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Keyboard/Display Interfaces
to 82C55A

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Direct Memory Access
• Interrupt driven and programmed I/O require active CPU
intervention
– Transfer rate is limited
– CPU is tied up
• DMA is the answer

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DMA Function
• Additional Module (hardware) on bus
• DMA controller takes over from CPU for I/O

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Typical DMA Module Diagram

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DMA Operation
• CPU tells DMA controller:-
– Read/Write
– Device address
– Starting address of memory block for data
– Amount of data to be transferred
• CPU carries on with other work
• DMA controller deals with transfer
• DMA controller sends interrupt when finished

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DMA Transfer Cycle Stealing
• DMA controller takes over bus for a cycle
• Transfer of one word of data
• Not an interrupt
– CPU does not switch context
• CPU suspended just before it accesses bus
– i.e. before an operand or data fetch or a data write
• Slows down CPU but not as much as CPU doing transfer

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DMA and Interrupt Breakpoints During an
Instruction Cycle

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Aside
• What effect does caching memory have on DMA?
• What about on board cache?
• Hint: how much are the system buses available?

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DMA Configurations (1)

• Single Bus, Detached DMA controller

• Each transfer uses bus twice
– I/O to DMA then DMA to memory
• CPU is suspended twice

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DMA Configurations (2)

• Single Bus, Integrated DMA controller

• Controller may support >1 device
• Each transfer uses bus once
– DMA to memory
• CPU is suspended once
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DMA Configurations (3)

• Separate I/O Bus

• Bus supports all DMA enabled devices
• Each transfer uses bus once
– DMA to memory
• CPU is suspended once
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Intel 8237A DMA Controller
• Interfaces to 80x86 family and DRAM
• When DMA module needs buses it sends HOLD signal to processor
• CPU responds HLDA (hold acknowledge)
– DMA module can use buses
• E.g. transfer data from memory to disk
1. Device requests service of DMA by pulling DREQ (DMA request) high
2. DMA puts high on HRQ (hold request),
3. CPU finishes present bus cycle (not necessarily present instruction) and puts high on HDLA (hold
acknowledge). HOLD remains active for duration of DMA
4. DMA activates DACK (DMA acknowledge), telling device to start transfer
5. DMA starts transfer by putting address of first byte on address bus and activating MEMR; it then activates
IOW to write to peripheral. DMA decrements counter and increments address pointer. Repeat until count
reaches zero
6. DMA deactivates HRQ, giving bus back to CPU

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8237 DMA Usage of Systems
Bus

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Fly-By
• While DMA using buses processor idle
• Processor using bus, DMA idle
– Known as fly-by DMA controller
• Data does not pass through and is not stored in DMA chip
– DMA only between I/O port and memory
– Not between two I/O ports or two memory locations
• Can do memory to memory via register
• 8237 contains four DMA channels
– Programmed independently
– Any one active
– Numbered 0, 1, 2, and 3

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I/O Channels
• I/O devices getting more sophisticated
• e.g. 3D graphics cards
• CPU instructs I/O controller to do transfer
• I/O controller does entire transfer
• Improves speed
– Takes load off CPU
– Dedicated processor is faster

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I/O Channel Architecture

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Interfacing
• Connecting devices together
• Bit of wire?
• Dedicated processor/memory/buses?
• E.g. FireWire, InfiniBand

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Conclusion
• Thank you.

• References
• Apeh, S. Lecture notes on Advanced
Microcomputer systems, 2015

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