www.covenantuniversity.edu.

ng

Raising a new Generation of Leaders

CEN 522: Microprocessor

System and Interfacing
Interrupts and Interrupt system by
Omoruyi O.
 Topic
• Interrupts
• Organisation of the interrupt system
• Interrupt vectors
• Implementation of single and multiple
Interrupts

2
 Interrupts
• When you come to my office, and I have other
business to attend to, I tell you to come back later.
• What if you were with your Parents, out of a sense of
respect, I will not do the same.
• The smarter thing would be to stop my present
activity and take care of your case.
• In this case, human memory serves me because I will
probably need to remember where I left off in that
activity when I am through with you and your parents.
3
 Interrupts
• An Interrupt in a CPU is modelled in this way.
• An interrupt is either a hardware-generated CALL
(externally derived from a hardware signal) or a
software-generated CALL (internally derived from
the execution of an instruction or by some other
internal event).
• At times, an internal interrupt is called an exception.
Either type interrupts the program by calling an
interrupt service procedure (ISP) or interrupt handler.
4
 Types of interrupt
• There are two main types of interrupt in the 8086
microprocessor, internal and external hardware
interrupts.
• Internal interrupts are software calls like INT, INTO,
and INT 3 or are initiated by the state of the CPU
(e.g. divide by zero error) or by an instruction.
• External interrupts are hardware type calls.
Hardware interrupts occur when a peripheral device
asserts an interrupt input pin of the microprocessor.
5
Sources of interrupts in 8086
microprocessor
• One source is an external signal applied to the non-
maskable interrupt (NMI) input pin or to the interrupt
input pin.
• A second source of an interrupt is execution of the
interrupt instruction or other interrupt-type instruction.
(e.g. INT, INTO etc.)
• The third source of an interrupt is some error condition
produced in the 8086 by the execution of an instruction.
An example of this is the divide by zero interrupt.

6
The Operation of an Interrupt sequence on the 8086 Microprocessor:

1. External interface sends an interrupt signal, to the Interrupt Request (INTR) pin, or an internal interrupt
occurs.
2. The CPU finishes the present instruction (for a hardware interrupt) and sends Interrupt Acknowledge
(INTA) to hardware interface.
3. The interrupt type N is sent to the Central Processor Unit (CPU) via the Data bus from the hardware
interface.
4. The contents of the flag registers are pushed onto the stack.
5. Both the interrupt (IF) and (TF) flags are cleared. This disables the INTR pin and the trap or single-step
feature.
6. The contents of the code segment register (CS) are pushed onto the Stack.
7. The contents of the instruction pointer (IP) are pushed onto the Stack.
8. The interrupt vector contents are fetched, from (4 x N) and then placed into the IP and from (4 x N +2)
into the CS so that the next instruction executes at the interrupt service procedure addressed by the
interrupt vector.
9. While returning from the interrupt-service routine by the Interrupt Return (IRET) instruction, the IP, CS
and Flag registers are popped from the Stack and return to their state prior to the interrupt.
7
 Interrupt vectors

An interrupt vector is a 4-byte number stored in

the first 1024 bytes of the memory(00000H–003FFH)
when the microprocessor operates in the real mode.
In the protected mode, the vector table is replaced
by an interrupt descriptor table that uses 8-byte
descriptors to describe each of the interrupts. There
are 256 different interrupt vectors, and each vector
contains the address of an interrupt service
procedure.
8
Intel interrupt vectors

9
 Interrupt vectors
Table 4-1 lists the interrupt vectors, with a
brief description and the memory location of
each vector for the real mode. Each vector
contains a value for IP and CS that forms the
address of the interrupt service procedure.
The first 2 bytes contain the IP, and the last 2
bytes contain the CS. Here is a more detailed
description of each vector:
10
 Interrupt vectors
DIVIDE-BY-ZERO INTERRUPT-TYPE 0:
The 8086 will automatically do a type 0 interrupt if the result of a DIV operation or an IDIV operation is
too large to fit in the destination register. For a type 0 interrupt, the 8086 pushes the flag register on
the stack, resets IF and TF and pushes the return addresses on the stack.
SINGLE STEP INTERRUPT-TYPE 1:
The use of single step feature found in some monitor programs and debugger programs. When you tell
a system to single step, it will execute one instruction and stop. If they are correct we can tell a system
to single step, it will execute one instruction and stop. We can then examine the contents of registers
and memory locations. In other words, when in single step mode a system will stop after it executes
each instruction and wait for further direction from you. The 8086 trap flag and type 1 interrupt
response make it quite easy to implement a single step feature direction.
NON-MASKABLE INTERRUPT-TYPE 2:
The 8086 will automatically do a type 2 interrupt response when it receives a low to high transition on
its NMI pin. When it does a type 2 interrupt, the 8086 will push the flags on the stack, reset TF and IF,
and push the CS value and the IP value for the next instruction on the stack. It will then get the CS
value for the start of the type 2 interrupt service procedure from address 0000AH and the IP value for
the start of the procedure from address 00008H.

11
 Interrupt Vectors
BREAKPOINT INTERRUPT-TYPE 3:
The type 3 interrupt is produced by execution of the INT3 instruction. The main
use of the type 3 interrupt is to implement a breakpoint function in a system.
When we insert a breakpoint, the system executes the instructions up to the
breakpoint and then goes to the breakpoint procedure. Unlike the single step
which stops execution after each instruction, the breakpoint feature executes all
the instructions up to the inserted breakpoint and then stops execution.
OVERFLOW INTERRUPT-TYPE4:
The 8086 overflow flag will be set if the signed result of an arithmetic operation
on two signed numbers is too large to be represented in the destination register
or memory location. For example, if you add the 8 bit signed number 01101100
and the 8 bit signed number 010111101, the result will be 10111101. This would
be the correct result if we were adding unsigned binary numbers, but it is not the
correct signed result.
12
 Interrupt vectors
SOFTWARE INTERRUPTS-TYPE 0 THROUGH 255:
The 8086 INT instruction can be used to cause the 8086 to do any one of
the 256 possible interrupt types. The desired interrupt type is specified
as part of the instruction. The instruction INT 32, for example will cause
the 8086 to do a type 32 interrupt response. The 8086 will push the flag
register on the stack, reset TF and IF, and push the CS and IP values of
the next instruction on the stack.
INTR INTERRUPTS-TYPES 0 THROUGH 255:
The 8086 INTR input allows some external signal to interrupt execution
of a program. Unlike the NMI input, however, INTR can be masked so that
it cannot cause an interrupt. If the interrupt flag is cleared, then the INTR
input is disabled. IF can be cleared at any time with CLEAR instruction.

13
 Interrupt vectors
The address of the interrupt vector is determined by multiplying the
interrupt type number by 4. For example, the INT 10H instruction
calls the interrupt service procedure whose address is stored
beginning at memory location 40H (10H × 4) in the real mode.
In the protected mode, the interrupt descriptor is located by
multiplying the type number by 8 instead of 4 because each
descriptor is 8 bytes long.
Each INT instruction is 2 bytes long. The first byte contains the
opcode, and the second byte contains the vector type number. The
only exception to this is INT 3, a 1-byte special software interrupt
used for breakpoints.

14
 PRIORITY OF 8086 INTERRUPTS

If two or more interrupts occur at the same time then

the highest priority interrupt will be serviced first, and
then the next highest priority interrupt will be serviced.
As a example suppose that the INTR input is enabled, the
8086 receives an INTR signal during the execution of a
divide instruction, and the divide operation produces a
divide by zero interrupt. Since the internal interrupts-
such as divide error, INT, and INTO have higher priority
than INTR the 8086 will do a divide error interrupt
response first.
15
Priority of interrupts in 8086

16
Flag registers (revision)

17
 8086 Interrupt Pins and
Timing
• INTR: Interrupt Request. Activated by a peripheral device to interrupt the
processor.
 Level triggered. Activated with a logic 1.
• INTA: Interrupt Acknowledge. Activated by the processor to inform the
interrupting device the interrupt request (INTR) is accepted.
 Level triggered. Activated with a logic 0.
• NMI: Non-Maskable Interrupt. Used for major system faults such as parity
errors and power failures.
 Edge triggered. Activated with a positive edge (0 to 1) transition.
 Must remain at logic 1, until it is accepted by the processor.
 Before the 0 to 1 transition, NMI must be at logic 0 for at least 2 clock cycles.
 No need for interrupt acknowledgement.

18
8086 Pin diagram

19
 Single Interrupt lines
• The microprocessor only has one interrupt request
(INTR) line which is triggered by a 1 signal. All hardware
devices use this line to generate an interrupt request.
• When say the INTR line goes high the microprocessor
does not have enough information to determine which
of the possible interrupting devices is requesting
attention. The device must be identified in order for the
microprocessor to run the appropriate service routine.

20
 Multiple Interrupts
• If more than one device is connected to the interrupt
line, the processor needs to know to which device
service routine it should branch to. The identification
of the device requesting service can be done in either
hardware or software, or a combination of both. The
three main methods are:
• Software Polling,
• Hardware Polling, (Daisy Chain),
• Hardware Identification (Vectored Interrupts).
21
 Software Polling
• A software routine is used to identify the device
requesting service. A simple polling technique is
used, each device is checked to see if it was the
one needing service.
• Having identified the device, the processor then
branches to the appropriate interrupt-handling-
routine address for the given device. The order in
which the devices appear in the polling sequence
determines their priority
22
Software polling

23
Hardware polling (Daisy Chain)

This is significantly faster than a pure

software approach. A daisy chain is used to
identify the device requesting service.

24
 Daisy chaining
Daisy chaining is used for level sensitive interrupts, which act like a wired 'OR'
gate. Any requesting device can take the interrupt line low, and keep it asserted
low until it is serviced. Because more than one device can assert the shared
interrupt line simultaneously, some method must be employed to ensure device
priority. This is done using the interrupt acknowledge signal generated by the
processor in response to an interrupt request. Each device is connected to the
same interrupt request line, but the interrupt acknowledge line is passed through
each device, from the highest priority device first, to the lowest priority device last.
After preserving the required registers, the microprocessor generates an interrupt
acknowledge signal. This is gated through each device. If device 1 generated the
interrupt, it will place its identification signal on the data bus, which is read by the
processor, and used to generate the address of the interrupt-service routine. If
device 1 did not request the servicing, it will pass the interrupt acknowledge signal
on to the next device in the chain. Device 2 follows the same procedure, and so on.

25
 Hardware Identification (Vectored Interrupts)

• This is the fastest system. The onus is placed on the

requesting device to request the interrupt, and
identify itself. The identity could be a branching
address for the desired interrupt-handling routine.
• If the device just supplies an identification number,
this can be used in conjunction with a lookup table to
determine the address of the required service
routine. Response time is best when the device
requesting service also supplies a branching address.
26
 PIC (Priority Interrupt
•
Controllers)
Priority Interrupt Controller Chips (PIC's) are hardware chips designed to make
the task of a device presenting its own address to the CPU simple. The PIC
also assesses the priority of the devices connected to it. Modern PIC's can also
be programmed to prevent the generation of interrupts which are lower than
a desired level.
• The decoded location is connected to the output of a priority encoder. The
input of the priority encoder is connected to each device. When a device
requests service, the priority encoder presents a special code combination
(unique for each device) to the decoded memory location. The port thus holds
the value or address associated with the highest device requesting service.
• The priority encoder arranges all devices in a list, devices given a lower
priority are serviced when no other higher priority devices need servicing.
This simplifies the software required to determine the device, resulting in an
increase in speed.
27
PIC (Priority Interrupt
Controller)

28
PIC (Intel 8259)

29
 8259a Priority Interrupt Controller

• In a small system, for example, we might read ASCII characters in

from a keyboard on an interrupt basis; count interrupts from
timer to produce a real time clock of second, minutes and hours
and detect several emergency or job done conditions on an
interrupt basis. Each of these interrupt applications requires a
separate interrupt input. If we are working with an 8086 , we
have problem here because the 8086 has only two interrupt
inputs, NMI and INTR. If we save NMI for a power failure interrupt,
this leaves only one input for all the other applications. For
applications where we have interrupts from multiple sources, we
use an external device called a priority interrupt controller.

30
 Interrupt Applications
• Hardware Interrupt Applications:
- Simple Interrupt Data Input
- Counting Applications
- Timing Applications:
• Software interrupts are used to call Basic Input Output
System, or BIOS, procedures in an IBM PC-type
computer.
• Software interrupt instruction INT N can be used to
test any other type of interrupt procedure.
31
Conclusion
• Thank you!

32
References
1. The Intel Microprocessor, Architecture, Programming
and Interfacing, 6th Ed., by Barr B Brey.
2. An introduction to interrupts
http://www.electronics.dit.ie/staff/tscarff/Interrupts/inter
rupts.htm
3. Interrupts and Interrupt applications:
https://www.ukessays.com/essays/education/interrupts-
and-interrupt-applications.php
4. Interrupts and Polling: LCS, Edinburgh Lecture notes
33