Verilog Dataflow Modeling

Vasudeva Murthy T

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 Session Objectives

• To learn to write a simple Verilog code

• To understand the different modeling styles in Verilog
• To understand the semantics of the language
• To comprehend the relevance of Operators
• To understand the inference of hardware from Verilog
operators
• To identify the salient features of dataflow modeling

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 Session Topics

• Verilog module and port declaration

• Four valued logic
• Number representation
• Dataflow modeling style
• Verilog Operators
• Inference of hardware from operators
• Continuous assignment statements

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 Introduction to Integrated Circuits
• As more and more complex functions are required in
various data processing and telecommunications devices,
the need to integrate these functions in a small
system/package is also necessary.
• This increase demand has led to the development of
sophisticated tools and advanced technologies for
integration of systems.
• The level of integration as measured by the number of
logic gates in a monolithic chip has been steadily rising
for almost three decades.
• The objective of this session is to learn and understand the
concepts of Integrated Circuits

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 Integrated Circuit(IC)
Definition
IC is a collection of a electronic circuits made by
simultaneously forming individual transistors,diodes and
resistors on a small ship of semiconductor material
typically silicon that are interconnected to one another
with a metal,such as aluminum, deposited on the chip
surface
Types
There are two types of IC
– Analog and Digital
– A combination of both on one chip is hybrid or
mixed signal design
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 Why Integrated Circuits

•High performance(speed ,
throughput)
•High reliability
•High complexity
•High applicability
•Fast design time
•Simple design process
•Low power dissipation
•Low power consumption
•Low cost

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 IC Quality Matrices

• Area (Cost)
• Speed (Value)
• Power Consumption (Energy Efficiency)
• Manufacturability
• Testability
• Reliability
• Time-to-market(TTM); Time-to-profit
• Know your boundary conditions

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 Cost factors in ICs

• For large-volume ICs:

• packaging is largest cost;
• testing is second-largest cost.
• For low-volume ICs, design costs may swamp all
manufacturing costs.
• Current cost: $2-3 billion.
• Typical fab line occupies about 1 city block, employs a
few hundred people.
• Most profitable period is first 18 months-2 years.

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 How to cope with complexity?
• In order to make the best use of the current
technology, the chip development time has to be short
enough to allow the maturing of chip and timely
delivery to customers.
• As a result, the level of actual logic integration tends
to fall short of the integration level achievable with
the current processing technology.
• Sophisticated computer-aided design (CAD) tools and
methodologies are developed and applied in order to
manage the rapidly increasing design complexity.

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 How to cope with complexity?

By applying:
– Rigid design
methodologies Rigid Design
Methodologies
– Design automation

Design Automation
(CAE Tools)

Successful
Design

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 Why Electronic Design Automation?

Imagine a Intel based micro processor having 1.5

million transistors. Would it be feasible to design such
a complex system with help of truth table and K-maps?

Obviously Impossible.

Today’s semiconductors and electronic systems are

complex that designing them would be impossible
without electronic design automation (EDA).

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Four Phases in Creating a Chip

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 Specification
• A specification of what to construct is the first major
step.
• Compromise between what is wanted and what can be
made requires extensive experience to define best
compromise
• A detailed specification must be agreed upon with the
system people. Major changes during design will result
in significant delays.
• Requirements must be considered at many levels
- System, sub-system, Board, Hybrid, IC
• Specifications can (must) be verified by system
simulations.

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 VLSI Design Cycle

• System Specification – Specification of the size,

speed, power and functionality of the VLSI system.

• Architectural Design – Decisions on the

architecture, e.g., RISC/CISC, # of ALU’s, pipeline
structure, cache size, etc. Such decisions can provide
an accurate estimation of the system performance,
die size, power consumption, etc.

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 VLSI Design Cycle
Functional Design – Identify main functional units and
their interconnections. No details of implementation .

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 VLSI Design Cycle

• Logic Design – Design the logic, e.g., boolean

expressions, control flow, word width, register
allocation, etc. The outcome is called an RTL (Register
Transfer Level) description. RTL is expressed in a
HDL (Hardware Description Language), e.g., VHDL
and Verilog.

X = (AB+CD)(E+F)
Y= (A(B+C) + Z + D)

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 VLSI Design Cycle
• Circuit Design – Design the circuit including gates,
transistors, interconnections, etc. The outcome is
called a netlist.

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 VLSI Design Cycle
• Physical Design – Convert the netlist into a geometric
representation. The outcome is called a layout.

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 VLSI Design Cycle

• Fabrication – Process includes lithography, polishing,

deposition, diffusion, etc., to produce a chip.

• Packaging – Put together the chips on a PCB (Printed

Circuit Board) or an MCM (Multi-Chip Module)

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 VLSI Design Cycle

System Specification Netlist

Architectural Physical
Design Design

Architectural Layout
Specification Circuit Design
or Fabrication
Functional
Logic Synthesis
Design
Chips
Timing & relationship
Packaging
between functional units
Logic Packaged and
Design
tested chips
RTL in HDL

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 Design Domains
Behavioral
• what a system does

Structural
• how entities are connected together to perform the
behavior

Physical (geometrical)
• how to build a structure that has the required
connectivity to implement the prescribed behavior

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 Motivation for HDLs
• Present Digital system complexity
• No longer able to breadboard systems
– Number of chips
– Number of components
– Number of interconnects
• Need to simulate and verify before committing to
hardware
• Hardware description languages (HDLs)
– Are computer-based hardware programming languages
– Allow modeling and simulating the functional behavior and
timing of digital hardware
– Synthesis tools take an HDL description and generate a
technology-specific netlist

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 Why HDLs
• More and more transistors can fit on a chip
– Allows larger designs!
– But working at transistor/gate level for large designs is hard
• Abstract large hardware designs!
– Describe what you need the hardware to do
– Tools then design the hardware for you
• Simplified & faster design process
• Lessen the time spent debugging the design
– Design errors still possible, but in fewer places
– Generally easier to find and fix
• Can reuse design to target different technologies
– Don’t manually change all transistors for rule change
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 Advantages of using HDLs
• Designs can be described at various levels of abstractions
• Top-Down Approach and hierarchical designs for large
projects
• Functional Simulation Early in the Design Flow
• Automatic Conversion of HDL Code to Gates
– With user level control, Consistent quality, Fast
• Early Testing of Various Design Implementations
– Due to fast synthesis, there is a scope for trying different
implementations
• Design Reuse
– Technology independence, standardization, portability, ease of
maintenance

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 Introduction to HDLs
• Two popular HDLs originated in the mid-80s
– VHDL – (Very large scale integrated circuit
Hardware Description Language)
• A very structured language
• Tough to master
• Efficient for higher level functions
• Many IEEE libraries
– Verilog – Verification of Logic
• Language built mostly on C
• Easy to learn
• Difficult to debug!!

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 Introduction to Verilog
Verilog HDL
– HDL developed in 1984/5
– Simple and effective way of describing digital circuits
– Intended for modeling, simulation and analysis
– Language became property of Gateway Design
Automation
– Language open to public since 1990
– Since 1995: IEEE Standard 1364
– Latest version Verilog 2001

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 Intro to Verilog (contd) . . .
• Originally a modeling language for a very efficient event-
driven digital logic simulator
• Later pushed into use as a specification language for logic
synthesis
• Now, one of the two most commonly-used languages in
digital hardware design
• Combines structural and behavioral modeling styles

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 Synthesis of HDLs
• Takes a description of what a circuit does
• Creates the hardware to do it
• HDLs may look like software, but they’re not!
– Not a program
– Doesn’t “run” on anything
• Though we do simulate them on computers
– Don’t confuse them!
• Also use HDLs to test the hardware you create
– This is more like software

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 Other Important HDL Features
• Are highly portable
• Are self-documenting (when commented well)
• Represent parallelism
• Provides many descriptive styles
– Structural
– Register Transfer Level (RTL)
– Behavioral
• Serve as input for synthesis tools

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 HDL Implementation Cycle

DESIGN ENTRY
Verilog
Functional Simulation

SYNTHESIS

Gate level simulation

Implementation
MAP, PLACE ,
ROUTE

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 Verilog ‘Module’
• A design in verilog is modeled using the concept of
“module”
• The module items define what constitutes a module, and
include many different types of declarations and
definitions
• A module will have two parts
– A port declaration part
• Ports represent the external interfaces of the design
– A functional description part
• Functional description describes the functionality of the logic
being designed

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 “Module”

• Module interface is defined using ports

• each port must be explicitly declared as one of
• input (wire or other net)
• output (reg or wire; can be read inside the module)
• inout (wire or other net)
• Modules contain local signals, etc.

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 Sample Code

in Z

module buffer (output Z, input in);

assign #1 Z = in;
endmodule
• Here the design is named as ‘buffer’
• It has an input port by name ‘in’ and a output port by name ‘Z’
• Data is simply traveling from input to output
• After any change in input ‘in’ it takes 1 time unit to travel to output
‘Z’

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 Verilog Module explained
• A module definition shall be enclosed between the
keywords module and endmodule
• The identifier following the keyword module shall be the
name of the module being defined
• The optional list of ports shall specify an ordered list of
the module's ports
• Modules declarations cannot be nested
• Modules may contain instances of other modules
• Modules are:
– Declared
– Instantiated

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 Declaring a module
• Can’t use keywords as module/port/signal names
– Choose a descriptive module name
• Naming restrictions
– Contain character [a-z, A-Z,_,$]
– Start with an alphabet
• Indicate the ports (connectivity)
• Declare the signals connected to the ports
– Choose descriptive signal names
• Declare any internal signals
• Write the internals of the module (functionality)

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 Declaring Ports
• Declare type of port
– input
– output
– inout (bidirectional)
• Scalar (single bit) - don’t specify a size
– input cin;
• Vector (multiple bits) - specify size using range
– Range is MSB to LSB (left to right)
– Don’t have to include zero if you don’t want to… (D[2:1])
– output OUT [7:0];
– input IN [0:4];

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 Comments
• Verilog supports 2 type of comment syntaxes
– Single line comment start with //, and end with newline.
– Block comment, start with /*, and end with */.
– Block comment cannot be nested.
• Example
/* This is how you comment out a number of lines in
Verilog. Can be used to intricately describe a code. The
comment stops where it encounters this => */

– input status; // 0:ready, 1:not ready

Line comments
– output data; // sync with clock mClock

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 Levels of Modeling
• Structural modeling :
• Use primitives and lower-level module instantiations.
• – logic gates and Verilog primitives
• Very close to physical implementation.
• Easy (straightforward) synthesis.
• Dataflow modeling :
• Define output signals in terms of input signal transformations.
• Behavioral modeling :
• Specify algorithmically the expected behavior of the system.
• Close to natural language description.
• Most difficult to synthesize.
• Best for verification.

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 Dataflow modeling explained
• Dataflow modeling consists of continuous assignment
statements
– They start with the keyword ‘assign’
– These statements are always active
– They are executed whenever there is a change in a variable on
the right hand side of the statement
– They are used when the system being designed can be
completely represented in Boolean equation format
– Several assignment statements are concurrent in nature
• They execute together
– Implicit continuous assignment is also possible
– They can also represent the propagation delay from input to
output

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 Language Conventions
• Case sensitivity
– Verilog is case-sensitive
– Some simulators are case-insensitive
– Advice: - Don’t use case-sensitive feature!
– Keywords are always lower case
• Different names must be used for different items
within the same scope
• Identifiers can have
– Upper case and lower case alphabets
– Decimal Digits (but should not start with digits)
– Underscore (again not at the beginning)

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 Language semantics
• All statements are terminated with ‘;’
• Comments :
– all characters after ‘//’ in a line are treated as comments
– multiple line comments begin and end with ‘*’
• Compiler directives begin with `
• Built in system task and functions begin with ‘$’
• Strings enclosed with double quotes must be on one line

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 Four Valued Logic
A single bit can have one of FOUR values
– 0 Numeric 0, logical FALSE
– 1 Numeric 1, logical TRUE
– x Unknown or ambiguous value
– z No value (high impedance)

Why x?
– Could be a conflict, could be lack of initialization
Why z?
– Nothing driving the signal
– Tri-states

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 Relevance of ‘x’, ‘z’
• In Simulation
– Can detect x or z using special comparison operators

• In Reality
– Cannot detect x or z
– No actual ‘x’ – electrically just 0, 1, or z
– Except for some uninitialized signals, x is bad!
• Multiple strong conflicting drivers => short circuit
• Weak signals => circuit can’t operate, unexpected results
– z means nothing driving signal (tri-state)

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 Resolving 4 valued logic

A OUT A OUT
B B

A B OUT A B OUT
0 0 0 0 0 0
0 1 1 0 1 0
1 1 1 1 1 1
0 x x 0 x 0
0 z x 0 z 0
1 x 1 1 x x
1 z 1 1 z x

OUT A 0 1 x z
A
OUT 1 0 x x

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 Number representation
• Representation: <size>’<base><number>
– size => number of bits (regardless of base used)
– base => base the given number is specified in
– number => the actual value in the given base
• Can use different bases
– d or D : Decimal – default if no base specified!
– h or H : Hexadecimal Hex
– o or O : Octal
– b or B : Binary
• Size defaults to at least 32…
– You should specify the size explicitly!
– Why create 32-bit register if you only need 5 bits?
– May cause compilation errors on some compilers

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 Number system examples
Number Decimal Equivalent Actual Binary
4’d3 3 0011
8’ha 10 00001010
8’o26 22 00010110
5’b111 7 00111
8’b0101_1101 93 01011101
8’bx1101 - xxxx1101
-8’d6 -6 11111010

Numbers with MSB of x or z extended with that value

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 Data Types
• Verilog has basically two data types
– Net
• Represent interconnects (physical wires)
• Various kinds – wire, tri, supplu0, supply1 etc
– Register
• Represent storage/ memory concept
• Various kinds – reg, integer, time

• More of this later

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 Operators

• For a system to be represented in boolean equation format

some operators are required
• Operators represent some pre-defined functions and are
well defined in the verilog language
• Not all operators have a hardware equivalent

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 Operators
Unary +, -, !, ~, &, ~&, ^, ~^, ^~, |, ~|
Arithmetic ** (power) , *, /, %, +, -
Shift <<, >>, <<<, >>>
Relational <, <=, >, >=
Equality ==, !=, ===, !==
Bitwise ~, &, ^, ~^, ^~, |
Logical !, &&, ||
Conditional ?:
Concatenation {}, {{}}
• Unary operators also known as reduction operators
• Concatenation operators also used as replication operator
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 Operator hardware inference
• Unary/ Reduction Operators:
– Also known as reduction operator as they can operate on any
n-bit operand and reduce them to one bit
– All the operators have their equivalent hardware
– ‘+’ and ‘-’ unary operators are used to signify the sign of any
operand, need not necessarily equate to hardware
– Example:
module AND(output Z, input [4:0] oper)
assign #2 Z = &oper; // where oper is 5 bit variable
endmodule
Gate has delay of 2 time units
oper[4]
oper[3]
oper[2]
oper[1] Z
oper[0]

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 Arithmetic Operators
Arithmetic Operators :
• Result in basic adders, subtractors, multiplier
• No support for synthesis of divider and modulus in FPGA as of
now
• Divide operator will synthesis if and only if denominator is a power
of 2
– Example
module wrong_divide(output Z, input [4:0] oper)
assign Z = oper/3’d6; // will not synthesize
endmodule

module correct_divide(output Z, input [4:0] oper)

assign Z = oper/4’d8; // will synthesize as the denominator is 2 3
endmodule
What will the hardware be??

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 Equality Operators
• Relational and equality operators result in comparator/
xor / xnor gates
• Case equality operators (===, !==)
– Do not have any logical hardware equivalent
– They match strings and used mainly in test benches
• Conditional operator
– Results in multiplexer kind of structure
– Also known as ternary operator as it take three operands
– Only operator which takes exactly 3 operands
– All operands should be available
– Conditional operators can be nested
module wrong_condition(output Z, input x, data)
assign Z = (x == 1’b1) ? data : ; // wrong as second option not existent
endmodule

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 Conditional Operator
Example
module comparator (output z , input [2:0] data, oper)
assign z = (oper == data) ? oper : data;
endmodule
data 0
Z
oper 1

oper[0] data[0] oper[1] data[1] oper[2] data[2]

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 Shift Operators
• Shift operators
– Result in shifter kind of logic
– Arithmetic shift operators (>>>, <<<) are realized as normal
shift operators
• Classic example of synthesis simulation mismatch
• Bitwise operators:
– All are synthesizable and have their equivalent hardware
– They are different from unary operators in that the output size
depends on the size of the operands
– Operation is bit by bit basis
– Bitwise and Unary operators look alike
• Operation is context dependent
• If only one operand is being acted upon it is reduction
operator

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 Bitwise Operators
Example:

module bitwise (output [4:0] x, [5:0] y, input [3:0] a,b, input [6:0] c);
assign x = a + c;
assign y = b ^ c;
endmodule

• In the first statement ‘a’ will be appended with a zero to the left and
‘c’ will be truncated by 2 bits from the left
• In the second statement b will appended with 2 zeroes to the left
and c will be truncated one bit from the left

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 Hardware inference
The example shown will result in this hardware
0,a c [4:0] 0,0,b c [5:0]

ADDER XOR Gates

X Y
b[3] b[2] b[1] b[0]
0 C[5] 0 C[4] C[3] C[2] C[1] C[0]

Y[5] Y[4] Y[3] Y[2] Y[1] Y[0]

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 Concatenation Operator
• Concatenation Operators
– Are used to concatenate two or more operands
– Are also used to replicate a given operand for a particular
number of times
– Also known as replication operator – is context dependent
– Example
• assume a = 4’b1001, b= 3’b110
• assign x = {a,b} : x = 1001_110
• assign y = {4{b}} : y = 110_110_110_110
• assign z = {a, 2{b}, a} : z = 1001_110_110_1001

• In the first instance ( x = {a,b}) the operator is concatenating ‘a’ and ‘b’
• In line 2 above (y={2{b}}) the operator is replicating ‘b’ twice
• In the last line both concatenation as well as replication is being done.
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 More examples
//concatenation operator used in the LHS of the assignment statement
module adder(output sum, carry_out,
input a, b, carry_in);
assign {carry_out,sum} = a + b + carry_in;
endmodule

//Verilog code for 4:1 multiplexer

module mux_4_1(output z, input I0, I1, I2, I3, input [1:0] sel);
assign z = (~sel[0]&~sel[1] &I0) | (~sel[0]&sel[1] &I1) |
(sel[0]&~sel[1] &I2) | (sel[0]&sel[1] &I3);
endmodule

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 Dataflow modeling revisited
• Design expressed using operators
• Output is represented as function of input transformations
• Continuous assignment statements drive values into nets
• Left hand side of assignment statement is scalar or vector net
• Left hand side variable can be concatenation of two operands
• Right hand side can be an expression, any other net or a value
Example
• module rhs( output p,q,r , input a,b,c)
assign p = ~ ( a & b );
assign q = 1’b1;
assign #10 r = c ;
endmodule
• Can accommodate delays
– As shown in line 3 of code above ‘r’ is updated 10 time units after there is
change in ‘c’

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 Summary

• Verilog data flow modeling has been discussed

• Number representation, different logics used has been
understood
• Continuous assignment statements and their operation has
been studied
• Operators their relevance and usage has been
comprehended
• Briefing of various data types has been given

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