Modeling of Sequential Circuits

Vasudeva Murthy T

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 Session Objectives
• To understand the functioning of various sequential
elements
• To understand the concept of edge sensitivity
• To comprehend the sensitivity list and its relevance
• To learn to differentiate between combinational and
sequential procedural blocks
• To learn to resolve priority of sensitivity list
• To understand non-blocking statements
• To learn to design counters and clock-dividers
• To learn to model memory

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 Session Topics

• Latch,flip-flop
• Set/Reset and Clear/Preset
• Edge and level Sensitivity
• Non-blocking statements
• Counters and clock-dividers
• Memory

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 Functioning of sequential circuits
clock

control
data
o/p of f-f xxxxxxxxx
for reset
o/p of f-f xxxxx
for clear
xxxxxxxxx
o/p of latch
for reset

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 Priority of Signals
• In a sequential circuit clock is the most important signal
• Amongst data and reset, reset has higher priority
• Most of the times reset has higher priority than set
• When a sequential element has clear / preset signal they
assume higher priority than clock
• Clear has higher priority than preset
• Flip-flops are sensitive to the edge of clock
• Latches are sensitive to the level of clock

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 Modeling of sequential circuits
• Upto now only combinational circuits were discussed
• Behavioural modeling was primarily meant for modeling sequential
circuits
• Sequential circuits are best / easily described using behavioural
modeling
• Sensitivity list of the always block very important in deciding kind
of hardware inferred
• Priority of signals is resolved on basis of sensitivity list
• Sequential circuits are different from combinational circuits in that
they have storage elements
• Sequential circuits are primarily built of flip-flops
• Almost all sequential circuits are sensitive to edge of the clock
(generally latches are avoided)
• Sequential circuits can have combinational blocks too

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 Concept of Edges
• Sensitivity list checks for ‘edge’
• A negedge is on the transitions
– 1 -> x, z, 0
– x, z -> 0
• A posedge is on the transitions
– 0 -> x, z, 1
– x, z -> 1

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 Sequential circuit code
Sample code for simple D flip-flop
module dff
(output reg q,
input data, clock);
always@(posedge clock) // edge detecting mechanism in verilog
q = data;
endmodule

Sample code for simple D flip-flop with reset signal

module dff
(output reg q,
input data, reset, clock);
always@(posedge clock) // edge detecting mechanism in verilog
if (reset) q = 1’b0; // flip-flop with synchronous reset
else q = data; // flip-flop waits for edge of clock before it can get reset
endmodule
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 JK flip-flop
Sample code for simple JK flip-flop
module Jk_ff
(output reg q,
input j,k, clock);

always@(posedge clock)
case({j,k})
2’b00 : q = q;
2’b01 : q = 1’b0;
2’b10 : q = 1’b1;
2’b11 : q = ~q;
endcase

endmodule

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 Clear signal
Sample code for simple D flip-flop with clear signal
module dff
(output reg q,
input data, clear_n, clock);
clear_n has equal / higher
always@(posedge clock, negedge clear_n) priority than clock. As soon
if (!clear_n) q = 1’b0; as clear_n goes low,
else q = data; always block will work

endmodule

active low signal of clear_n being

detected. FF will not wait for clock
and is immediately reset

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 Blocking Assignments
• The = token represents a blocking procedural assignment
• Evaluated and assigned in a single step
• Execution flow within the procedure is blocked until the
• assignment is completed
• Evaluations of concurrent statements in the same time
step
• Are blocked until the assignment is completed
//swap bytes in word
always @(posedge clk)
begin
word[15:8] = word[ 7:0];
word[ 7:0] = word[15:8];
end

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 Non-blocking statements
• Sequential circuits have concept of ‘next-cycle’
• Combinational circuit output is directly function of input
• Sequential circuit output depends on input and previous state
• Data takes one clock cycle to travel from one flip-flop to the next
• This functionality of sequential circuits is modeled by the non-
blocking ‘<=’ assignment statement
• In combinational logic the nth level of logic depends on output
of n-1th level.
• In sequential circuits nth level of flip-flops takes the ‘previous’ data
of the n-1th level of flip-flop
• Non-blocking assignments hold the previous value until next clock
cycle

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 Non - Blocking
• The <= token represents a non-blocking assignment
• Evaluated and assigned in two steps:
• The right-hand side is evaluated immediately
• The assignment to the left-hand side is postponed until other
evaluations in the current time step are completed
• Execution flow within the procedure continues until a timing
control is encountered (flow is not blocked)

//swap bytes in word

always @(posedge clk)
begin
word[15:8] = word[ 7:0];
word[ 7:0] = word[15:8];
end

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 Schedule and Allocate
• Statements in same timestep considered simultaneously
• Evaluate all RHS first, then assign in order
• Inter-assignment delays block evaluation and update
• Blocks subsequent statements (in different time step)
– #4 c <= d; #8 e <= f;
• Intra-assignment delays block update but not evaluation
• Does not block subsequent statements
– c <= #4 d; e <= #8 f;
• Non-blocking assignments for a given behavior block are scheduled
after blocking

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 Blocking vs. Non-blocking
– Statements are order – Statements not order dependent
dependent
– Blocking assignments – Non-blocking assignments
statements used to model statement used to model
combinational hardware pipelined sequential hardware
– Blocks execution of – Does not block sub-sequent
subsequent statements unless statements from getting
first statement is evaluated executed
and assigned value
– LHS immediately updates – LHS updated when simulation
has been suspended

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 Order dependency
always always
begin begin
b = a; b <= a; //old value of a
c = b; // in-effect a c <= b; // old value of b
d = c; // in-effect b (a) d <= c; // old value of c
e = d; // in-effect c (b)(a) e <= d; // old value of e
end end

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 Difference between blocking and non-blocking
module test_display();
reg[3:0] a, b; reg clk;
initial begin a = 3; b = 2; clk = 1; end
always@(posedge clk)
begin
a <= #2 a + b;
#2 b <= a - b;
$display("display: t = %t, a = %d, b = %d", $time, a, b);
$strobe("strobe: t = %t, a = %d, b = %d", $time, a, b);
end
initial $monitor("monitor: t = %t, a = %d, b = %d", $time, a, b);
endmodule
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 Output
Non-blocking
# monitor: t = 0, a = 3, b = 2 // initialization
# display: t = 2, a = 3, b = 2 // old values
# monitor: t = 2, a = 5, b = 1 // new values
# strobe: t = 2, a = 5, b = 1 // new values
Blocking
# monitor: t = 0, a = 3, b = 2 // initialization
# monitor: t = 2, a = 5, b = 2 // a assigned
# display: t = 4, a = 5, b = 3 // new values
# strobe: t = 4, a = 5, b = 3 // new values
# monitor: t = 4, a = 5, b = 3 // b assigned

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 Shift register
module piso #(parameter n = 4) if(load) shift = parallel;
(output reg serial, else if(count < 3’d4)
output done, begin
input [n-1:0] parallel, for(j=0; j<n;j=j+1)
input clr_n, load, clock);
shift[j] <= shift[j+1];
reg [n-1:0] shift; count = count +1;
reg [2:0] count; end
always@(posedge clock, negedge clr_n) else done = 1’b1;
if(!clr_n)
begin assign serial = shift[0];
shift = {n{1’b0}}; endmodule
count = 3’b0;
done = 1’b0;
end
else

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 Counters
• Various kinds of counters based on
• Number of output bits
• Number of unique states
• Code sequence
– Straight Binary
– BCD
– Ring Counter
– Johnson Counter
– Gray Counter / Reflective Code
– Up-down Counter
• Synchronous / Asynchronous

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Mod-6 Counter

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 Johnson Counter
//Also known as switch tail ring counter
module johnson #(parameter n = 4)
(output reg [n-1:0] johnson
input clock, clear_n);

always@(posedge clock, negedge clear_n)

if(!clear_n) johnson <= {n{1’b0}};
else johnson <= {!johnson[0], johnson[n:1]};

endmodule

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 Clock Dividers
• Frequently used components in digital designs
• Especially used by FPGA designers
• Consists of flip-flops
• Basically built on counters
• A simple T flip-flop acts like divide by 2 circuit
• A divide by n circuit requires a mod-n counter
• Divide by fraction requires a little tweaking around

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Divide by 3 with 50% duty cycle

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 Memory
• Present day designs are incomplete without memories
• Memories are nothing but a collection of storage elements
• A memory is an array of n-bit registers
– reg [15:0] mem_name [0:127]; //128 16-bit words
– reg array_2D [15:0] [0:127]; // 2D array of 1-bit regs
• Can only access full word of memory
– mem_name[122] = 35; // assigns word
– mem_name[13][5] = 1; // illegal – works in simulation
– array_2D[122] = 35; // illegal – causes compiler error
– array_2D[13][5] = 1; // assigns bit
• Can use continuous assign to read bits
– assign mem_val = mem[13]; // get word in slot 13
– assign out = mem_val[5]; // get bit in slot 5 of word
– assign dataout = mem[addr];
– assign databit = dataout[bitpos];
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 Memory Code
module memory(output [7:0] out, input [7:0] in, input [7:0] addr,
input wr, clk, rst);

reg [7:0] mem [0:255];

reg [8:0] initaddr;
synchronous reset!
always @ (posedge clk) begin
if (rst) begin
for (initaddr = 0; initaddr < 256; initaddr = initaddr + 1) begin
mem[initaddr] <= 8’d0;
synchronous write
end
end else if (wr) mem[addr] <= in;
end synchronous read

always @(posedge clk) out <= mem[addr];

endmodule

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 Local Parameters
• Local Parameters are parameters that are local to a module
• They can not be re-defined from outside the module
• They depend on existing parameters of the module
• They are declared using the keyword ‘localparam’
• Some designs will have some parameters dependent on other
parameters
• Example :
– The depth of a memory depends on the width of address
– Width of address will be parameter of design
– Depth will be a local parameter

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 Local Parameter Example
module ram #(parameter ADDR_SIZE = 10, DATA_SIZE = 8)
(output [DATA_SIZE-1:0] data,
input [ADDR_SIZE-1:0] addr,
input en, rw_n);

localparam MEM_DEPTH = 1<<ADDR_SIZE;

reg [DATA_SIZE-1:0] mem [0:MEM_DEPTH-1];

assign data = (rw_n && en) ? mem[addr] : {DATA_SIZE{1'bz}};

always @*
if (!rw_n && en) mem[addr] <= data;

endmodule

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 Initializing Memories
• Can read values from text file into a “memory”
– This is not synthesizable
• $readmemb(“filename”, memname);
– Reads binary (plain-text) numbers from text file
• $readmemh(“filename”, memname);
– Reads hexadecimal (plain-text) numbers from text file
• Text files can have numbers, spaces, comments
• Can also specify start/end address of memory
– $readmemh(“filename”, memname, start, stop);
• Can fill memory in ascending or decending order by changing the
“start” and “stop” addresses

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 Summary

• The functioning of various sequential elements has been

understood
• Edge edge sensitivity and its relevance has been discussed
• The differences between combinational and sequential
procedural blocks has been comprehended
• Resolving priority of sensitivity list has been understood
• Non-blocking statements have been scrutinized
• Counters and clock-dividers circuit design has been learnt
• Modeling of memory has been discussed

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