Combinational Circuits

◉ A combinational circuit is a connected arrangement of logic gates with a set of inputs

and outputs.
◉ A combinational circuit transforms binary information from the given input data to
the required output data
◉ A combinational circuit can be described by a truth table showing the binary
relationship between the n input variables and the m output variables.
◉ The truth table lists the corresponding output binary values for each of the 2" input
combinations.

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◉ Combinational Circuits are made from 3 Basic Gates; NAND, NOR, NOT
that re combined and connected together to produce more complicated
switching circuits.
◉ These gates are building blocks of Combinational logic circuits.
◉ There are 3 main ways to specify the function of combinational circuits
1. Boolean Algebra
2. Truth Table
3. Logic Diagram

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Classification of Combinational Circuits:
◉ There are three main categories of combinational circuits: arithmetic or
logical functions, data transmission and code converter as given below in
category diagram.

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 Half Adder
◉ Half adder is a combinational logic circuit with two inputs and two outputs.
◉ The half adder circuit is designed to add two single bit binary number A and B. It is the basic
building block for addition of two single bit numbers.
◉ It doesn’t take carry from previous sum
◉ This circuit has two outputs carry and sum.
◉ The Boolean Expression for Half adder is:
Sum = A‘B+AB'
Carry = A.B

Block diagram
Circuit Diagram
Truth Table
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 Full Adder
◉ It is used to add more than single bit
◉ It is a cascading full adders
◉ IC is 4 bit or 8 bit full adders
◉ The full adder is used to add three 1-bit binary numbers A, B, and carry
C. The full adder has three input states and two output states i.e., sum
and carry.

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• The above block diagram describes the construction of the Full adder circuit. In the
above circuit, there are two half adder circuits that are combined using the OR gate.
• The first half adder has two single-bit binary inputs A and B.
• As we know that, the half adder produces two outputs, i.e., Sum and Carry.
• The 'Sum' output of the first adder will be the first input of the second half adder, and
the 'Carry' output of the first adder will be the second input of the second half adder.
• The second half adder will again provide 'Sum' and 'Carry'. The final outcome of the Full
adder circuit is the 'Sum' bit.
• In order to find the final output of the 'Carry', we provide the 'Carry' output of the first
and the second adder into the OR gate. The outcome of the OR gate will be the final
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The full adder circuit construction can also be represented in a Boolean
expression.
Sum:
◉ Perform the XOR operation of input A and B.
◉ Perform the XOR operation of the outcome with carry. So, the sum is (A XOR
B) XOR Cin which is also represented as:
(A ⊕ B) ⊕ Cin
Carry:
◉ Perform the 'AND' operation of input A and B.
◉ Perform the 'XOR' operation of input A and B.
◉ Perform the 'OR' operations of both the outputs that come from the
previous two steps. So the 'Carry' can be represented as:
A.B + (A ⊕ B)
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 Flip Flops
◉ The storage elements employed in clocked sequential circuits are called Flip-Flops.
◉ A Flip flop is capable of storing one bit of information.
◉ It has 1 inputs and 2 outputs.
◉ One output is for normal value and another output is for complement value of a bit
stored to it.
Types of flip-flops:
◉ SR Flip Flop
◉ JK Flip Flop
◉ D Flip Flop
◉ T Flip Flop

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 SR Flip Flop
◉ S-R flip-flop stands for SET-RESET flip-flops.
◉ The SET-RESET flip-flop consists of two NOR gates and also two NAND
gates.

◉ It is a clocked flip flop.

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S.N. Condition Operation
1 S = R = 0 : No If S = R = 0 then output of NAND gates 3 and 4 are forced to become 1.
change Hence R' and S' both will be equal to 1. Since S' and R' are the input of the
basic S-R latch using NAND gates, there will be no change in the state of
outputs.

2 S = 0, R = 1, E = Since S = 0, output of NAND-3 i.e. R' = 1 and E = 1 the output of NAND-4 i.e.
1 S' = 0.
Hence Qn+1 = 0 and Qn+1 bar = 1. This is reset condition.

3 S = 1, R = 0, E = Output of NAND-3 i.e. R' = 0 and output of NAND-4 i.e. S' = 1.

1 Hence output of S-R NAND latch is Qn+1 = 1 and Qn+1 bar = 0. This is the reset
condition.

4 S = 1, R = 1, E = As S = 1, R = 1 and E = 1, the output of NAND gates 3 and 4 both are 0 i.e. S'
1 = R' = 0.
Hence the Race condition will occur in the basic NAND latch.

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 D (Data or Delay) Flip-Flop
◉ D Flip-Flop is a slight modification of SR Flip-Flop. Since SR flip flop suffers from an unavoidable
condition called NO VALUE or RACE CONDITION.
◉ D Flip-Flop is designed to avoid it.
◉ The D input to this Flip-Flop is sole input and is inverted to create a set of two necessary inputs.
◉ This management disables the similar input combinations like [0,0] or [1,1] and only SET, RESET
outputs are evaluated.
◉ D flip-flop operates with only positive clock transitions or negative clock transitions.

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S.N Condition Operation
.

1 E=0 Latch is disabled. Hence no change in output.

2 E = 1 and D = 0 If E = 1 and D = 0 then S = 0 and R = 1. Hence irrespective of
the present state, the next state is Qn+1 = 0 and Qn+1 bar = 1.
This is the reset condition.

3 E = 1 and D = 1 If E = 1 and D = 1, then S = 1 and R = 0. This will set the latch

and Qn+1 = 1 and Qn+1 bar = 0 irrespective of the present state.

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 JK((Jack Kilby) Flip Flops
◉ The JK flip flop is used to remove the drawback of the S-R flip flop i.e.,
undefined states. .
◉ The JK flip flop is formed by doing modification in the SR flip flop
◉ When S and R input is set to true, the SR flip flop gives an inaccurate result. But in the
case of JK flip flop, it gives the correct output.

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 T (Toggling) Flip-Flop
◉ T Flip-Flop is a slight modification of JK Flip-Flop.
◉ The T input to this Flip-Flop is sole input and is distributed to create a set of two
necessary inputs.
◉ This management disables the differing input combinations like [0,1] or [1,0] and only
"NO CHANGE" & "TOGGLE" outputs are evaluated.
◉ T flip-flop is the simplified version of JK flip-flop.
◉ It is obtained by connecting the same input ‘T’ to both inputs of JK flip-flop.
◉ It operates with only positive clock transitions or negative clock transitions.

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S.N Condition Operation
.

1 T = 0, J = K The output Q and Q bar won't change

=0

2 T = 1, J = K Output will toggle corresponding to every leading

=1 edge of clock signal.

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 Master Slave JK flip flop
◉ The Master-Slave Flip-Flop is basically a combination of two JK flip-flops
connected together in a series configuration.
◉ Out of these, one acts as the “master” and the other as a “slave”.
◉ The output from the master flip flop is connected to the two inputs of the
slave flip flop whose output is fed back to inputs of the master flip flop.
◉ In addition to these two flip-flops, the circuit also includes an inverter.
◉ The inverter is connected to clock pulse in such a way that the inverted
clock pulse is given to the slave flip-flop.
◉ In other words if CP=0 for a master flip-flop, then CP=1 for a slave flip-flop
and if CP=1 for master flip flop then it becomes 0 for slave flip flop.

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 Sequential Circuits
◉ A sequential circuit is an interconnection of flip-flops and gates.
◉ The gates by themselves constitute a combinational circuit, but when
included with the flip-flops, the overall circuit is classified as a sequential
circuit.

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◉ Sequential circuits are digital circuits that store and use the previous state information
to determine their next state.
◉ Unlike combinational circuits, which only depend on the current input values to produce
outputs,
◉ sequential circuits depend on both the current inputs and the previous state stored in
memory elements.
◉ A Sequential circuit is specified by
1. A time sequence of external inputs
2. External outputs
3. Internal flip flop binary states

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State table of Sequential Circuit:
◉ The behaviour of sequential circuit is determined from the inputs, the
outputs and the state of its flip flops
◉ A sequential circuit is specified by a state table that relates outputs and
next states s function of inputs and present states.

The Next state values are then

determined from the input equations
DA=Ax+Bx
DB=A’x
The output column is derived from the
output equation
Y=Ax’ + Bx’

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State Diagram:
◉ The information in a state table can be graphically represented in a state
diagram.
◉ In this type of diagram, a state represented by a circle, and the transition
between states indicated by directed lines connecting the circles.
◉ The state diagram of the sequential circuit given below.

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◉ The directed line from state 00 to 01 labelled 1/0.
◉ It means that when the sequential circuit is in the present state 00 and the input is 1, the output
is 0.
◉ After a clock transition, the circuit goes to the next state 01.
◉ The same clock transition may change the input value.
◉ If the input changes to 0, the output becomes 1.
◉ But if the input remains at 1, the output stays at 0.
◉ This information obtained from the state diagram along the two directed lines from the circle
representing state 01.

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Design of sequential circuit:
1. Translate the circuit specification into state diagram
2. Convert state diagram into state table
3. From state table derive the equations and draw the logic circuit
diagrams.

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