Logic families

Integration Technologies
Scheme #gates/chip
Small Scale Integration(SSI) <12
Medium Scale Integration(MSI) 12 - 99
Large Scale Integration(LSI) 1000
Very large Scale Integration(VLSI) 10k
Ultra large Scale Integration(ULSI) 100k
Giga Scale Integration (GSI) 1Meg
Digital Logic Family
➢Logic families can be classified broadly according to
the technologies they are built with
➢There are various logic families namely–
Diode logic(DL)
Resistor-Transistorlogic(RTL)
Diode-Transistor logic(DTL)
Emitter coupled logic(ECL)
Transistor-Transistorlogic(TTL)
CMOS logic
➢TTL and CMOS logic family is most widely used IC
technologies.
➢Within each family, several subfamilies of logic types
are available,with different rating for speed, power
consumption, temperature range, voltage level and
current level.
Nomenclature of Logic family
The prefix of the part number represents the manufacturer code
Prefix used for manufacturers:
S- Signetics
SN- Texas Instruments
DM- National Semiconductor
The suffix at the middle denotes the subfamily of the ICs and suffix
at the end denotes the packaging type.
Suffixusedforsubfamily:
74H04-High-speed 74L045-Low-Power
74S04-Usesa SchottkyDiode
74ALS04-AdvancedlowpowerSchottky
Suffixusedforpackaging:
N- Plastic dual inline package
W- Ceramic flat pack
D- Surface mounted plastic package
For example: If the part number is S74F08N. The 7408 is the basic number used by all manufacturer for
quad AND gate. The S prefix is the manufacture’s code for Signetics, F stands for FAST TTL subfamily,
and the N suffix at the end is used to specify the plastic dual in line packaging
Logic family classification
Voltage and current levels
Voltage and current levels
 Logic families: Voltage levels
VOH(min) – The minimum voltage level at an output in the logical
“1” state under defined load conditions
VOL(max) – The maximum voltage level at an output in the logical
“0” state under defined load conditions
VIH(min) – The minimum voltage required at an input to be
recognized as “1” logical state
VIL(max) – The maximum voltage required at an input that still will
be recognized as “0” logical state

VOH VIH VOL VIL

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 Logic families: Current requirements
IOH – Current flowing into an output in the logical “1” state under specified load
conditions
IOL – Current flowing into an output in the logical “0” state under specified load
conditions
IIH – Current flowing into an input when a specified HI level is applied to that
input
IIL – Current flowing into an input when a specified LO level is applied to that
input

IOH IIH IOL IIL

VOH VIH VOL VIL

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Fan-in: It determines the number of
inputs the logic gate can handle.

Fan-out: Determines the number of

circuits that a gate can drive.
 Logic families: fanout
Fanout: the maximum number of logic inputs (of the
same logic family) that an output can drive reliably

I I OL
DC fanout = min( OH , )
I IH I IL
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Noise Immunity: Maximum
noise that a circuit can
withstand without affecting
the output.
Noise margin
HI state noise margin:
VNH = VOH(min) – VIH(min)

LO state noise margin:

VNL = VIL(max) – VOL(max)

Noise margin:
VN = min(VNH,VNL)
 Speed

Speed of a logic circuit is determined by the time between the application of input and change in the output of the circuit.
Logic families: propagation delay
Logic families: propagation delay
Speed-power product: TPD Pavg
Standard voltage levels for different logic families
Diode logic OR gate
Diode logic AND gate
RTL logic NOT gate
Two input RTL NOR gate
Specifications of RTL
Two input DTL NAND gate
Specifications of DTL
Two input TTL NAND gate with Multiple emitter Transistor
Diode Equivalent of Q1
Two input TTL NAND gate with Totemploe output
Static analysis when output is HIGH
Static analysis when output is LOW
Q4 acting as current sink when output is low
Q4 acting as current Source when output is HIGH
When TTL Output HIGH
When TTL Output LOW
TTL VOLGATE LEVELS
TTL logic levels and noise margin
Standard TTL Specifications
2-input High speed NAND gate
2-input Low power NAND gate
Drawback of Totempole
Open collector output
Tristate TTL inverter
Input and out devices
Input and out devices
 Switching characteristics
MOSFET Type VGS ≪ 0 VGS = 0 VGS ≫ 0

N-channel OFF OFF ON

Enhancement

N-channel OFF ON ON
Depletion

P-channel ON OFF OFF

Enhancement

P-channel ON ON OFF
Depletion
CMOS NAND Gate
CMOS NAND Gate
CMOS NAND Gate
CMOS NAND Gate
CMOS NOR Gate
CMOS NOR Gate
CMOS NOR Gate
CMOS NOR Gate
 Emitter Coupled Logic(ECL)
PROS: Fastest logic family available (~1ns)
• CONS: low noise margin and high power
dissipation
• Operated in emitter coupled geometry (recall
differential amplifier or emitter-follower),
transistors are biased and operate near their Q-
point (never near saturation!)
• Logic levels
•Logic 0–>1.7V
•Logic 1 –> 0.8V
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Basic Emitter Coupled Logic(ECL) inverter
ECL OR/NOR Gate
 TTL
Overview
Logic TPD Trise/fall VIH,min VIL,max VOH,min VOL,max Noise
Family Margin

• Values typical for Vcc/Vdd = 5V

CMOS
• When interfacing different families, pay attention
to their input/output voltage, current (fanout) 79