Overview

 Last lecture
 End of combinational logic
 Very fast introduction to Verilog
 Today
 Sequential logic
 Latches

01/20/25 CSE 370 – Winter 2002 - Sequential Logic - 1

Why do we study sequential logic

 Why not only combinational logic?

 We can build complex circuits: adder, multiplier etc.
 But… real-world problems are sequential in time
 We want to build systems that step through computations
 These systems have memory and feedback
 They use sequence of inputs to transition from state to state

01/20/25 CSE 370 – Winter 2002 - Sequential Logic - 2

Recall: Combinational vs. sequential systems

 A simple model of a digital system is a unit with inputs and

outputs:

inputs system outputs

 Combinational systems are "memory-less"

 The outputs depend only on the present inputs
 Sequential systems have memory
 The output values depend on the input values and previous
input values outputs
inputs

01/20/25 CSE 370 – Winter 2002 - Sequential Logic - 3

Recall: The steady-state abstraction

 Combinational logic: Output depends on current inputs

 After sufficient time has elapsed
 Sequential logic: outputs retain their settled values
 even after waiting for the transient activity to finish
 Sequential logic relies on the steady-state abstraction:
 the memory of a system is its state
 changes in system state are only allowed to occur at specific
times most often controlled by an external periodic clock
 the clock period is the time that elapses between state
changes. It must be sufficiently long so that the system reaches
a steady-state before the next state change at the end of the
period

01/20/25 CSE 370 – Winter 2002 - Sequential Logic - 4

Overview: Sequential logic

 Assumes steady-state signals

 Has memory
 Usually employs feedback
 Is clocked (or self-timed)
 The basic devices and concepts
 Latches, flip-flops, shift registers, state machines
 Timing is critical
 Asynchronous inputs must be synchronized
 Metastability

01/20/25 CSE 370 – Winter 2002 - Sequential Logic - 5

Sequential circuits

 Circuits with feedback

 outputs = f(inputs, past inputs, past outputs)
 basis for building "memory" into logic circuits
 door combination lock is an example of a sequential circuit
 If there is an error the lock doesn't open
 Punch in 3 values in sequence and the door opens

new equal reset

value
C1 C2 C3
multiplexer mux comb. logic
control
comparator state clock

equal open/closed

01/20/25 CSE 370 – Winter 2002 - Sequential Logic - 6

Memory in sequential circuits

 Memory: Stored combination, present digit, errors or successes

in past inputs

new equal reset

value
C1 C2 C3
mux
multiplexer controller
control
comparator clock

equal open/closed

01/20/25 CSE 370 – Winter 2002 - Sequential Logic - 7

Feedback in sequential circuits

 Inputs: Sequence of number values, reset

 Outputs: Door open/close
 Feedback: Comparator output ("equal" signal)

new equal reset

value
C1 C2 C3
mux
multiplexer controller
control
comparator clock

equal open/closed

01/20/25 CSE 370 – Winter 2002 - Sequential Logic - 8

Clocking sequential circuits

 Inputs are synchronized by the clock

 Inputs are accepted when the clock signal goes high
 Controller is clocked
 Mux-control and open/closed signals change on the clock
edge

new equal reset

value
C1 C2 C3
mux
multiplexer controller
control
comparator clock

equal open/closed

01/20/25 CSE 370 – Winter 2002 - Sequential Logic - 9

What we will study

1) Tools and devices

 Feedback, memory, state diagrams, clocking, timing
 Latches, flip-flops, registers
2) Sequential circuit design
 Counters, shift registers
 The design process: From state diagrams to logic devices
 Finite state machines (FSMs)
3) Implementation details
 FSM optimization and state assignment
 Detailed design examples

01/20/25 CSE 370 – Winter 2002 - Sequential Logic - 10

Circuits with feedback

 How to control feedback?

 what stops values from cycling around endlessly

X1 Z1
X2 Z2
• switching •
• network •
• •
Xn Zn

01/20/25 CSE 370 – Winter 2002 - Sequential Logic - 11

Simplest circuits with feedback

 Two inverters form a static memory cell

 will hold value as long as it has power applied

"1"

"stored value"
"0"

 How to get a new value into the memory cell?

 selectively break feedback path
 load new value into cell

"remember"

"load" "stored value"

"data"

01/20/25 CSE 370 – Winter 2002 - Sequential Logic - 12

Memory with cross-coupled gates

 Cross-coupled NOR gates (allows info to be changed)

 similar to inverter pair, with capability to force output to 0 (reset=1) or
1 (set=1)

R Q
Q
R
S Q'
S
 Cross-coupled NAND gates
 similar to inverter pair, with capability to force output to 0 (reset=0) or
1 (set=0)

S' Q
Q
S'
R' Q'
R'

01/20/25 CSE 370 – Winter 2002 - Sequential Logic - 13

Timing behavior: the R-S latch

R Q

S Q'

Reset Hold Set Reset Set 100 Race

R
S
Q
\Q

01/20/25 CSE 370 – Winter 2002 - Sequential Logic - 14

State diagrams

 How do we characterize logic circuits?

 Combinational: Truth tables
 Sequential: State diagrams
Q Q' Q Q'
 Begin by drawing the states 0 1 1 0
 States  possible values for fed back
signals (Q, Q')
 Example: R-S latch state diagram
Q Q'
0 0

R Q

Q Q'
Q' 1 1
S

01/20/25 CSE 370 – Winter 2002 - Sequential Logic - 15

State diagrams (con’t)

 Now draw the state SR=10

transitions SR=00 SR=00
SR=01 SR=10
 Transitions  Q Q' SR=01 Q Q'
Changes in state due 0 1 1 0
to inputs SR=01 SR=10
 Example: R-S latch SR=11

Q Q'
R Q 0 0
SR=11 SR=11

SR=00
SR=00 SR=11
S Q' SR=01 SR=10

possible oscillation Q Q'

between states 00 and 11 1 1

01/20/25 CSE 370 – Winter 2002 - Sequential Logic - 16

Observed R-S latch behavior

 The 1-1 state is transitory

 one of R or S usually changes first
 Ambiguously returns to state 0-1 or 1-0
 a so-called "race condition“ or non-deterministic transition

SR=10
SR=00 SR=00
SR=01 SR=10
Q Q' SR=01 Q Q'
0 1 1 0
SR=01 SR=10
SR=11

Q Q'
SR=11 0 0 SR=11
SR=00 SR=00

01/20/25 CSE 370 – Winter 2002 - Sequential Logic - 17

R-S latch characteristic equation

 Break feedback path

R Q

S Q'

S R Q(t) Q(t+)
0 0 0 0 S
hold
0 0 1 1
0 0 X 1
0 1 0 0
reset
0 1 1 0 Q(t) 1 0 X 1
1 0 0 1
set R
1 0 1 1
1 1 0 X not allowed characteristic equation
1 1 1 X Q(t+) = S + R’ Q(t)

01/20/25 CSE 370 – Winter 2002 - Sequential Logic - 18

Gating an R-S latch

 Basic R-S latch is glitch sensitive

 Static 0-hazards can cause state changes
 Solution: Define when inputs can change
 Use an enable input

Basic R-S latch Gated R-S latch

R R' R
Q Q
 enable'

S Q' Q'
S' S

01/20/25 CSE 370 – Winter 2002 - Sequential Logic - 19

Gated R-S latch

 Control when R and S

inputs matter R' R
 State can only Q
change when enable'
enable’ is a logic 0 Q'
S' S

Set Reset
100

S'
R'
enable'
Q
Q'

01/20/25 CSE 370 – Winter 2002 - Sequential Logic - 20

Clocks

 Used to keep time

 wait long enough for inputs (R' and S') to settle
 then allow to have effect on value stored
 Clocks are regular periodic signals
 period (time between ticks)
 duty-cycle (time clock is high between ticks - expressed as % of
period)

duty cycle (in this case, 50%)

period

01/20/25 CSE 370 – Winter 2002 - Sequential Logic - 21

Using a clock as a gating signal

 Controlling an R-S latch with a clock

 can't let R and S change while clock is active (allowing R and S
to pass)
 only have half of clock period for signal changes to propagate
 signals must be stable for the other half of clock period

R' R
Q

clock'
Q'
S' S

stablechanging stable changing stable

R' and S'

clock

01/20/25 CSE 370 – Winter 2002 - Sequential Logic - 22