Unit-3

• Data Representation: Data types, Complements, Fixed Point

Representation, Floating Point Representation.

• Computer Arithmetic: Addition and subtraction, multiplication

Algorithms, Division Algorithms, Floating Point Arithmetic
operations. Decimal Arithmetic unit, Decimal Arithmetic operations.
Integer Data Types: Integers represent whole numbers (positive,
negative, or zero) without any fractional parts.

Different integer data types include:

• Signed Integers: Represent both positive and negative whole numbers
using a sign bit and magnitude.
• Unsigned Integers: Represent only non-negative whole numbers,
utilizing all bits for magnitude.
The floating number representation of a number has two part:
• The first part represents mantissa.
• The second part of designates the position of the decimal point and is
called the exponent: M x r e.
Fixed-Point Representation
There are three parts of a fixed-point number representation:
Sign field
 Integer field
Fractional field
The steps to convert binary to decimal are as follows:
• Step 1: Multiply each digit starting from the rightmost digit by the
powers of 2.
• Step 2: The sum of all these values obtained for each digit gives the
equivalent value of the given binary number in the decimal system.
 One's Complement

• In one's complement representation, the complement of a binary

number is found by flipping all the bits (changing 0s to 1s and 1s to
0s).
• One's complement arithmetic involves addition and subtraction using
one's complement representations.
• One of the drawbacks of one's complement representation is that there
are two representations for zero: a positive zero and a negative zero.
Two's Complement:

• Two's complement representation is the most common method for

representing signed integers in digital systems.
• To obtain the two's complement of a binary number, we first find the
one's complement and then add 1 to the least significant bit (LSB).
• Two's complement representation simplifies arithmetic operations,
especially addition and subtraction, as it eliminates the need to handle
two representations for zero.
The 9's complement representation is a system used to represent
negative numbers.
Find the 9's complement of each digit:452
• 9's complement of 4: 9 - 4 = 5
• 9's complement of 5: 9 - 5 = 4
• 9's complement of 2: 9 - 2 = 7
• Add 1 to the least significant digit:547 + 1 (carried over to the
rightmost digit) = 548
• Therefore, the 9's complement of the number 452 is 548.
In the decimal number system, the 10's complement representation is a
method used to represent both positive and negative numbers.
Find the 10's complement of each digit:786
• 10's complement of 7: 10 - 7 = 3
• 10's complement of 8: 10 - 8 = 2
• 10's complement of 6: 10 - 6 = 4
• Write down the obtained complements: 324
• Therefore, the 10's complement of the number 786 is 324.
Adder and Subtractor
XOR Gate
The two signs A, and B, are compared by an exclusive-OR gate.
 If the output of the gate is 0, the signs are identical
 If it is 1, the signs are different.
 For an add operation, identical signs dictate that the magnitudes be
added.
 For a subtraction operation, different signs dictate that the
magnitudes be added.
• The magnitudes are added EA ->A + B. where EA is a register that
combines E and A.
• The carry in E, after the addition constitutes an overflow if it is equal
to 1.
• The value of E is transferred into the add-overflow flip-flop AVF.
• 1 in E indicates that A>=B and the number in A is the correct result.
• 0 in E, the sign A, must be made positive to avoid a negative zero.
• 0 in E indicates that A < B.
• It is necessary to take the 2's complement of the value in A.
• when A < B, the sign of the result is the complement of the original
sign of A.
Multiplication
The hardware for multiplication
Initially, the multiplicand is in register B and the multiplier in Q.
The sum of A and B forms a partial product which is transferred to the
EA register.
 Both partial product and multiplier are shifted to the right.
This shift will be denoted by the statement shr EAQ
LSB of A is shifted into the most significant position of Q.

The bit from E is shifted into the most significant position of A, and 0
is shifted into E.

 After the shift, one bit of the partial product is shifted into Q, pushing
the multiplier bits one position to the right.
Initially, the multiplicand is in B and the multiplier in Q. Their
corresponding signs are in Bs, and Qs, respectively.
Registers A and E are cleared .
The sequence counter SC is set to a number equal to the number of
bits of the multiplier.
After the initialization, the low-order bit of the multiplier in Q, is
tested.
If Qn is a 1, the multiplicand in B is added to the present partial
product in A.
 Register EAQ is then shifted once to the right to form the new partial
product .
The sequence counter is decremented by 1
 If Qn is 0, nothing is done.
 Register EAQ is then shifted once to the right to form the new partial
product .
The sequence counter is decremented by 1 and its new value checked.
• The partial product formed in A if it is not equal to zero, the process is
repeated.
• The process stops when SC = 0.
• Shifted into Q one bit at a time and eventually replaces the multiplier.
• The final product is available in both A and Q
• A holding the most significant bits
• Q holding the least significant bits.
 Booth’s Multiplication Algorithm (signed-2’s complement)

• If the numbers are represented in signed 2’s complement then we

multiply them by using Booth algorithm.
• Booth’s Algorithm offers several benefits, including a reduced number
of arithmetic operations, decreased execution time, and optimized
hardware utilization.
• Initially AC and Qn+1 bit is cleared to zero
• SC is set to number n equal to number of bits in multiplier.
• The two bits of the multiplier in Qn and Qn+1 are inspected.
• If two bits are equal to 01, the multiplicand is added to partial product
in AC.
• If two bits are equal to 10, the multiplicand is subtracted from the
partial product in AC.
• When two bits are 00,11 equal, partial product does not change.
• The next step is to do arithmetic shift right the partial product in AC
and Multiplier in QR.
• The SC is decremented by one and the loop computation is repeated
for n times.
• Finally the result is available in AC and QR with 2’s complement
representation for negative numbers
1. The multiplicand is subtracted from the partial product when the
first least significant 1 in a string of 1's in the multiplier.

2. The multiplicand is added to the partial product when we get the first
Q (provided that there was a previous 1) in a string of 0's in the
multiplier.

3. The partial product does not change when the multiplier bit is the
same as the previous multiplier bit.
 Division Algorithms

When the dividend is twice as long as the divisor, we can understand

the condition for overflow as follows:
A divide-overflow occurs if the high-order half bits of the dividend
makes a number greater than or equal to the divisor.
The dividend is in A and Q and the divisor in B.
SC to specify the number of bits in the Divisor.
A divide-overflow condition is tested by subtracting the divisor in B
from half of the bits of the dividend stored in A.
If A >= B, the divide-overflow flip-flop DVF is set and the operation
is terminated prematurely.
If A < B, no divide overflow occurs so the value of the dividend is
restored by adding B to A.
Division Algorithms
1) The division of the magnitudes starts by shifting the dividend in AQ
to the left with the high-order bit shifted into E.
2) If E=1,0 ,Divisor B complement +1 is added to A.
3) If E = 1, it signifies that A >= B; therefore, Qn, is set to 1. Need to
decrement the SC by 1.
4) If E = 0, add B to A it signifies that A < B. In the latter case we
leave 0 in Qn. Need to decrement the SC by 1.
 Floating-point Arithmetic operations

Floating- point hardware is included in most computers.

• There are two part of a floating-point number in a computer - a
mantissa m and an exponent e.
• The two parts represent a number generated from multiplying m times
a radix r raised to the value of e.
• Thus M x re .
• For example, assume a fraction representation and a radix 10.
• The decimal number 537.25 is represented in a register with
• M= 53725 and
• e = 3 and is interpreted to represent the floating-point number .53725
x 103
• Three registers are there BR, AC, and QR.
• Each register is subdivided into two parts.
• The mantissa part has the same uppercase letter symbols as in fixed-
point representation.
• The exponent part may use corresponding lower-case letter symbol.
Note that the symbol AC represents the entire register, that is, the
concatenation of As, A and a.
In the similar way, register BR is subdivided into Bs, B, and b and QR
into Qs, Q and q.
A parallel-adder adds the two mantissas and loads the sum into A and
the carry into E.
 A separate parallel adder can be used for the exponents.
 Addition and Subtraction of Floating Point Numbers:
• During addition or subtraction, the two floating-point operands are
kept in AC and BR.
• The sum or difference is formed in the AC.
The algorithm can be divided into four consecutive parts:
1. Check for zeros.
2. Align the mantissas.
3. Add or subtract the mantissas
4. Normalize the result
1. Check for zeros at the beginning and terminate the process if
necessary.
2. If BR is equal to zero, the operation is terminated, with the value in
the AC being the result.
3. If AC is equal to zero, we transfer the content of BR into AC
4. Complement its sign if the numbers are to be subtracted.
5. If neither number is equal to zero, we proceed to align the
mantissas.
6. If the two exponents are equal, we go to perform the arithmetic
operation.
7. If the exponents are not equal, the mantissa having the smaller
exponent is shifted to the right and its exponent incremented.
8. This process is repeated until the two exponents are equal.
9. The magnitude part is added or subtracted depending on the signs of
the two mantissas.
10. If an overflow occurs when the magnitudes are added, it is
transferred into flip-flop E.
11. If E is equal to 1, the bit is transferred into A1 and all other bits of A
are shifted right.
12. The exponent must be incremented to maintain the correct number.
13. If the mantissa is zero, the entire floating-point number in the AC is
made zero
14. The mantissa has an underflow if the most significant bit in position
A1 is 0.
15. In that case, the mantissa is shifted left and the exponent
decremented.
16. The bit in A1 is checked again and the process is repeated until it is
equal to 1.
17. When A1 = 1, the mantissa is normalized and the operation is
completed.
 Multiplication of Floating Point Numbers

The procedure for multiplication is divided in to below things

1. Check for zeros.
2. Add the exponents.
3. Multiply the mantissas
4. Normalize the result
To avoid having to represent negative exponents a bias is added to the
true exponent.
Why Use Bias?

• Simplifying Comparison: By using a biased exponent, the

representation allows for easier comparison of floating-point numbers.
Since all stored exponent values are positive.

• Handling Negative Exponents: Without bias, representing negative

exponents directly could complicate the arithmetic and comparison
operations.
1. The two operands are checked to determine if they contain a zero.
2. If either operand is equal to zero, the product in the AC is set to
zero and the operation is terminated.
3. If neither of the operands is equal to zero, the process continues
with the exponent addition.
4. The exponent of the multiplier is in q then add exponents a and b.
5. Transfer the exponents from q to a
6. Add the two exponents, and transfer the sum into a.
7. Both exponents are biased by the addition of a constant.
8. The correct biased exponent for the product is obtained by subtracting
the bias number from the sum.
9. The multiplication of the mantissas is done product residing in A
and Q.
10. The product may have an underflow.
11. The most significant bit in A is checked. If it is a 1, the product is
already normalized.
12. If it is a 0, the mantissa in AQ is shifted left and the exponent
decremented.
 Division of Floating Point Numbers

The procedure for division is divided in to below things:

1. Check for zeros.

2. Subtract the exponents.
3. Divide the mantissas
4. Normalize the result
1. The two operands are checked for zero.
2. If the divisor is zero, it indicates an attempt to divide by zero, the
operation is terminated with an error message.
3. If the dividend in AC is zero, the quotient in QR is made zero and
the operation terminates
4. The Q register is cleared to 0.
5. The sequence counter SC is set to a number equal to the number of
bits in the Divisor.
6. The two fractions are compared by a subtraction test. The carry in E
determines their relative magnitude.
7. The dividend fraction is restored to its original value by adding the
divisor.
8. If A >= B, it is necessary to shift A once to the right and increment
the dividend exponent.
9. The divisor exponent is subtracted from the dividend exponent.
10. The bias is then added and the result transferred into q.
11. The mantissa quotient resides in Q and the remainder in A.
QUESTIONS
1. Exercise problems on conversion of one type of number(base) into another
number (other base).
2. Describe how to Perform Addition and Subtraction using Complements.
3. Describe how to Perform Arithmetic Addition and Subtraction on Floating
Point Numbers.
4. Express the Addition and Subtraction Hardware as well as Algorithm
(Flowchart) with example using computer.
5. Describe the Arithmetic Multiplication Hardware as well as Algorithm
(Flowchart) with example using computer.
6. Describe Booth Multiplication Algorithm (Flowchart) with example.
7. Describe the Arithmetic Division Hardware as well as Algorithm
(Flowchart) with example using computer.