VLSI Design

21EC504

Lavanya B L
[email protected]
Assistant Professor
NMAMIT, Nitte.
Course Learning Objectives:
This course will enable the students to
1. To know about VLSI Design flow.
2. Understand the concepts of physical design.
3. Analyse CMOS inverters and compute the delay in combinational circuits.
4. To know the principle of dynamic CMOS logic and to know the concepts of
CMOS testing.

Scheme of SEE Question Paper There will be 8 questions of 20 marks each in the
question paper divided into 3 Units as per the syllabus & contact hours and the
student will have to answer 5 full questions, selecting 2 full questions from Unit - I
& Unit – II and 1 full question from Unit – III
VLSI Design-21EC504
Course Outcomes: At the end of the course the student will be able to
1. Explain the VLSI design flow and construct logic circuits using CMOS logic.
2. Explain CMOS fabrication flow and MOSFET scaling; design stick diagram and area
optimised layout for the given combinational logic circuit.
3. Analyse the sources of power dissipation in CMOS inverter, analyse CMOS inverter DC
and transient response. Estimate the delay through logical cascade and optimize using
Logical Effort Technique.
4. Analyse pseudo-NMOS, CVSL logic families, lathes and flip-flops.
5. Explain the concept of dynamic logic circuits, explain the need for testing and testability
issues in VLSI Design.
TEXT BOOKS:
1. Neil H. E. Weste and David Money Harris, “CMOS VLSI Design- A Circuits and
Systems Perspective”, 4th Edition, Pearson Education India, 2011.
2. Sung-Mo Kang, Yosuf Leblebici, “CMOS Digital Integrated Circuits: Analysis and
Design”, Third Edition, Tata McGraw-Hill, 2003.

REFERENCE BOOKS:
1. Neil H. E. Weste and Kamaran Eshraghian, “Principles of CMOS VLSI Design”,
Addison-Wesley, 2nd Edition, 2004.
2. John P. Uyemura, “Introduction to VLSI Circuits and Systems”, Wiley, 2002.
NPTEL/

MOOC Link:
1. https://nptel.ac.in/courses/122106025/2
2. https://nptel.ac.in/courses/117106091
****
Introduction to VLSI Design-21EC504
UNIT -1

Lavanya B L
[email protected]
Assistant Professor
NMAMIT,Nitte
6
 Introduction
• Very-large-scale integration (VLSI) is the process of
creating an IC by combining thousands
of transistors into a single chip.
• VLSI began in the 1970s when complex
semiconductor and communication technologies were
being developed. The microprocessor is a VLSI device.
• An electronic circuit might consist of
a CPU, ROM, RAM and other glue logic. VLSI lets IC
makers add all of these into one chip.
• By the 1980's, very large scale integration (VLSI)
squeezed hundreds of thousands of components onto a
chip. the size and price of computers.
• It also increased their power, efficiency and reliability.
• The microprocessor is the characteristic of fourth
generation computers, capable of performing all of the
functions of a computer's central processing unit. 7
 Integrated Circuits

Why Make IC’s ?

 Integration improves
 size
 speed
 power
 Integration reduce manufacturing costs
 (almost) no manual assembly

8
 Scale of Integration
  Small scale integration(SSI) --1960 The technology was developed by
integrating the number of transistors of 1-100 on a single chip. Ex: Gates,
flip-flops, op-amps.
  Medium scale integration(MSI) --1967 The technology was developed by
integrating the number of transistors of 100- 1000 on a single chip. Ex:
Counters, MUX, adders, 4-bit microprocessors.
  Large scale integration(LSI) --1972 The technology was developed by
integrating the number of transistors of 1000- 10000 on a single chip. Ex:8-
bit microprocessors,ROM,RAM.
  Very large scale integration(VLSI) -1978 The technology was developed
by integrating the number of transistors of 10000- 1Million on a single chip.
Ex:16-32 bit microprocessors, peripherals, complimentary high MOS.
  Ultra large scale integration(ULSI) The technology was developed by
integrating the number of transistors of 1Million 10 Millions on a single chip.
Ex: special purpose processors.
  Giant scale integration(GSI) The technology was developed by integrating
the number of transistors of above 10 Millions on a single chip. Ex:
Embedded system, system on chip.

9
 Chips
Integrated circuits consist of:
 A small square or rectangular “die”, < 1mm thick
 Small die: 1.5 mm x 1.5 mm => 2.25 mm2
 Large die: 15 mm x 15 mm => 225 mm2
 Larger die sizes mean:
 More logic, memory
 Less volume
 Less yield
 Dies are made from silicon (substrate)
 Substrate provides mechanical support and electrical
common point

10
11
• I N 1 9 4 7 , J O H N B A R D E E N A N D WA LT E R B RAT TA I N B U I LT T H E F I R S T
F U N C T I O N I N G P O I N T C O N TA C T T RA N S I S T O R AT B E L L L A B O RAT O R I E S ,
SHOWN IN FIGURE 1.2(A)
• F I G U R E 1 . 2 ( B ) S H O W S H I S F I R S T P R O T O T Y P E O F A N I N T E G RAT E D
C I RC U I T , C O N S T R U C T E D F R O M A G E R M A N I U M S L I C E A N D G O L D
WIRES.
12
 History
 1958: First integrated circuit
 Flip-flop using two transistors
 Built by Jack Kilby (Nobel Laureate) at Texas Instruments
 Robert Noyce (Fairchild) is also considered as a co-inventor

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Different IC’s

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15
 History and Evolution
 In 1947, John Bardeen and Walter Brattain built the first functioning point contact
transistor at Bell Laboratories and Ten years later, Jack Kilby at Texas Instruments realized
the potential for miniaturization if multiple transistors could be built on one piece of
silicon. [Figure1.2]
 The invention of the transistor earned the Nobel Prize in Physics in 1956 for Bardeen,
Brattain, and their supervisor William Shockley.
 Kilby received the Nobel Prize in Physics in 2000 for the invention of the integrated circuit.
 Transistors can be viewed as electrically controlled switches with a control terminal and
two other terminals that are connected or disconnected depending on the voltage or
current applied to the control.
 Soon after inventing the point contact transistor, Bell Labs developed the bipolar junction
transistor.
 Bipolar transistors were more reliable, less noisy, and more power-efficient. Early
integrated circuits primarily used bipolar transistors. Bipolar transistors require a small
current into the control (base) terminal to switch much larger currents between the other
two (emitter and collector) terminals.
 The quiescent power dissipated by these base currents, drawn even when the circuit is
not switching, limits the maximum number of transistors that can be integrated onto a
single die.
Prepared by: Lavanya B L,Assistant Professor, NMAMIT,Nitte
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 History and Evolution
 In 1958, Jack Kilby built the first integrated circuit flip-flop with two
transistors at Texas Instruments.
 In 1976, Steve Jobs and Steve Wozniak built the Apple II, the first personal
computer in a garage in California.
 Then, in 1981, IBM introduced its first personal computer. 1982, "Time"
magazine dedicated its annual "Man of the Year Issue" to the computer. The
other feature of the microprocessor is its versatility.
 Whereas previously the integrated circuit had had to be manufactured to fit
a special purpose, now one microprocessor could be manufactured and then
programmed to meet any number of demands.
 Soon everyday household items such as microwave ovens, television sets
and automobiles with electronic fuel injection incorporated
microprocessors.
 The 1980's saw an expansion in computer use in all three arenas as clones of
the IBM PC made the personal computer even more affordable. The number
of personal computers in use more than doubled from 2 million in 1981 to
5.5 million in 1982.
Prepared by: Lavanya B L,Assistant Professor, NMAMIT,Nitte
17
 History and Evolution
 By the 1960s, Metal Oxide Semiconductor Field Effect Transistors
(MOSFETs) began to enter production.
 MOSFETs offer the compelling advantage that they draw almost zero
control current while idle.
 They come in two flavors: nMOS and pMOS, using n-type and p-type
silicon, respectively.
 The original idea of field effect transistors dated back to the German
scientist Julius Lilienfield in 1925
 In 1963, Frank Wanlass at Fairchild described the first logic gates using
MOSFETs.
 Fairchild’s gates used both nMOS and pMOS transistors, earning the
name Complementary Metal Oxide Semiconductor, or CMOS.
 The circuits used discrete transistors but consumed only nano-watts
of power, six orders of magnitude less than their bipolar counterparts.
Prepared by: Lavanya B L,Assistant Professor, NMAMIT,Nitte
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 History and Evolution
 First Planer IC built in 1961
 2003
 Intel Pentium 4 processor (55 million transistors)
 512 Mbit DRAM (> 0.5 billion transistors)
 53% compound annual growth rate over 45 years
 No other technology has grown so fast so long
 Driven by miniaturization of transistors
 Smaller is cheaper, faster, lower in power!
 Revolutionary effects on society
 In 2008, Intel’s Itanium microprocessor contained more than 2 billion
transistors and a 16 Gb Flash memory contained more than 4 billion
transistors.
 This corresponds to a compound annual growth rate of 53% over 50
years. No other technology in history has sustained such a high
growth rate lasting for so long.

Prepared by: Lavanya B L,Assistant Professor, NMAMIT,Nitte

19
 A Brief History
As more and more complex functions are required in various data
processing and telecommunications devices, the need to integrate
these functions in a small package is also increasing. The level of
integration as measured by the number of logic gates in a monolithic
chip has been steadily rising for almost three decades, mainly due to
the rapid progress in processing technology and interconnect
technology . Thus, VLSI Design came into existence.

Avantages of VLSI :-
 Less area/volume and therefore, compactness
 Less power consumption
 Less testing requirements at system level
 Higher reliability, mainly due to improved on-chip interconnects
 Higher speed, due to significantly reduced interconnection length
 Significant cost savings
Prepared by: Lavanya B L,Assistant Professor, NMAMIT,Nitte
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21
 Scaling
 The only constant in VLSI is constant
change
 Feature size shrinks by 30% every 2-3 years
 Transistors become cheaper
 Transistors become faster and lower power
 Wires do not improve
(and may get worse)
 Scale factor S
 Typically
 Technology nodes
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 A Brief History
 When comparing the integration density of integrated circuits, a clear distinction
must be made between the memory chips and logic chips. Figure below shows the
level of integration over time for memory and logic chips, starting in 1970.

Prepared by: Lavanya B L,Assistant Professor, NMAMIT,Nitte

23
 Moore’s Law
• Gordon Moore: co-founder of Intel
• Predicted that the number of transistors per chip
would grow exponentially (double every 18
months)
• Exponential improvement in technology is a
natural trend:
• e.g. Steam Engines - Dynamo – Automobile
• Moore’s Law is driven primarily by scaling down
the size of transistors and, to a minor extent, by
building larger chips.

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 A Brief History
• Digital CMOS (Complementary Metal Oxide Semiconductor) integrated circuits
(ICs) have been the driving 'force behind Very Large Scale Integration (VLSI) for
high performance computing and other scientific and engineering applications.
• The demand for digital CMOS ICs will be continually strong due to salient
features such as low power, reliable performance, circuit techniques for high
speed such as using dynamic circuits, and ongoing improvements in processing
technology.
• The minimum feature size in CMOS ICs can decrease to 0.1 μm within a few
years.
• With such a technology, the level of integration in a single chip can be on the
order of several hundreds of millions of transistors for logic chips or even higher
in the case of memory chips, which presents an immense challenge for chip
developers in processing, design methodology, testing, and project management.

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 Classification of CMOS digital circuit types

• Fig. shows a simple "family tree" for digital

integrated circuits that clarifies the
classification and relations among different
types of circuits.
• Based on the fundamental operating
principles, the circuits are classified into
two main categories, i.e., static circuits and
dynamic circuits.
• The static CMOS circuits are further
divided into sub-categories such as classical
(fully complementary) CMOS circuits,
transmission-gate logic circuits, pass-
transistor logic circuits and cascade voltage
switch logic (CVSL) circuits.
• The dynamic CMOS circuits are divided
into sub-categories such as domino logic,
NORA, and true single-phase clock (TSPC)
circuits

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The Flow of Circuit Design Procedure

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 The Flow of Circuit Design Procedure
• The logic circuit is first translated into a CMOS circuit and the initial layout
is done.
• From the layout, all of the important parasitics are calculated by using a
circuit extraction program.
• Once a full circuit description is obtained from the initial layout, we analyze
the circuit for DC and transient performance by using the circuit-level
simulation program, SPICE, and then compare the results with the given
design specifications.
• If the initial design fails to meet any one of the specifications, which is the
case in this exercise, we devise an improved circuit design to meet the
design objective.
• Then the improved design will be implemented into a new layout and the
design-analysis cycle will be repeated until all of the design specifications
are met.
• The simplified flow of this circuit design procedure is illustrated in Fig.
• Note that the topics covered in this textbook concern primarily the two
important steps enclosed in the dotted box, namely, VLSI design and
design verification.

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 Overview of VLSI design methodology
1. Full Custom Design :-
 Using the full-custom design style (where the geometry and the placement of
every transistor can be optimized individually) requires a longer time until design
maturity can be reached,
 yet the inherent flexibility of adjusting almost every aspect of circuit design allows
far more opportunity for circuit performance improvement during the design
cycle.
 The final product typically has a high level of performance (e.g. high processing
speed, low power dissipation) and the silicon area is relatively small because of
better area utilization. But this comes at a larger cost in terms of design time.

2. Semi custom Design :-

 Using a semi-custom design style (such as standard-cell based design or FPGA)
will allow a shorter design time until design maturity can be achieved.
 In the early design phase, the circuit performance can be even higher than that of
a full-custom design, since some of the components used in semi-custom design
are already optimized.
 But the semi-custom design style offers less opportunity for performance
improvement over the long run, and the overall performance of the final product
will inevitably be less than that of a full-custom design.
29
 Overview of VLSI design methodology
 This above facts are illustrated qualitatively in Figue below where two different VLSI
design styles are compared for their relative merits in the design of the same product.
 The choice of the particular design style for a VLSI product depends on the
performance requirements, the technology being used, the expected lifetime of the
product and the cost of the project. In the following sections, we will discuss the
various aspects of different VLSI design styles and consider their impact upon circuit
performance and overall cost.

Figure : Impact of different VLSI design

styles upon the design cycle time and the
achievable circuit performance

30
 VLSI Design flow
• The Y-chart (first introduced
by D. Gajski) shown in
Figure illustrates a design
flow for most logic chips,
using design activities on
three different axes
(domains) which resemble
the letter "Y.“
• The Y-chart consists of three
domains of representation,
namely
(i) behavioral domain
(ii) structural domain
(iii)geometrical layout domain

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 VLSI Design flow
• The design process, at various levels, is usually evolutionary in nature. It starts
with a given set of requirements.
• Initial design is developed and tested against the requirements. When
requirements are not met, the design has to be improved. If such improvement is
either not possible or too costly, then a revision of requirements and an impact
analysis must be considered.
• The design flow starts from the algorithm that describes the behavior of the target chip.
The corresponding architecture of the processor is first defined. It is mapped onto the
chip surface by floorplanning. The next design evolution in the behavioral domain
defines finite state machines (FSMs) which are structurally implemented with functional
modules such as registers and arithmetic logic units (ALUs). These modules are then
geometrically placed onto the chip surface using CAD tools for automatic module
placement followed by routing, with a goal of minimizing the interconnects area and
signal delays. The third evolution starts with a behavioral module description. Individual
modules are then implemented with leaf cells. At this stage the chip is described in
terms of logic gates (leaf cells), which can be placed and interconnected by using a cell
placement and routing program. The last evolution involves a detailed Boolean
description of leaf cells followed by a transistor level implementation of leaf cells and
mask generation. In the standardcell based design style, leaf cells are pre-designed (at
the transistor level) and stored in a library for logic implementation, effectively
eliminating the need for the transistor level design.
32
 Design Hierarchy
• The use of the hierarchy, or "divide and conquer" technique
• It involves dividing a module into sub-modules and then repeating this operation on the sub-
modules until the complexity of the smaller parts becomes manageable.
• This approach is very similar to software development wherein large programs are split into
smaller and smaller sections until simple subroutines, with well-defined functions and
interfaces, can be written.
• We know that the design of a VLSI chip can be represented in three domains.
Correspondingly, a hierarchy structure can be described in each domain separately.
• However, it is important for the simplicity of design that the hierarchies in different domains
be mapped into each other easily
• In the physical domain, partitioning a complex system into its various functional blocks will
provide a valuable guide for the actual realization of these blocks on the chip.
• Figure 2 shows the hierarchical decomposition of the four-bit adder in physical description
(geometrical layout) domain, resulting in a simple floorplan.
• This physical view describes the external geometry of the adder, the locations of input and
output pins, and the pin locations that allow some signals (in this case the carry signals) to
be transferred from one sub-block to the other without external routing.
• At lower levels of the physical hierarchy, the internal mask layout of each adder cell defines
the locations and the connections of each transistor and wire.

33
Design Hierarchy

34
Design Hierarchy

35
Regularity :-
• Regularity means that the hierarchical decomposition of a large system should result
in not only simple, but also similar blocks, as much as possible.
• A good example of regularity is the design of array structures consisting of identical
cells - such as a parallel multiplication array. Regularity can exist at all levels of
abstraction.
• For example, at the transistor level, uniformly sized transistors simplify the design
and at the logic level, identical gate structures can be used.

36
Regularity :-
• Figure 1 shows regular circuit-level designs of a 2-1 MUX (multiplexer) and a D-type
edge-triggered flip flop.
• Note that both of these circuits were designed by using inverters and tri-state buffers
only.
• If the designer has a small library of well-characterized basic building blocks, a
number of different functions can be constructed by using this principle.
• Regularity usually reduces the number of different modules that need to be
designed and verified, at all levels of abstraction.

37
Modularity
• Modularity in design means that the various functional blocks which make up the
larger system must have well-defined functions and interfaces.
• Modularity allows that each block or module can be designed relatively
independently from each other, since there is no ambiguity about the function and
the signal interface of these blocks.
• All of the blocks can be combined with ease at the end of the design process, to
form the large system.
• The concept of modularity enables the parallelization of the design process. The
well-defined functionality and signal interface also allow the use of generic modules
in various designs.
Locality
• By defining well-characterized interfaces for each module in the system, we
effectively ensure that the internals of each module become unimportant to the
exterior modules.
• Internal details remain at the local level.
• The concept of locality also ensures that connections are mostly between
neighboring modules, avoiding long-distance connections as much as possible.
• This last point is extremely important for avoiding long interconnect delays.
• Time-critical operations should be performed locally, without the need to access
distant modules or signals. If necessary, the replication of some logic may solve this
problem in large system architectures.

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VLSI Chip Types/ VLSI Design Styles
 Full-custom Design:
where every circuit is custom designed for Project
 Extremely tedious
 Time-consuming process
 Semi-custom Design:
Using a group of primitive predefined cells as building blocks, called
cell library (Standard cell based Design)
 Programmable Logic Devices
–– Field Programmable Gate Array (FPGA)
–– Gate Array Design

39
 VLSI Chip Types/ VLSI Design Styles
(1) Full Custom Design
• In this design, the designer starts from scratch. This means that the designer
abandons the approach of pre-designed and pre-tested and pre-characterized cells
for all or part of the design.
• This might be because existing cell libraries are not fast enough, or the logic cells are
not small enough or consume too much power.
• You may need to use full-custom design if the ASIC technology is new or so
specialized that there are no existing cell libraries or because the ASIC is so
specialized that some circuits must be custom designed.
• Fewer and fewer full-custom ICs are being designed because of the problems with
these special parts of the ASIC.
• As a designer, you can optimize your design for speed, power, and area
requirements.
• The full custom design approach needs more time and the cost of prototyping is
higher compared to other design styles.

40
 VLSI Chip Types/ VLSI Design Styles
(1) Full Custom Design

41
 VLSI Chip Types/ VLSI Design Styles
(1) Full Custom Design

42
 VLSI Chip Types/ VLSI Design Styles
(2)Semi Custom Design

43
(2)Semi Custom Design
• In a standard cell-based design approach, the
Standard
designer Cell-Based
uses pre-designed Design
logic cells such as
gates (AND, OR, NOR, NAND, etc.),
multiplexers, flip flops, etc., and they are
commonly known as standard cells.
• Those pre-designed and tested cells are stored
in a library.
• Different cells with different speed grades,
power, and area requirements are also
available.
• The chip designer only defines the placement
and interconnections between different cells.
• By using standard cells, a designer can save
time, and risk of failure by using a pre-
designed tested, and characterized cell library.
• The disadvantage of this type of design
approach is the expense of purchasing the cell
library.
• Also, it may take time to interconnect all
layers.
• The average manufacturing lead time is six to
44
 VLSI Chip Types/ VLSI Design Styles
(2)Semi Custom Design

45
 VLSI Chip Types/ VLSI Design Styles
(2)Semi Custom Design

46
 VLSI Chip Types/ VLSI Design Styles
(3) Programmable Logic Devices
3.1 Gate Array-Based Design
• In this design style, the transistors are predefined on a silicon wafer.
These are called base arrays or base cells.
• Only the top few layers of metal which are used to make
interconnections are customized. The designer chooses a pre-verified
gate array library of logic cells.
• These are termed “macros“. The designer needs to define the
interconnections between the base array.
• Depending upon the configuration of base cells, there are three different
types
(i) channel-less (ii) Channelled, and Since only metal
(iii) Structured interconnections
gate array. are
unique for Mased Gatted Array(MGA), we
can use prefabricated wafers (with
completed transistor layers)
• the turnaround time is reduced to a few
days or at most a couple of weeks
• the costs for all the initial prefabrication
steps for MGA are shared for each
consumer
=> the cost of an MGA is reduced
compared to FC and CBIC
47
 VLSI Chip Types/ VLSI Design Styles
(3) Programmable Logic Devices
3.1 Gate Array-Based Design
Gate array design
• Uncommitted transistors separated by routing
channels
• Circuit implementation: 2 step manufacturing
process
• 1st phase: generic masks for uncommitted
transistors on each Gate Array chip (stored)
• 2nd phase: Customization by (multiple) metal
fabrication process
• Ranks second after FPGA with a turn-around
time of a few days
• Chip utilization factor is higher than that of the
FPGA

48
 VLSI Chip Types/ VLSI Design Styles
(3) Programmable Logic Devices
3.2 Field Programmable Gate Array (FPGA)
• Logic gates with programmable interconnects
• I/O buffers, configurable logic blocks (CLBs) and
programmable interconnect structures
• Requires no process steps for logic realization
• For fast prototyping and small-volume ASIC
production (short turn-around time)

Design flow of FPGA:

• Behavioral description of its functionality .
• Technology-mapped into circuits or logic cells
• Assigns logic cells to FPGA CLBs and
determines the routing pattern

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 VLSI Chip Types/ VLSI Design Styles
(3) Programmable Logic Devices
3.2 FPGA
• a step above the PLD in complexity;
it is usually larger and more complex than a PLD
• rapidly growing in importance
• Pre-manufactured components with programmable
interconnect
• CAD tools greatly reduce design effort
• Low Design Cost / Low NRE Cost / High Unit Cost
• Lower Performance

•Characteristics
• none of mask layers are customized
• a method for programming basic cells and the interconnect
• the core is regular array of programmable basic logic cells (combinational + sequential)
• a matrix of programmable interconnect that surrounds the basic cells
• programmable I/O cells around the core
• design turnaround is a few hours

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VLSI Applications
 VLSI is an implementation technology for electronic circuitry -
analogue or digital
 It is concerned with forming a pattern of interconnected switches and
gates on the surface of a crystal of semiconductor
 Microprocessors
 personal computers
 microcontrollers
 Memory - DRAM / SRAM
 Special Purpose Processors - ASICS (CD players, DSP applications)
 Optical Switches
 Has made highly sophisticated control systems mass-producable and
therefore cheap

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Advantages of CMOS Technology
• CMOS technology devices are used in a variety of
applications with analog circuits such as data
converters, image sensors, etc.

The benefits of CMOS technology over NMOS

technology include the following.
• Static power consumption is very slow.
• The complexity of the circuit reduces
• The high density of logic functions on a chip
• Static power consumption is very low
• High noise immunity

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