DAYANANDA SAGAR UNIVERSITY

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

DIGITAL LOGIC DESIGN

UNIT-1
INTRODUCTION TO VERILOG
Chapter Outline

Arithmetic Circuits and Verilog Modelling

Introduction to Verilog: Syntax of Verilog coding, Modelling styles in

Verilog, Verilog Operators, Test bench for simulation

(Text Book-3: Chapter 1: 1.1, 1.2.2, 1.3.1, 1.3.2, 1.3.3, 1.4.2, 1.5.1.2, 1.5.2.2, 1.5.3.2,
1.5.4.2, 1.6.2)

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 Introduction to HDL (Hardware Description
Language)

Why HDL?

• In software everything is sequential

• Sequence of statements is significant, since they are

executed that order

• In hardware events are concurrent, so a software language

be used for describing and simulating hardware.

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e.g. C = (not (X) and Y) or (not (X))

Case 1
A = not X
B = A and Y
C = A or B
Result: C = 1
Case 2
B = A and Y
C = A or B
A = not X
Result: C = 0
Case 3
C = A or B
A = not X
B = A and Y
Result: C = 0
Different outputs with software programming languages
with ‘0’ initial values
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Features of HDLs

• Concurrent Descriptions
• Synchronizing mechanisms between concurrent
flows
• Event Scheduling
• Special object types and data types
• Hierarchy

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Advantages of using Hardware Description Languages
• Designs can be described at various levels of abstractions
• Top-Down Approach and hierarchical designs for large projects
•Functional Simulation Early in the Design Flow
• Automatic Conversion of HDL Code to Gates
• Early Testing of Various Design Implementations
Due to fast synthesis, there is a scope for trying different implementations

• Design Reuse
Technology independence, standardization, portability, ease of maintenance

All these result in low risk, high convergence, fast

time to market
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 About Verilog

•Hardware Description Language based on software language C

•Developed by Gateway Design Automation
•Made public by Candence in 1990
•In 1995 became IEEE Standard
•Presently maintained by OVI

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Application Areas of Verilog

System Suitable for all levels

SystemSpecification
Specification
Behavioral level
Not suitable
HW/SW
HW/SW
Partition
Partition
Hardware
Hardware Softwre
Softwre
Spec
Spec Spec
Spec
ASIC
ASIC
FPGA
FPGA Boards
Boards
&& Software
Software
PLD
PLD Systems
Systems
Std
StdParts
Parts
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Features of Verilog
Verilog is:
• A hardware design language (HDL)
Case Sensitive
• Tool for specifying hardware circuits
• Syntactically, a lot like C or Java
• An alternative to VHDL (and more widely used)
Syntax of Verilog
• Declaration & Body

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 Data Types in Verilog

• Basic type: bit vector

Values: 0, 1, X (don't care), Z (high impedence)

• Bit vectors expressed in multiple ways:

binary: 4'b11_10 ( _ is just for readability)
hex: 16'h034f
decimal: 32'd270
other formats but these are the most useful
Array declaration
Represent buses
wire [3:0] busA;
reg [1:4] busB;
reg [1:0] busC;
Left number is MS bit
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 Net type
• Connect things together with: wire
Single wire:
wire Y; // declaration
wire my_wire;
assign Y = A & B;
“Array” of wires
wire[7:0] my_wire;
Register type
• For procedural assignments, we'll use reg
Again, can either have a single reg or an array
reg[3:0] accum; // 4 bit “reg”
reg is not necessarily a hardware register
reg A, C; // declaration
// assignments are always done inside a procedure
A = 1;
C = A; // C gets the logical value 1
A = 0; // C is still 1
C = 0; // C is now 0
Parameter type
•Represent global constant
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 Verilog Operators

Logical Operators

• &&  logical AND

• ||  logical OR
• !  logical NOT
• Operands evaluated to ONE bit value: 0, 1 or x
• Result is ONE bit value: 0, 1 or x
A = 6; A && B  1 && 0  0
B = 0; A || !B  1 || 1  1
C = x; C || B  x || 0  x but
butC&&B=0
C&&B=0

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Bitwise Operators (i)

•&  bitwise AND

•|  bitwise OR
•~  bitwise NOT
•^  bitwise XOR
• ~^ or ^~  bitwise XNOR

• Operation on bit by bit basis

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Bitwise Operators (ii)

c = ~a; c = a & b;

• a = 4’b1010;
b = 4’b1100;

c = a ^ b;

• a = 4’b1010;
b = 2’b11;

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Reduction Operators

•&  AND
•|  OR
•^  XOR
• ~&  NAND
• ~|  NOR
• ~^ or ^~  XNOR

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Shift Operators

• >>  shift right

• <<  shift left

• Result is same size as first operand, always zero filled

a = 4’b1010;
...
d = a >> 2; // d = 0010
c = a << 1; // c = 0100

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 LEVELS OF ABSTRACTION
•Structural Level
Lower level
Has all the details in it (which gates to use, etc)
Is always synthesizable Behavioral Behavioral
•Functional Level RTL
RTL Our focus
Higher Level
Easier to write Gate
Gate
Gate level, RTL level, behavioral Layout (VLSI)
Layout (VLSI)
Not always synthesizable

We’ll be sticking with functional mostly

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 MODELLING STYLES

Data Flow level

• In this style of modeling the flow of data is expressed using concurrent
signal assignment statements.
• Expressed using boolean equations.

Structural level
• In this style of modeling the module is described as a set of
interconnected statements.
• Architecture/module includes the instantiation of blocks

Behavioral level
• This style of modeling specifies the behavior of an module as a set of
statements that are executed sequentially in the specified order.
• The architecture/module includes the predefined word always.

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DIGITAL LOGIC DESIGN
 Data Flow Modeling
•A Dataflow model specifies the functionality of the entity
without explicitly specifying its structure.
•This functionality shows the flow of information through the
assign statement, which is expressed primarily using
concurrent signal.

•The primary mechanism for modeling the dataflow behavior

of an entity is using the boolean equations defining the
required operations.
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 A 1 bit full adder
(Mode of the port which
specifies Direction of flow
module FA( input a, b, cin, are defined in the module. It
output s, cout); can be input, output or
inout)
assign s = a ^ b ^ c;
assign cout = (a & b) | (a & cin) | (b & cin);
Endmodule

*** Note:
red means new concept (keywords)

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 Behavioural Modeling
• The behavior of the module is expressed using sequentially
executed, procedural code, which is very similar in syntax and
semantics to that of a high level programming languages such as C
or Pascal.
• always statement is the primary mechanism used to model the
behavior of a module.
• always statement has a declarative part (before the keyword
begin) and a statement part (between the keywords begin and
end).
• The statements appearing within the statement part are
sequential statements and are executed sequentially.
• May not be synthesizable or may lead to a very large circuit
• Primarily used for simulation
21

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 SEQUENTIAL PROCESSING (always)
• always defines the sequential behavior of module or some
portion of the design.

• always is synchronized with the other concurrent statements

using the sensitivity list or wait statement.

• Statements, which describe the behavior in a always, are

executed sequentially.

• All processes in an architecture behave concurrently.

• Simulator takes Zero simulation time to execute all

statements in a always.

• always repeats forever, unless suspended.

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• Process can be in waiting or executing.
• Once the process has started it takes time delta ‘t’ for it to be
moved back to waiting state.
• This means that no simulation time is taken to execute the
process.

syntax:
always (sensitivity
list)
<declarations>
begin
<sequential
statements>;
end;

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Example:
A
S
With if statements B
C
always(clk,reset)
begin half adder
if reset=‘1’ module half_adder(S,
Z=‘0’; C, A, B);
output S, C;
elsif clk = ‘1’ input A, B;
Z=(i1 and i2) and i3;
reg S,C;
end if; wire A, B;
end;
always @(A or B) begin
S = A ^ B;
C = A && B;
end

endmodule
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 Structural Modeling
• A module is modeled as a set of modules connected by
signals.

• The behavior of the module is not explicitly apparent from its

model.

• The instantiation statement is the primary mechanism used

for describing such a model .

• A component instantiated in a structural description must

first be declared using a component declaration.

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 Hierarchical
Design

Top
TopLevel
Level E.g.
Module
Module

Full
FullAdder
Adder
Sub-Module
Sub-Module Sub-Module
Sub-Module
11 22

Half
HalfAdder
Adder Half
HalfAdder
Adder
Basic
BasicModule
Module Basic
BasicModule
Module Basic
BasicModule
Module
11 22 33

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 HIERARCHICAL DESIGNS

• A larger design entity can call a smaller design unit in it.

• This forms a hierarchical structure.
• This is allowed by a feature of verilog called instantiation.
• A component is a design module in itself which is instantiated in
the larger module.
• signals must be declared in the declarative part of the
architecture.

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 Verilog code Example 1: (Ripple Carry Adder)

module adder4(A, B, cin, S, cout);

input[3:0] A, B;
input cin;
output[3:0] S;
output cout;
wire c1, c2, c3;

// 4 instantiated 1-bit Full Adders

FullAdder fa0(A[0], B[0], cin, c1, S[0]);

FullAdder fa1(A[1], B[1], c1, c2, S[1]);
FullAdder fa2(A[2], B[2], c2, c3, S[2]);
FullAdder fa3(A[3], B[3], c3, cout, S[3]);
endmodule

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 Simulation & Synthesis
• Hardware description has to be simulated & tested.

• Hardware description has to be synthesized onto an electronic

chip.

Steps for simulation & synthesis

1. Choose Language for describing system (VHDL/ Verilog/mixed

language)
2. Choose the style of description, write code .
3. Compile using the compiler.
4. Assign data & run simulation.
5. Synthesize using synthesizer.
6. Check schematic & net list.
7. Download net list onto FPGA chip.
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 Testing Your Modules
module top_test;
wire [1:0] t_out; // Top’s signals
reg [3:0] t_in;
reg clk;

top inst(t_out, t_in, clk); // Top’s instance

initial begin // Generate clock

clk = 0;
forever #10 clk = ~clk;
end

initial begin // Generate remaining inputs

$monitor($time, " %b -> %b", t_in, t_out);
#5 t_in = 4'b0101;
#20 t_in = 4'b1110;
#20 t_in[0] = 1;
#300 $finish;
end

endmodule

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Exercise Questions
1. Write a Verilog code for designing the full-adder using
gate level primitives.
2. Write a Verilog code for a generic specification of a ripple-
carry adder using for loops.
3. Write a Verilog code for designing the full-subtractor using
gate level primitives.
4. Write a Verilog code for testing a 4 bit parallel subtractor
using structural modelling style.
5. Write a Verilog code for designing the full-adder using Half
adders.
6. Write a Verilog behavioral model to design an n-bit adder
with carry-out and overflow signals. (select n=16)
7. Write a Verilog code for designing a 4 bit comparator.

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