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Clockless Chip

The document summarizes a presentation on clockless chips. It introduces problems with synchronous circuits like wasted energy from distributing clocks globally. Clockless chips work asynchronously using handshake signals between components rather than a centralized clock, allowing different parts to work at varying speeds. This approach minimizes power consumption and reduces electromagnetic interference. While clockless chips offer advantages like lower power usage and extended battery life, challenges remain in interfacing them with mostly synchronous devices and a lack of expertise and tools in their design.

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Ramireddy Gangadhar Reddy
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232 views20 pages

Clockless Chip

The document summarizes a presentation on clockless chips. It introduces problems with synchronous circuits like wasted energy from distributing clocks globally. Clockless chips work asynchronously using handshake signals between components rather than a centralized clock, allowing different parts to work at varying speeds. This approach minimizes power consumption and reduces electromagnetic interference. While clockless chips offer advantages like lower power usage and extended battery life, challenges remain in interfacing them with mostly synchronous devices and a lack of expertise and tools in their design.

Uploaded by

Ramireddy Gangadhar Reddy
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Date: February 14, 2012.

Clockless Chips
Presented by: KONIJETI NARASIMHA RAO (11C104216) Vardhaman College of Engineering.

Presentation flow:
       

Introduction. Problems with synchronous circuits. Clockless / Asynchronous circuits. How clockless chips work? Simplicity in design. Applications. Applications (technical perspective). Challenges.
Presentation on Clockless Chips 2

February 14, 2012

Introduction.


Struggle for the improvement in the microprocessors performance/functioning.


Pipelining (Simultaneous) Multi-threading Clockless / Asynchronous logic

Synchronous

February 14, 2012

Presentation on Clockless Chips

Problems with Synchronous Approach


    

Distributing the clock globally. Wastage of energy. Traverse the chips longest wires in one clock cycle. Order of arrival of the signals is unimportant. Clocks themselves consume lot of energy (~30%).
February 14, 2012 Presentation on Clockless Chips 4

Synchronous circuit


Longest path determines the minimum clock period.

Dissipation of energy for each clock cycle.

EMI is more in synchronous elements.

February 14, 2012

Presentation on Clockless Chips

Clockless chips (Asynchronous logic circuits)


   

Colckless chips/Asynchronous/self-timed circuits. Functions away from the clock. Different parts work at different speeds. Hand-off the result immediately.

February 14, 2012

Presentation on Clockless Chips

Clock time cycle vs. clockless time cycle

Courtesy: Fulcrum Microsystems.


February 14, 2012 Presentation on Clockless Chips 7

Courtesy: Computers without clocks Ivan E Sutherland and Jo Ebergen


February 14, 2012 Presentation on Clockless Chips 8

How do they work?


  

No pure asynchronous chips are available. Uses handshake signals for the data exchange. Data moves only when required, not always.
Minimizes power consumption. Less EMI less noise more applications. Stream data applications.

February 14, 2012

Presentation on Clockless Chips

Simple and efficient design


 

No centralized clock required. Standardized components can be used.

February 14, 2012

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Some features


Integrated pipelining mode.


Domino logic. Delay insensitive.

Two different implementation details


Dual rail. Bundled data.

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Advantages
    

Works at its average speed. Low power consumption.


Twice life-time.

Less heat generated.


Good to mobile devices.

Less EMI less noise more applications. Smart cards (due to asynchronous nature).

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Advantages (technical look)




Asynchronous for higher performance:


Data-dependent delays. All carry bits need to be computed.

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Advantages (technical look)




Asynchronous for low power:


Consumes power only when and where active. Rest of the time returns to a non-dissipating state, until next activation. Illustrated through frequency divider

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Advantages (technical look)




Asynchronous for low power:


Almost fixed power dissipation is achieved. Many applications such as:
Infrared communication receiver. Filter bank for digital hearing. In pagers. Double battery life.

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Advantages (technical look)




Asynchronous for low noise and low emission:


Digital sub-circuits
Generates voltage noise (on power lines) Induces current on silicon substrate. Emits electromagnetic radiation at its clock frequency or its harmonics.

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Advantages (technical look)




Heterogeneous Timing:
Gate delays. Interconnection delays. Heterogeneous systems would increase the delays in the circuits.

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Challenges


Interfacing between synchronous and asynchronous


Many devices available now are synchronous in nature. Special circuits are needed to align them.

   

Lack of expertise. Lack of tools. Engineers are not trained in these fields. Academically, no courses available.
Presentation on Clockless Chips 18

February 14, 2012

References


Scanning the Technology: Applications of Asynchronous Circuits C. H. (Kees) van Berkel, Mark B. Josephs, and Steven M. Nowick Computers without clocks Ivan E Sutherland and Jo Ebergen. http://ieeexplore.ieee.org/iel5/2/30617/01413111.pdf (October 2001) http://csdl2.computer.org/comp/mags/dt/2003/06/d6005.pdf http://www1.cs.columbia.edu/async/misc/technologyreview_oct_0 1_2001.html http://www.technologyreview.com/articles/01/10/tristram1001.asp http://www1.cs.columbia.edu/async/misc/economist/Economist_c om.htm
February 14, 2012 Presentation on Clockless Chips 19

   

 

Thank you

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