Interrupts

Interrupts
Computers often need to handle multiple
tasks simultaneously or respond to external
events promptly.
Interrupts are a mechanism that allows the
CPU to suspend its current activities
temporarily to respond to a specific event.
When an interrupt occurs, the CPU stops
executing its current task and transfers
control to a designated code segment
called the Interrupt Service Routine (ISR) or
Interrupt Handler.
Interrupts
Each type of interrupt is assigned an index
from 0—255.
 0—31 are for processor interrupts fixed
by Intel
 E.g., 14 is always for page faults
32—255 are software configured
 32—47 are often for device interrupts
(IRQs)
 Most device’s IRQ line can be configured
 Why do we need interrupts?
Interrupts are a fundamental aspect of computer
systems, and they serve several critical purposes that
make them indispensable. Here are the key reasons
why we need interrupts:
●Fix an abnormal condition
 Page not mapped in memory
● Notifications from external devices
 Network packet received
● Preemptive scheduling
 Timer interrupt
● Secure interface between OS and applications
 System calls
 Cont…
 Handling Asynchronous Events: Interrupts allow the
CPU to respond to external events that occur
asynchronously, such as user input from a keyboard, data
arriving from a network, or a hardware device signaling
the completion of an operation.
 Efficient Resource Utilization: Instead of constantly
polling hardware devices to check if they need attention,
interrupts enable the CPU to perform other tasks until a
device requires servicing.
 Real-Time Response: Interrupts enable real-time
systems to respond promptly to critical events without
waiting for the completion of ongoing tasks.
 Prioritization: Interrupts can be prioritized, ensuring
that more urgent or important events are handled before
less critical ones.
 Exception Handling: Interrupts are used to handle
Types of Interrupts
Hardware Interrupts: Triggered by
external hardware devices (e.g., keyboard,
mouse, timer, I/O devices) to request the
CPU's attention.
Software Interrupts: Invoked by software
instructions (system calls) to request
services from the operating system.
Exception Interrupts: Caused by
exceptional conditions during program
execution, such as division by zero or
invalid memory access.
 The Interrupt Cycle
 Detection: An external device generates a signal (e.g., a
hardware device sends an electrical signal) to indicate an
interrupt condition or the CPU detects an exception
condition internally.
 Interrupt Request (IRQ): The signal is sent to the
Interrupt Controller, which prioritizes interrupts and informs
the CPU.
 Interrupt Acknowledge: The CPU acknowledges the
interrupt request and saves the current execution state on
the stack.
 Interrupt Handling: The CPU looks up the Interrupt Vector
Table (IVT) to find the memory address of the corresponding
Interrupt Service Routine (ISR) for the specific interrupt
type.
 Interrupt Service Routine (ISR): It is the code
responsible for handling the specific interrupt. It performs
 Instruction Cycle with ‘Interrupts Cycle’
 To accommodate interrupts, an interrupt cycle is
added to the ‘instruction cycle’.
 In the interrupt cycle the processor checks to see if
any interrupts have occurred, indicated by the
presence of an interrupt signal.
 If no interrupts are pending, the processor
proceeds to the fetch cycle and fetches the next
instruction of the current program.

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 Instruction Cycle, ‘State Diagram’
with Interrupts

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 Steps of ‘Interrupt Handler
Process’
Hardware sends an electrical signal on a
physical interrupt line.
Processor detects that signal and translates
it into an interrupt request (IRQ) number.
Processor then jumps to interrupt handling
code.
Software searches through its interrupt
request table (stored in RAM) for entry or
entries that match the IRQ.
If found, software jumps to the registered
interrupt service routine (ISR).
11 If not found, software ignores interrupt.
 Interrupt Handler and Multiple Interrupts

 When multiple interrupts occur simultaneously or

in rapid succession, it leads to the issue of
interrupt handling.
 To manage this, a priority system is often
employed. Some interrupts are given higher
priority than others.
 If a higher-priority interrupt occurs while the CPU is
handling a lower-priority interrupt, the CPU
suspends the current ISR and begins executing the
higher-priority ISR.
 The priority of interrupts is typically configurable,
and hardware may also include masking
mechanisms to enable or disable specific
interrupts.
 Multiple Interrupts (example)
 There is a possibility that multiple interrupts can
occur at a time.
 For example, a program may be receiving data
from communication line and printing results.
 The printer will generate interrupt every time it
completes a printer operation.
 The communication line controller will generate
an interrupt every time a unit of data arrives.
(e.g. a character or a block of data)
 In any case, it is possible for a communications
interrupt to occur while a printer interrupt is
being processed.

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 Two Approaches to Dealing with
‘Multiple Interrupts’
1. Disable interrupts (Maskable interrupt)
Processor will ignore further interrupts whilst
processing one interrupt.
Interrupts remain pending and are checked after first
interrupt (ISR) has been processed.
Interrupts handled in sequence as they occur. (e.g.
data may be lost on a line)
Drawback, it does not take into account relative
priority, or time critical needs.
2. Define priorities (Non-Maskable interrupt)
Low priority interrupts can be interrupted by higher
priority interrupts.
When higher priority interrupt has been processed,
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processor returns to previous interrupt.
Conclusion
 Interrupts are vital for the efficient functioning
of modern computer systems.
 They allow CPUs to respond to external events
promptly, handle multiple tasks simultaneously
and efficient use of system resources.
 Proper interrupt handling is crucial to ensure
the stability and responsiveness of computer
systems.
 Without interrupts, computer systems would be
much less capable, less responsive, and more
resource-intensive.