Input / Output

UNIT 5
Peripheral devices
A peripheral or peripheral device is an auxiliary device used to put
information into and get information out of a computer. The term peripheral
device refers to all hardware components that are attached to a computer and
are controlled by the computer system. Input or output devices attached to the
computer are also called peripherals. Among the most common peripherals
are keyboards, display units, and printers.

 An Input device sends data or instructions to the computer, such as

a mouse, keyboard, image scanner, barcode reader, light
pen, microphone and webcam;
 An Output device provides output data from the computer, such as
a computer monitor, projector, printer, headphones and computer speaker;
 An Input/Output device performs both input and output functions, such
as a computer data storage device (including a disk drive, solid-state
drive, USB flash drive, memory card and tape drive).
Input-Output Interface
Input-output interface provides a method for transferring
information between internal storage and external I/0 device.
Peripherals connected to a computer need special
communication links for interfacing them with the central
processing unit. The purpose of the communication link is to
resolve the differences that exist between the central computer
and each peripheral.
The major differences are:

1. Peripherals are electromechanical and electromagnetic devices and

their manner of operation is different from the operation of the
CPU and memory, which are electronic devices. Therefore, a
conversion of signal values may be required.
2. The data transfer rate of peripherals is usually slower than the
transfer rate of the CPU, and consequently, a synchronization
mechanism may be needed.
3. Data codes and formats in peripherals differ from the word format
in the CPU and memory.
4. The operating modes of peripherals are different from each other
and each must be controlled so as not to disturb the operation of
other peripherals connected to the CPU.
 To resolve these differences, computer systems include special hardware
components between the CPU and peripherals to supervise and
synchronize all input and output transfers. These components are called
interface units because they interface between the processor bus and the
peripheral device.

I/O BUS
 A typical communication link between the processor and several
peripherals is shown in Fig. The I/O bus consists of data lines, address
lines, and control lines. The magnetic disk, printer, and terminal are
employed in practically any general-purpose computer..
 Each peripheral device has associated with it an interface unit. Each
interface decodes the address and control received from the I/O bus,
interprets them for the peripheral, and provides signals for the peripheral
controller. It also synchronizes the data flow and supervises the transfer
between peripheral and processor.
 The I/O bus from the processor is attached to all peripheral interfaces. To
communicate with a particular device, the processor places a device
address on the address lines. Each interface attached to the I/0 bus contains
an address decoder that monitors the address lines. When the interface
detects its own address, it activates the path between the bus lines and the
device that it controls. All peripherals whose address does not correspond
to the address in the bus are disabled by their interface.
I/O Commands
An interface receives any of the following four commands
 Control − A control command is issued to activate the peripheral
and to inform it what to do.
 Status − A status command is used to test various status conditions
in the interface and the peripheral. For example, the computer may
wish to check the status of the peripheral before a transfer is
initiated.
 Data Output − A data output command causes the interface to
respond by transferring data from the bus into one of its registers
 Data Input − The data input command is opposite to the data
output command. In data input, the interface gets an element of data
from the peripheral and places it in its buffer register.
Example of I/O Interface
 Port A and Port B: The l/0 data to and from the device can be transferred into either port A or
port B. Each port consist of bi-directional data input buffer and bi-directional data output buffer.
 Control and Status Register :
CPU gives control information to control register on basis of control information. Interface unit
control input and output operation between CPU and input-output device. Bits which are present
in status register are used for checking of status conditions. Status register indicate status of data
register, port A, port B and also record error that may be occur during transfer of data.
 The l/0 read and write are two control lines that specify an input or output, respectively
 This circuit enables the chip select (CS) input when the interface is selected by the address bus.
The two register select inputs RSl and RSO select one of the four registers in the interface as
specified in the table accompanying the diagram. The content of the selected register is transfer
into the CPU via the data bus when the I/O read signal is enabled. The CPU transfers binary
information into the selected register via the data bus when the I/O write input is enabled.
Interrupts

 In computer architecture, an interrupt is a signal to the processor emitted by hardware

or software indicating an event that needs immediate attention.
 Interrupt is a signal emitted by hardware or software when a process or an event needs
immediate attention. It alerts the processor to a high priority process requiring interruption
of the current working process. In I/O devices one of the bus control lines is dedicated for
this purpose and is called the Interrupt Service Routine (ISR).
 An interrupt in computer architecture is a signal that requests the processor to suspend its
current execution and service the occurred interrupt. To service the interrupt the processor
executes the corresponding interrupt service routine (ISR). After the execution of the
interrupt service routine, the processor resumes the execution of the suspended program
INTERRUPT HANDLING MECHANISM AND
INTERRUPT SERVICE ROUTINE (ISR):

 The job of the interrupt handler in Interrupt handling is to service the device and
stop it from interrupting. Once the handler returns, the CPU resumes what it was
doing before the interrupt occurred
 The routine that gets executed when an interrupt request is made is called as
interrupt service routine.
 Step 1: When the interrupt occurs the processor is currently
executing i’th instruction and the program counter will be currently
pointing to (i + 1)th instruction.
 Step 2: When the interrupt occurs the program counter value is stored on
the processes stack.
 Step 3: The program counter is now loaded with the address of interrupt
service routine.
 Step 4: Once the interrupt service routine is completed the address on the
processes stack is pop and place back in the program counter.
 Step 5: Execution resumes from (i + 1)th line of compute routine
TYPES OF INTERRUPTS
Although interrupts have highest priority than other signals, there are many type of interrupts but basic type of
interrupts are –

1.Hardware Interrupts

2. Software Interrupts

1.Hardware Interrupts: If the signal for the processor is from external device or hardware is called hardware
interrupts.
 Example: from keyboard we will press the key to do some action this pressing of key in keyboard will
generate a signal which is given to the processor to do action, such interrupts are called hardware
interrupts.

Hardware interrupts can be classified into two types ->

 Maskable Interrupt: The hardware interrupt that can be ignored or delayed for some time if the processor
is executing a program with higher priority are termed as maskable interrupts.
 Non Maskable Interrupt: The hardware interrupts that can neither be ignored nor delayed and must
immediately be serviced by the processor are termed as non-maskable interrupts.
2. Software Interrupts: Software interrupt can also divided in to two types they are -

 Normal Interrupts: the interrupts which are caused by the software

instructions are called software instructions.

 Exception: unplanned interrupts while executing a program is called

Exception. For example: while executing a program if we got a value which

should be divided by zero is called a exception.

Example: Division by zero, execution of an illegal opcode or memory related

fault could cause exceptions.

INTERRUPT HARDWARE

Many computers have facility to connect two or more input and output
devices to it like laptop may have 3 USB slots. All these input and output
devices are connected via switches as shown -
 So there is a common interrupt line for all N input/output devices and the interrupt handling

works in the following manner ->

1. When no interrupt is issued by the input/output devices then all the switches are open

and the entire voltage from Vdd is flown through the single line INTR and reaches the

processor. Which means the processor gets a voltage of 1V.

2. When the interrupt is issued by the input/output devices then the switch associated with

the input/output device is closed, so the entire current now passes via the switches which

means the hardware line reaching the processes i.e INTR line gets 0 voltage. This is an

indication for the processor that an interrupt has occurred and the processor needs to

identify which input/output device has triggered the interrupt

3. The value of INTR is a logical NOT of the requests from individual devices.

4. The resistor R is called as a pull up resistor because it pulls the line voltage to high

voltage state when all switches are open( no interrupt state).

Priority Interrupt

 A priority interrupt is a system which decides the priority at which various devices,
which generates the interrupt signal at the same time, will be serviced by the CPU.
The system has authority to decide which conditions are allowed to interrupt the
CPU, while some other interrupt is being serviced. Generally, devices with high
speed transfer such as magnetic disks are given high priority and slow devices such
as keyboards are given low priority.
 When two or more devices interrupt the computer simultaneously, the computer

services the device with the higher priority first.

This could be done with either software or hardware methods.
1. Software Method
• Polling
2. Hardware Method
• DAISY CHAINING Priority
• Parallel Priority Interrupt
POLLING
In this method, all interrupts are serviced by branching to the same service program.
This program then checks with each device if it is the one generating the interrupt.
The order of checking is determined by the priority that has to be set. The device
having the highest priority is checked first and then devices are checked in descending
order of priority. If the device is checked to be generating the interrupt, another
service program is called which works specifically for that particular device.
The structure will look something like this-

• The disadvantage of the software method is

that if there are many interrupts, the time
required to poll them can exceed the time
available to service the I/O device. In this
situation a hardware priority-interrupt unit
can be used to speed up the operation.
Daisy chaining priority
interrupt
 The daisy-chaining method involves connecting all the devices that can request an interrupt in
a serial manner. This configuration is governed by the priority of the devices. The device with
the highest priority is placed first followed by the second highest priority device and so on.
The given figure depicts this arrangement.
WORKING:
There is an interrupt request line which is common to all the devices and goes into the CPU.
 When no interrupts are pending, the line is in HIGH state. But if any of the devices raises an

interrupt, it places the interrupt request line in the LOW state.

 The CPU acknowledges this interrupt request from the line and then enables the interrupt

acknowledge line in response to the request.

 This signal is received at the PI(Priority in) input of device 1.

 If the device has not requested the interrupt, it passes this signal to the next device through its

PO(priority out) output. (PI = 1 & PO = 1)

 However, if the device had requested the interrupt, (PI =1 & PO = 0)

◦ The device consumes the acknowledge signal and block its further use by placing 0 at its
PO(priority out) output.
◦ The device then proceeds to place its interrupt vector address(VAD) into the data bus of CPU.
◦ The device puts its interrupt request signal in HIGH state to indicate its interrupt has been
taken care of.
NOTE: VAD is the address of the service routine which services that device.
 If a device gets 0 at its PI input, it generates 0 at the PO output to tell other devices that

acknowledge signal has been blocked. (PI = 0 & PO = 0)

 Hence, the device having PI = 1 and PO = 0 is the highest priority device that is requesting an

interrupt. Therefore, by daisy chain arrangement we have ensured that the highest priority
interrupt gets serviced first and have established a hierarchy. The farther a device is from the first
device, the lower its priority
Parallel Priority Interrupt
Working
 The parallel priority interrupt method uses a register whose bits are set separately by the
interrupt signal from each device. Priority is established according to the position of the bits in
the register.
 In addition to the interrupt register, the circuit may include a mask register whose purpose is
to control the status of each interrupt request. The mask register can be programmed to disable
lower-priority interrupts while a higher-priority device is being serviced. It can also provide a
facility that allows a high-priority device to interrupt the CPU while a lower-priority device is
being serviced.
 The magnetic disk, being a high-speed device, is given the highest priority. The printer has the
next priority, followed by a character reader and a keyboard.
 Each interrupt bit and its corresponding mask bit are applied to an AND gate to produce the
four inputs to a priority encoder. In this way an interrupt is recognized only if its
corresponding mask bit is set to 1 by the program.
 The priority encoder generates two bits of the vector address, which is transferred to the CPU.
 Another output from the encoder sets an interrupt status flip-flop lST when an interrupt that is
not masked occurs. The interrupt enable flip-flop lEN can be set or cleared by the program to
provide an overall control over the interrupt system.
 The outputs of lST ANDed with lEN provide a common interrupt signal for the CPU. The
interrupt acknowledge IN'TACK signal from the CPU enables the bus buffers in the output
register and a vector address VAD is placed into the data bus.

Priority Encoder
 The logic of the priority encoder is such that if two or more inputs arrive at the same time, the
input having the highest priority will take precedence.
 The x's in truth table designate don't-are conditions. Input I 0 has the highest priority; so
regardless of the values of other inputs, when this input is 1, the output generates an output xy
= 00.
 I1 has the next priority level The output is 01 if I 1 =1 provided that I0 = 0, regardless of the
values of the other two lower-priority inputs. The output for I 2 is generated only if higher-
priority inputs are 0, and so on down the priority level.
Modes of Transfer
 Binary information received from an external device is usually stored in memory for later
processing. Information transferred from the central computer into an external device
originates in the memory unit. The CPU merely executes the I/O instructions and may
accept the data temporarily, but the ultimate source or destination is the memory unit.
 Data transfer between the central computer and I/O devices may be handled in a variety
of modes. Some modes use the CPU as an intermediate path; others transfer the data
directly to and from the memory unit. Data transfer to and from peripherals may be
handled in one of three possible modes.
1. Programmed I/O

2. Interrupt-initiated I/O

3. Direct memory access (DMA)

• Programmed I/O:
It is due to the result of the I/O instructions that are written in the computer program. Each data
item transfer is initiated by an instruction in the program. Usually the transfer is from a CPU
register and memory. In this case it requires constant monitoring by the CPU of the peripheral
devices.
In the programmed I/0 method, the I/O device does not have direct access to memory. A transfer
from an I/O device to memory requires the execution of several instructions by the CPU,
including an input instruction to transfer the data from the device to the CPU and a store
instruction to transfer the data from the CPU to memory
Example of Programmed I/O:
 An example of data transfer from an I/O device through an interface into the CPU is shown in
Fig. The device transfers bytes of data one at a time as they are available. When a byte of data
is available, the device places it in the I/O bus and enables its data valid line. The interface
accepts the byte into its data register and enables the data accepted line. The interface sets a
bit in the status register that we will refer to as an F or "flag" bit. The device can now disable
the data valid line, but it will not transfer another byte until the data accepted line is disabled
by the interface.
 A program is written for the computer to check the flag in the status register to determine if a
byte has been placed in the data register by the I/O device. This is done by reading the status
register into a CPU register and checking the value of the flag bit. If the flag is equal to 1, the
CPU reads the data from the data register. The flag bit is then cleared to 0 by either the CPU
or the interface, depending on how the interface circuits are designed. Once the flag is cleared,
the interface disables the data accepted line and the device can then transfer the next data byte.
Fig.2 Flowchart for CPU program to input
data.
A flowchart of the program that must be written for the CPU is shown in Fig. It is assumed that
the device is sending a sequence of bytes that must be stored in memory. The transfer of each
byte requires three instructions:

1. Read the status register.

2. Check the status of the flag bit and branch to step 1 if not set or to step 3 if set.

3. Read the data register.

Disadvantages: In the programmed I/0 method, the CPU stays in a program loop until the I/0
unit indicates that it is ready for data transfer. This is a time-consuming process since it keeps the
processor busy needlessly. CPU continuously check status register until status flag is set.
Interrupt-initiated I/O

 In the programmed I/0 method, the CPU stays in a program loop until the 1/0 unit
indicates that it is ready for data transfer. This is a time-consuming process since it
keeps the processor busy needlessly.
 An alternative to the CPU constantly monitoring the flag is to let the interface
inform the computer when it is ready to transfer data. This mode of transfer uses
the interrupt facility. While the CPU is running a program, it does not check the
flag. However, when the flag is set, the computer is momentarily interrupted from
proceeding with the current program and is informed of the fact that the flag has
been set. The CPU deviates from what it is doing to take care of the input or output
transfer.
 After the transfer is completed, the computer returns to the previous program to
continue what it was doing before the interrupt .
Direct memory access (DMA)

 Direct Memory Access (DMA) transfers the data between the memory and peripheral
devices of the system, without the participation of the processor. The unit that controls the
activity of accessing memory directly is called a DMA controller.

 Figure 11-16 shows two control signals in the CPU that facilitate the DMA transfer-
 The bus request (BR) input is used by the DMA controller to request the CPU to leave control
of the buses. When this input is active, the CPU terminates the execution of the current
instruction and places the address bus, the data bus, and the read and write lines into a high-
impedance state.
 The CPU activates the bus grant (BG) output to inform the external DMA that the buses are
in the high-impedance state.
 The DMA that originated the bus request can now take control of the buses to conduct
memory transfers without processor intervention.
  When the DMA terminates the transfer, it disables the bus request line. The
CPU disables the bus grant, takes control of the buses, and returns to its normal
operation.
 When the DMA takes control of the bus system, it communicates directly with

the memory.
The transfer can be made in several ways-
burst transfer:
 In DMA burst transfer, a block sequence consisting of a number of memory

words is transferred in a continuous burst while the DMA controller is master

of the memory buses.
 This mode of transfer is needed for fast devices such as magnetic disks, where

data transmission cannot be stopped or slowed down until an entire block is

transferred.
cycle stealing
 An alternative technique called cycle stealing allows the DMA controller to

transfer one data word at a time, after which it must return control of the buses
to the CPU.
DMA Controller
DMA Controller is a hardware device that allows I/O devices to directly access memory with less
participation of the processor .
 The DMA controller needs the usual circuits of an interface to communicate with the CPU and
I/O device. In addition, it needs an address register, a word count register, and a set of address
lines. The address register and address lines are used for direct communication with the
memory The word count register specifies the number of words that must be transferred.
 The data transfer may be done directly between the device and memory under control of the
DMA.
 Figure 11-17 shows the block diagram of a typical DMA controller. The unit communicates
with the CPU via the data bus and control lines. The registers in the DMA are selected by the
CPU through the address bus by enabling the DS (DMA select) and RS (register select)
inputs. The RD (read) and WR (write) inputs are bidirectional.
 When the BG (bus grant) input is 0, the CPU can communicate with the DMA registers
through the data bus to read from or write to the DMA registers.
 When BG=1, the CPU has relinquished the buses and the DMA can communicate directly
with the memory by specifying an address in the address bus and activating the RD or WR
control. The DMA communicates with the external peripheral through the request and
acknowledge lines by using a prescribed handshaking procedure.
 The DMA controller has three registers: an address register, a word count register, and a
control register. The address register contains an address to specify the desired location in
memory. The address bits go through bus buffers into the address bus. The address register is
incremented after each word that is transferred to memory..
 The word count register holds the number of words to be transferred. This register
is decremented by one after each word transfer and internally tested for zero.
 The control register specifies the mode of transfer (Read or Write).

 The CPU initializes the DMA by sending the following information through the

data bus:
1. The starting address of the memory block where data are available (for read) or
where data are to be stored (for write)
2. The word count, which is the number of words in the memory block

3. Control to specify the mode of transfer such as read or write

4. A control to start the DMA transfer.
The starting address is stored in the address register. The word count is stored in the
word count register, and the control information in the control register. Once the DMA
is initialized, the CPU stops communicating with the DMA unless it receives an
interrupt signal or if it wants to check how many words have been transferred.
DMA Transfer
 The position of the DMA controller among the other components in a computer system is illustrated
in Fig. 11-18. The CPU communicates with the DMA through the address and data buses as with
any interface unit.
 When the peripheral device sends a DMA request, the DMA controller activates the BR line,
informing the CPU to relinquish the buses. The CPU responds with its BG line, informing the DMA
that its buses are disabled. The DMA then puts the current value of its address register into the
address bus, initiates the RD or WR signal, and sends a DMA acknowledge to the peripheral device.
Note that the RD and WR lines in the DMA controller are bidirectional. The direction of transfer
depends on the status of the BG line.
 When BG=0, the RD and WR are input lines allowing the CPU to communicate with the internal
DMA registers. When BG=1, the RD and WR are output lines from the DMA controller to the
random-access memory to specify the read or write operation for the data.
 When the peripheral device receives a DMA acknowledge, it puts a word in the data bus (for write)
or receives a word from the data bus (for read). Thus the DMA controls the read or write operations
and supplies the address for the memory. The peripheral unit can then communicate with memory
through the data bus for direct transfer between the two units while the CPU is momentarily
disabled.
 For each word that is transferred, the DMA increments its address register and decrements its word
count register.
 If the word count register reaches zero, the DMA stops any further transfer and removes its bus
request. It also informs the CPU of the termination by means of an interrupt. When the CPU
responds to the interrupt, it reads the content of the word count register. The zero value of this
register indicates that all the words were transferred successfully
Input-Output Processor
(IOP)
 An input–output processor (IOP) may be classified as a processor with direct memory access
capability that communicates with I/O devices.
 The IOP is similar to a CPU except that it is designed to handle the details of I/O processing.
 Unlike the DMA controller that must be set up entirely by the CPU, the IOP can fetch and
execute its own instructions. IOP instructions are specifically designed to facilitate I/O
transfers.
 The block diagram of a computer with two processors is shown in Fig. 11-19. The memory
unit occupies a central position and can communicate with each processor by means of direct
memory access.
 The CPU is responsible for processing data needed in the solution of computational tasks. The
IOP provides a path for transfer of data between various peripheral devices and the memory
unit.
CPU—IOP Communication
 The communication between CPU and IOP may take different forms, depending on the
particular computer considered. In most cases the memory unit acts as a message center where
each processor leaves information for the other .
 The CPU sends an instruction to test the IOP path. The IOP responds by inserting a
status word in memory for the CPU to check.
 The bits of the status word indicate the condition of the IOP and I/O device, such as
IOP overload condition, device busy with another transfer, or device ready for I/O
transfer.
 The CPU refers to the status word in memory to decide what to do next. If all is in
order, the CPU sends the instruction to start I/O transfer.
 The memory address received with this instruction tells the IOP where to find it?
program.
 The CPU can now continue with another program while the IOP is busy with the
I/O program.
 When the IOP terminates the execution of its program, it sends an interrupt request
to the CPU.
 The CPU responds to the interrupt by issuing an instruction to read the status from
the IOP.
 The IOP responds by placing the contents of its status report into a specified
memory location. The status word indicates whether the transfer has been
completed or if any errors occurred during the transfer.
 From inspection of the bits in the status word, the CPU determines if the I/O
operation was completed satisfactorily without error.
Status: The status field identifies the conditions in the device
and the channel and any errors that occurred during the
transfer
Channel Command Word Format :
 data address: The data address field specifies the first address of a memory buffer.
 count : the count field gives the number of bytes involved in the transfer.
 Flag: the flag bits provide additional information for the channel.
 Command code: The command field corresponds to an operation code that
specifies one of six basic types of I/O operations:
1. Read:. Transfer data from memory to I/O device.
2. Write: Transfer data from I/O device to memory.
3. Read backwards: Read magnetic tape with tape moving backward.
4. Control: Used to initiate an operation not involving transfer of data, such as
rewinding of tape or positioning a disk-access mechanism.
5. Sense: Informs the channel to transfer its channel status word to memory
location 64.
6. Transfer in channel:Used instead of a jump instruction. Here the data address
field specifies the address of the next command word to be executed by the
channel.
Location of information in memory for I/O
operations in the IBM 370
• The operation begins when the CPU
program encounters a start I/O instruction.
The IOP then goes to memory location 72 to
obtain a channel address word. This word
contains the starting address of the I/O
channel program. The channel then
proceeds to execute the program specified
by the channel command words. The
channel constructs a status word during the
transfer and stores it in location 64. Upon
interruption, the CPU can refer to memory
location 64 for the status word
Intel 8089 IOP

 The 8089 is designed to function as an IOP in a microcomputer system where the Intel 8086
microprocessor is used as the CPU.
 Within the 8089 are two independent units called channels.
 A microcomputer system using the Intel 8086/8089 pair of integrated circuits is shown in Fig.
11-23. The 8086 functions as the CPU and the 8089 as the IOP. The two units share a common
memory through a bus controller connected to a system bus, which is called a “multibus” by
Intel. The IOP uses a local bus to communicate with various interface units connected to I/O
devices.
 The CPU communicates with the IOP by enabling the channel attention line.
 The select line is used by the CPU to select one of two channels in the 8089.
 The IOP gets the attention of the CPU by sending an interrupt request.
 The CPU and IOP communicate with each other by writing messages for one another in
system memory.
 The CPU prepares the message area and signals the IOP by enabling the channel attention
line. The IOP reads the message, performs the required I/O functions, and executes the
appropriate channel program. When the channel has completed its program, it issues an
interrupt request to the CPU.
 The communication scheme consists of program sections called “blocks,” which are stored in
memory as shown in Fig. 11-24.
 The busy flag indicates whether the IOP is busy or ready to perform a new I/O operation.
 The CCW (channel command word) is specified by the CPU to indicate the type of operation
required from the IOP
 The CCW here is more like an I/O instruction that specifies an operation for the IOP, such as
start operation, suspend operation, resume operation, and halt I/O program.
 The parameter block contains variable data that the IOP program must use in carrying out its
task. The task block contains the actual program to be executed in the IOP.
 The CPU then fills in the information in the parameter block and writes a “start operation”
command in the CCW.
 After the communication blocks have been set up, the CPU enables the channel attention
signal to inform the IOP to start its I/O operation. The CPU then continues with another
program.
 The IOP starts executing the program in the task block using the information in the parameter
block. The entries in the parameter block depend on the I/O device. The parameters listed in
Fig. 11-24 are suitable for data transfer to or from a magnetic disk.
 The memory address specifies the beginning address of a memory buffer. The byte count
gives the number of bytes to be transferred.
 The device address specifies the particular I/O device to be used. The track and sector
numbers locate the data on the disk. When the I/O operation is completed, the IOP stores its
status bits in the status word location of the parameter block and interrupts the CPU.
 The CPU can refer to the status word to check if the transfer has been completed satisfactorily.