Long Term Scheduling

In some systems a newly

created process begins
Determines which Once submitted, a job in a swapped-out
programs are submitted becomes a process for condition, in which case
for processing the short term scheduler it is added to a queue for
the medium-term
scheduler

Time-sharing system Batch system

• A process request is generated when a
• Newly submitted jobs are routed to disk
user attempts to connect to the
and held in a batch queue
system
• The long-term scheduler creates
• OS will accept all authorized comers
processes from the queue when it can
until the system is saturated
• At that point a connection request is
met with a message indicating that
the system is full and to try again later

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+
Medium-Term Scheduling
and Short-Term Scheduling
Medium-Term Short-Term
Part of the swapping function  Also known as the
Swapping-in decision is based on dispatcher
the need to manage the degree of  Executes frequently and
multiprogramming
makes the fine-grained
Swapping-indecision will consider decision of which job to
the memory requirements of the execute next
swapped-out processes

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© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
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 Logical address
- expressed as a location
relative to the beginning of the
program

Physical address
- an actual location in main
memory

Base address
- current starting location of
the process

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+ Virtual Memory
Demand Paging
 Each page of a process is brought in only when it is needed
 Principle of locality
 When working with a large process execution may be confined to a small section
of a program (subroutine)
 It is better use of memory to load in just a few pages
 If the program references data or branches to an instruction on a page not in main
memory, a page fault is triggered which tells the OS to bring in the desired page

 Advantages:
 More processes can be maintained in memory
 Time is saved because unused pages are not swapped in and out of memory

 Disadvantages:
 When one page is brought in, another page must be thrown out (page
replacement)
 If a page is thrown out just before it is about to be used the OS will have to go get
the page again
 Thrashing
 When the processor spends most of its time swapping pages rather than
executing instructions
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+
Segmentation

 Usually visible to the programmer

 Advantages:
 Provided as a convenience for
organizing programs and data and as  Simplifies the handling of
a means for associating privilege and growing data structures
protection attributes with instructions
and data
 Allows programs to be
altered and recompiled
 Allows the programmer to view independently without
memory as consisting of multiple requiring that an entire
address spaces or segments set of programs be re-
linked and re-loaded
 Lends itself to sharing
among processes
 Lends itself to protection

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  Includes hardware for both segmentation and paging
 Unsegmented unpaged memory Intel
Virtual address is the same as the physical address
x86


 Useful in low-complexity, high performance controller

applications
 Unsegmented paged memory
 Memory is viewed as a paged linear address space
 Protection and management of memory is done via paging
 Favored by some operating systems
 Segmented unpaged memory Memory
 Memory is viewed as a collection of logical address spaces Management
 Affords protection down to the level of a single byte
 Guarantees that the translation table needed is on-chip
when the segment is in memory
 Results in predictable access times
+  Segmented paged memory
 Segmentation is used to define logical memory partitions
subject to access control, and paging is used to manage
the allocation of memory within the partitions
 Operating systems such as UNIX System V favor this view

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+
Segmentation
 Each virtual address consists of a 16-bit segment
reference and a 32-bit offset
 Two bits of segment reference deal with the protection
mechanism
 14 bits specify segment

 Unsegmented virtual memory is 232 = 4Gbytes

 Segmented virtual memory is 246=64 terabytes (Tbytes)
 Physical address space employs a 32-bit address for a
maximum of 4 Gbytes
 Virtual address space is divided into two parts
 One-half is global, shared by all processors
 The remainder is local and is distinct for each process
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+ Segment Protection
 Associated with each segment are two forms of protection:
 Privilege level
 Access attribute

 There are four privilege levels

 Most protected (level 0)
 Least protected (level 3)

 Privilege level associated with a data segment is its “classification”

 Privilege level associated with a program segment is its “clearance”

 An executing program may only access data segments for which its
clearance level is lower than or equal to the privilege level of the
data segment

 The privilege mechanism also limits the use of certain instructions

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 Table 8.5
x86 Memory Management Parameters (page 1 of 2)

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 Table 8.5
x86 Memory Management Parameters (page 2 of 2)

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+ Paging
 Segmentation may be disabled
 In which case linear address space is used

 Two level page table lookup

 First, page directory
 1024 entries max
 Splits 4 Gbyte linear memory into 1024 page groups of 4
Mbyte
 Each page table has 1024 entries corresponding to 4
Kbyte pages
 Can use one page directory for all processes, one per
process or mixture
 Page directory for current process always in memory
 Use TLB holding 32 page table entries
 Two page sizes available, 4k or 4M
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+
Virtual Memory Address Translation

 The ARM supports memory  Sections and supersections are supported

access based on either sections to allow mapping of a large region of
or pages
memory while using only a single entry in
 Supersections (optional) the TLB
 Consist of 16-MB blocks of
main memory  The translation table held in main memory
has two levels:
 Sections
 First-level table
 Consist of 1-MB blocks of main
memory  Holds section and supersection
translations, and pointers to second-
 Large pages level table
 Consist of 64-kB blocks of main  Second-level tables
memory
 Hold both large and small page
 Small pages translations
 Consist of 4-kB blocks of main
memory
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+ Access Control
 The AP access control bits in each table entry control access to a region of
memory by a given process

 A region of memory can be designated as:

 No access
 Read only
 Read-write

 The region can be privileged access only, reserved for use by the OS and
not by applications

 ARM employs the concept of a domain:

 Collection of sections and/or pages that have particular access permissions
 The ARM architecture supports 16 domains
 Allows multiple processes to use the same translation tables while maintaining some
protection from each other

 Two kinds of domain access are supported:

 Clients
 Users of domains that must observe the access permissions of the individual
sections and/or pages that make up that domain
 Managers
 Control the behavior of the domain and bypass the access permissions for table
entries in that domain

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+ Summary Operating System
Support
Chapter 8
 Memory management
 Operating system overview  Swapping
 Operating system  Partitioning
objectives and functions
 Paging
 Types of operating systems
 Virtual memory
 Scheduling
 Translation lookaside buffer
 Long-term scheduling
 Segmentation
 Medium-term scheduling
 ARM memory management
 Short-term scheduling
 Memory system
 Intel x86 memory
organization
management
 Virtual memory address
 Address space
translation
 Segmentation  Memory-management
 paging formats
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