Fly-By DMA Controller

Data does not pass 8237 contains four DMA

through and is not channels
stored in DMA chip • Programmed
• DMA only between independently
I/O port and memory Can do memory to • Any one active
• Not between two memory via register • Numbered 0, 1, 2, and
I/O ports or two 3
memory locations

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 Table 7.2

Intel
8237A
Registers

E/D = enable/disable
TC = terminal count

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Direct Cache Access (DCA)
• DMA is not able to scale to meet the increased
demand due to dramatic increases in data rates for
network I/O
• Demand is coming primarily from the widespread
deployment of 10-Gbps and 100-Gbps Ethernet
switches to handle massive amounts of data transfer to
and from database servers and other high-
performance systems
• Another source of traffic comes from Wi-Fi in the
gigabit range
• Network Wi-Fi devices that handle 3.2 Gbps and 6.76
Gbps are becoming widely available and producing
demand on enterprise systems
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Cache-Related Performance
Issues
Network traffic is transmitted in the form of a sequence of protocol blocks called packets or protocol
data units

The lowest, or link, level protocol is typically Ethernet, so that each arriving and departing block
of data consists of an Ethernet packet containing as payload the higher-level protocol packet

The higher-level protocols are usually the Internet Protocol (IP), operating on top of Ethernet
and the Transmission Control Protocol (TCP), operating on top of IP

The Ethernet payload consists of a block of data with a TCP header and an IP header

For outgoing data, Ethernet packets are formed in a peripheral component, such as in I/O
controller or network interface controller (NIC)

For incoming traffic, the I/O controller strips off the Ethernet information and delivers the TCP/IP packet
to the host CPU

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Cache-Related Performance Issues

In a DMA scheme, when an

application wishes to transmit data,
it places that data in an application-
assigned buffer in main memory
• The core transfers this to a system buffer in
main memory and creates the necessary
TCP and IP headers, which are also buffered
For both outgoing in system memory
• The packet is then picked up via DMA for
and incoming transfer via the NIC
• This activity engages not only main memory
traffic the core, but also the cache
• Similar transfers between system and
main memory, and application buffers are required for
incoming traffic
cache are all
involved
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Packet Traffic Steps:
Incoming
Outgoing
• Packet arrives
• Packet transfer
• DMA requested
• NIC interrupts host • Packet created
• Retrieve descriptors • Output operation
and headers invoked
• Cache miss occurs • DMA transfer
• Header is processed • NIC signals completion
• Payload transferred • Driver frees buffer
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Direct Cache Access Strategies

Simplest strategy was implemented as a prototype on a

number of Intel Xeon processors between 2006 and 2010
The DCA function in the memory controller
This form of DCA applies only to incoming This enables the core to prefetch the data
sends a prefetch hint to the core as soon as
network traffic packet from the system buffer
the data is available in system memory

Much more substantial gains can be realized by avoiding

the system buffer in main memory altogether
The packet and packet For incoming packets, the
Implemented in Intel’s
descriptor information core reads the data from It has no need to access
Xeon processor line,
are accessed only once in the buffer and transfers that data in the system Cache injection
referred to as Direct Data
the system buffer by the the packet payload to an buffer again
I/O
core application buffer

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 Evolution of the I/O
Function
1. The CPU directly controls
4. The I/O module is given direct access
a peripheral device. to memory via DMA. It can now move
2. A controller or I/O a block of data to or from memory
module is added. The without involving the CPU, except at
CPU uses programmed the beginning and end of the transfer.
I/O without interrupts. 5. The I/O module is enhanced to
3. Same configuration as in become a processor in its own right,
with a specialized instruction set
step 2 is used, but now
tailored for I/O
interrupts are employed.
The CPU need not spend 6. The I/O module has a local memory of
time waiting for an I/O its own and is, in fact, a computer in its
operation to be own right. With this architecture a
performed, thus large set of I/O devices can be
increasing efficiency. controlled with minimal CPU
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Universal Serial Bus
• Widely used for peripheral connections
(USB)
• Is the default interface for slower speed devices
• Commonly used high-speed I/O
• Has gone through multiple generations
• USB 1.0
• Defined a Low Speed data rate of 1.5 Mbps and a Full Speed rate of 12 Mbps
• USB 2.0
• Provides a data rate of 480 Mbps
• USB 3.0
• Higher speed bus called SuperSpeed in parallel with the USB 2.0 bus
• Signaling speed of SuperSpeed is 5 Gbps, but due to signaling overhead the
usable data rate is up to 4 Gbps
• USB 3.1
• Includes a faster transfer mode called SuperSpeed+
• This transfer mode achieves a signaling rate of 10 Gbps and a theoretical
usable data rate of 9.7 Gbps
• Is controlled by a root host controller which attaches to devices
to create a local network with a hierarchical tree topology
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FireWire Serial Bus
• Was developed as an alternative to small computer system
interface (SCSI) to be used on smaller systems, such as personal
computers, workstations, and servers
• Objective was to meet the increasing demands for high I/O rates
while avoiding the bulky and expensive I/O channel technologies
developed for mainframe and supercomputer systems
• IEEE standard 1394, for a High Performance Serial Bus
• Uses a daisy chain configuration, with up to 63 devices connected
off a single port
• 1022 FireWire buses can be interconnected using bridges
• Provides for hot plugging which makes it possible to connect and
disconnect peripherals without having to power the computer
system down or reconfigure the system
• Provides for automatic configuration
• No terminations and the system automatically performs a
configuration function to assign addresses
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SCSI
• Small Computer System Interface
• A once common standard for connecting peripheral devices
to small and medium-sized computers
• Has lost popularity to USB and FireWire in smaller systems
• High-speed versions remain popular for mass memory
support on enterprise systems
• Physical organization is a shared bus, which can support up
to 16 or 32 devices, depending on the generation of the
standard
• The bus provides for parallel transmission rather than serial,
with a bus width of 16 bits on earlier generations and 32 bits
on later generations
• Speeds range from 5 Mbps on the original SCSI-1
specification to 160 Mbps on SCSI-3 U3

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+
Thunderbolt
• Most recent and fastest peripheral
connection technology to become
available for general-purpose use
• Developed by Intel with
collaboration from Apple
• The technology combines data,
video, audio, and power into a • Provides up to 10 Gbps
single high-speed connection for throughput in each direction and
peripherals such as hard drives, up to 10 Watts of power to
RAID arrays, video-capture boxes, connected peripherals
and network interfaces

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d.
InfiniBand
• I/O specification aimed at the high-end server market
• First version was released in early 2001
• Heavily relied on by IBM zEnterprise series of mainframes
• Standard describes an architecture and specifications for
data flow among processors and intelligent I/O devices
• Has become a popular interface for storage area
networking and other large storage configurations
• Enables servers, remote storage, and other network devices
to be attached in a central fabric of switches and links
• The switch-based architecture can connect up to 64,000
servers, storage systems, and networking devices

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 SATA
PCI Express
• Serial Advanced
• High-speed bus Technology Attachment
system for connecting • An interface for disk
peripherals of a wide storage systems
variety of types and • Provides data rates of up
speeds to 6 Gbps, with a
maximum per device of
300 Mbps
• Widely used in desktop
computers and in
industrial and embedded
applications

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Ethernet
• Predominant wired
networking technology
• Has evolved to support data • Has moved from bus-
rates up to 100 Gbps and based to switch-based
distances from a few meters • Data rate has
to tens of km periodically increased by
• Has become essential for an order of magnitude
supporting personal • There is a central switch
computers, workstations, with all of the devices
servers, and massive data connected directly to
storage devices in the switch
organizations large and small
• Ethernet systems are
• Began as an experimental
currently available at speeds
bus-based 3-Mbps system
up to 100 Gbps

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 Wi-Fi • As the technology of
antennas, wireless
• Is the predominant wireless transmission
Internet access technology
techniques, and
• Now connects computers,
tablets, smart phones, and wireless protocol
other electronic devices such design has evolved,
as video cameras TVs and the IEEE 802.11
thermostats
committee has been
• In the enterprise has become
an essential means of
able to introduce
enhancing worker productivity standards for new
and network effectiveness versions of Wi-Fi at
• Public hotspots have higher speeds
expanded dramatically to
provide free Internet access in • Current version is
most public places 802.11ac (2014) with a
maximum data rate of
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 Figure 7.20
IBM zEC12 I/O Frames-Front View

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 Summary
Chapter 7 Input/Output
• Interrupt-driven I/O
• External devices • Interrupt processing
• Keyboard/monitor • Design issues
• Disk drive • Intel 82C59A interrupt controller
• I/O modules • Intel 82C55A programmable
• Module function peripheral interface
• I/O module structure • Direct Cache Access
• Programmed I/O • DMA using shared last-level
cache
• Overview of programmed I/O
• Cache-related performance
• I/O commands/instructions issues
• Direct memory access • Direct cache access strategies
• Drawbacks of programmed and • Direct data I/O
interrupt-driven I/O • I/O channels and processors
• DMA function • The evolution of the I/O function
• Intel 8237A DMA controller • Characteristics
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