Mizan-Tepi University

School of Computing and Informatics

Department of Software Engineering

Chapter-6

Central Processing Unit (CPU)

By:
Melkamu D. (M.Sc)

Jun, 2023
MTU, Ethiopia
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Outline/contents
 Introduction
 General Register Organization
 Stack Organization
 Instruction Formats
 Addressing Modes
 Data Transfer and Manipulation
 Program Control
 Characteristics of RISC and CISC
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Introduction
 CPU stands for Central Processing Unit.
 It is the soul or brain of a computer system .
 The CPU along with the memory and the I/O sub-systems establish a strong computer
system.
 A CPU includes small layers of hundreds of transistors.
 Transistors are microscopic bits of substances that block electricity at one voltage (non-
conductor) and enable electricity to move through them at multiple voltages (conductor).
 These slight bits of substantial are the semiconductors that create two electronic inputs and
create multiple outputs when one or both inputs are turned on.
 CPU is the most significant in a computer system.
 It is the component that regulates all internal and external devices and implements
arithmetic and logic operations to perform the set of instructions saved in the computer’s
memory.
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Cont.….
 CPU is made up of three major parts:
 The register set: stores intermediate data used during the execution of the
instructions.
 The Arithmetic and Logic unit (ALU): performs the required micro-operations
for executing the instructions.
 The control unit: supervises the transfer of information among the registers and
instructs the arithmetic and logic units as to which operation to perform.
 The CPU performs a variety of functions dictated by the type of instructions that
are incorporated in the computer.
 Computer architecture is sometimes defined as the computer structure and
behavior as seen by the programmer that uses machine language instructions.
 This includes the instruction formats, addressing modes, the instruction sets
and the general organizations of the CPU registers
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Major Components of CPU

 Storage Components:
 Registers
 Flip-flops
 Execution (Processing) Components:
 Arithmetic Logic Unit (ALU):
 Arithmetic calculations
 Logical computations
 Shifts/Rotates
 Transfer Components:
 Bus
 Control Components:
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General Register Organization

 Bus organization for 7 CPU registers: Clock
Input

 2 MUX: select one of 7 register or external data input

R1
by SELA and SELB. R2
 BUS A and BUS B : form the inputs to a common ALU. R3
R4
 ALU : OPR determine the arithmetic or R5
R6
logic microoperation. The result of the microoperation is R7
available for external data output and also goes into the inputs Load
(7 lines)
of all registers. SELA{ MUX MUX }SELB
 3 X 8 Decoder: select the register (by SELD) that
3x8
A bus B bus
decoder
receives the information from ALU
 An operation is selected by the ALU operation selector (OPR).
SELD
 The result of a microoperation is directed to a destination OPR ALU

register selected by a decoder (SELD).

 Control word: The 14 binary selection inputs Output
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Operation Of Control Unit (CU)

 The control unit directs the information flow through ALU by:
 Selecting various Components in the system
 Selecting the Function of ALU

Example1: R1  R2 + R3 3 3 3 5

Control Word SELA SELB SELD OPR

[1] MUX A selector (SELA): BUS A  R2

[2] MUX B selector (SELB): BUS B  R3 Binary
Code SELA SELB SELD
000 Input Input None
[3] ALU operation selector (OPR): ALU to ADD 001
010
R1
R2
R1
R2
R1
R2
011 R3 R3 R3
[4] Decoder destination selector (SELD): R1  Out Bus 100
101
R4
R5
R4
R5
R4
R5
110 R6 R6 R6
111 R7 R7 R7

Encoding of register selection fields

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Register Stack Organization

 Stack
 Very useful feature for
nested subroutines,
nested loops control.
 Also efficient for arithmetic
expression evaluation
 Storage which can be
accessed in LIFO.
 Pointer: SP
 Only PUSH and POP
operations are applicable.
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Memory Stack Organization

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Reverse Polish Notation

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Instruction Format
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Three, And Two-address Instructions

 Three-Address Instructions:
 Program to evaluate X = (A + B) * (C + D) :
ADD R1, A, B /* R1  M[A] + M[B] */
ADD R2, C, D /* R2  M[C] + M[D] */
MUL X, R1, R2 /* M[X]  R1 * R2 */
- Results in short programs
- Instruction becomes long (many bits)
 Two-Address Instructions:
 Program to evaluate X = (A + B) * (C + D) :
MOV R1, A /* R1  M[A] */
ADD R1, B /* R1  R1 + M[B] */
MOV R2, C /* R2  M[C] */
ADD R2, D /* R2  R2 + M[D] */
MUL R1, R2 /* R1  R1 * R2 */
MOV X, R1 /* M[X]  R1 */
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One, And Zero-address Instructions

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Addressing Modes
 Addressing Modes:

 Specifies a rule for interpreting or modifying the address field of the

instruction (before the operand is actually referenced).
 Variety of addressing modes:

 To give programming flexibility to the user.

 To use the bits in the address field of the instruction efficiently.
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Types Of Addressing Modes

 Implied Mode
 Address of the operands are specified implicitly in the definition of the
instruction.
- No need to specify address in the instruction
- EA = AC, or EA = Stack[SP], EA: Effective Address.
 Immediate Mode
 Instead of specifying the address of the operand, operand itself is specified.
-No need to specify address in the instruction
-However, operand itself needs to be specified
-Sometimes, require more bits than the address
-Fast to acquire an operand
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Cont.……
 Register Mode
 Address specified in the instruction is the register address.
- Designated operand need to be in a register
- Shorter address than the memory address
- Saving address field in the instruction
- Faster to acquire an operand than the memory addressing
- EA = IR(R) (IR(R): Register field of IR)
 Register Indirect Mode
 Instruction specifies a register which contains the memory address of the operand.
-Saving instruction bits since register address is shorter than the memory address.
-Slower to acquire an operand than both the register addressing or memory addressing.
- EA = [IR(R)] ([x]: Content of x)
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Cont.….
 Auto-increment or Auto-decrement features: Same as the Register Indirect, but: When the
address in the register is used to access memory, the value in the register is incremented or
decremented by 1 (after or before the execution of the instruction).
 Direct Address Mode: Instruction specifies the memory address which can be used directly to
the physical memory.
- Faster than the other memory addressing modes
- Too many bits are needed to specify the address for a large physical memory space
- EA = IR(address), (IR(address): address field of IR)
 Indirect Addressing Mode: The address field of an instruction specifies the address of a
memory location that contains the address of the operand
-When the abbreviated address is used, large physical memory can be addressed with a
relatively small number of bits
-Slow to acquire an operand because of an additional memory access
-EA = M[IR(address)]
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Cont…
 Relative Addressing Modes:
The Address fields of an instruction specifies the part of the address (abbreviated address)
which can be used along with a designated register to calculate the address of the operand.
PC Relative Addressing Mode(R = PC)
- EA = PC + IR(address)
- Address field of the instruction is short.
- Large physical memory can be accessed with a small number of address bits.
 Indexed Addressing Mode:
XR: Index Register:
- EA = XR + IR(address)
 Base Register Addressing Mode:
BAR: Base Address Register:
- EA = BAR + IR(address)
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Addressing Modes - Examples

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Data Transfer Instructions

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Data Manipulation Instructions

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Program Control Instructions

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Conditional Branch Instructions

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Program Interrupt
 Types of Interrupts:
 External interrupts
 External Interrupts initiated from the outside of CPU and Memory
 I/O Device -> Data transfer request or Data transfer complete
 Timing Device -> Timeout
 Power Failure
 Internal interrupts (traps)
 Internal Interrupts are caused by the currently running program
 Register, Stack Overflow
 Divide by zero
 OP-code Violation
 Protection Violation
 Software Interrupts
Both External and Internal Interrupts are initiated by the computer Hardware.
Software Interrupts are initiated by executing an instruction.
- Supervisor Call -> Switching from a user mode to the supervisor mode
-> Allows to execute a certain class of operations which are not allowed in the user mode
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RISC (Reduced Instruction Set Computers) Processor

 RISC stands for Reduced Instruction Set Computer Processor, a microprocessor architecture
with a simple collection and highly customized set of instructions.
 It is built to minimize the instruction execution time by optimizing and limiting the number of
instructions.
 It means each instruction cycle requires only one clock cycle, and each cycle contains three
parameters: fetch, decode and execute.
 The RISC processor is also used to perform various complex instructions by combining them into
simpler ones.
 RISC chips require several transistors, making it cheaper to design and reduce the execution time for
instruction.
 Examples of RISC processors are: SUN's SPARC, PowerPC, Microchip PIC processors, RISC-V.
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Cont.….
Advantages of RISC Processor
1. The RISC processor's performance is better due to the simple and limited number of the instruction set.
2. It requires several transistors that make it cheaper to design.
3. RISC allows the instruction to use free space on a microprocessor because of its simplicity.
4. RISC processor is simpler than a CISC processor because of its simple and quick design, and it can
complete its work in one clock cycle.

Disadvantages of RISC Processor

1. The RISC processor's performance may vary according to the code executed because subsequent
instructions may depend on the previous instruction for their execution in a cycle.
2. Programmers and compilers often use complex instructions.
3. RISC processors require very fast memory to save various instructions that require a large
collection of cache memory to respond to the instruction in a short time.
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Cont.…
RISC Architecture

It is a highly customized set of instructions used in portable devices due to

system reliability such as Apple iPod, mobiles/smartphones, Nintendo DS,
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CISC (Complex Instruction Set Computers)
Processor
 The CISC Stands for Complex Instruction Set Computer, developed by the Intel.
 It has a large collection of complex instructions that range from simple to very
complex and specialized in the assembly language level, which takes a long time
to execute the instructions. So, CISC approaches reducing the number of
instruction on each program and ignoring the number of cycles per instruction.
 It emphasizes to build complex instructions directly in the hardware because the
hardware is always faster than software.
 However, CISC chips are relatively slower as compared to RISC chips but use
little instruction than RISC.
 Examples of CISC processors are: VAX, AMD, Intel x86 and the System/360.
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Characteristics of CISC Processor

 Following are the main characteristics of the RISC processor:
 The length of the code is shorts, so it requires very little RAM.
 CISC or complex instructions may take longer than a single clock cycle to
execute the code.
 Less instruction is needed to write an application.
 It provides easier programming in assembly language.
 Support for complex data structure and easy compilation of high-level languages.
 It is composed of fewer registers and more addressing nodes, typically 5 to 20.
 Instructions can be larger than a single word.
 It emphasizes the building of instruction on hardware because it is faster to create
than the software.
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CISC Processors Architecture

 The CISC architecture helps reduce program code by embedding multiple operations on
each program instruction, which makes the CISC processor more complex.
 The CISC architecture-based computer is designed to decrease memory costs because
large programs or instruction required large memory space to store the data, thus
increasing the memory requirement, and a large collection of memory increases the
memory cost, which makes them more expensive.
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Cont.…
 Advantages of CISC Processors
1. The compiler requires little effort to translate high-level programs or statement languages into assembly or machine
language in CISC processors.
2. The code length is quite short, which minimizes the memory requirement.
3. To store the instruction on each CISC, it requires very less RAM.
4. Execution of a single instruction requires several low-level tasks.
5. CISC creates a process to manage power usage that adjusts clock speed and voltage.
6. It uses fewer instructions set to perform the same instruction as the RISC.

 Disadvantages of CISC Processors

1. CISC chips are slower than RSIC chips to execute per instruction cycle on each program.
2. The performance of the machine decreases due to the slowness of the clock speed.
3. Executing the pipeline in the CISC processor makes it complicated to use.
4. The CISC chips require more transistors as compared to RISC design.
5. In CISC it uses only 20% of existing instructions in a programming event.
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Difference Between the RISC and CISC Processors

RISC CISC

It is a Reduced Instruction Set Computer. It is a Complex Instruction Set

Computer.
It emphasizes on software to optimize the It emphasizes on hardware to
instruction set. optimize the instruction set.
It is a hard wired unit of programming in the Microprogramming unit in CISC
RISC Processor. Processor.
It requires multiple register sets to store the It requires a single register set to store
instruction. the instruction.
RISC has simple decoding of instruction. CISC has complex decoding of
instruction.
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Cont.…
Uses of the pipeline are simple in RISC. Uses of the pipeline are difficult in
CISC.
It uses a limited number of instruction that It uses a large number of instruction
requires less time to execute the instructions. that requires more time to execute the
instructions.
It uses LOAD and STORE that are It uses LOAD and STORE instruction
independent instructions in the register-to- in the memory-to-memory interaction
register a program's interaction. of a program.

RISC has more transistors on memory CISC has transistors to store complex
registers. instructions.

The execution time of RISC is very short. The execution time of CISC is longer.
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Cont.…
RISC RISC
architecture can be used
architecture canwithbehigh-end applications
used with like telecommunication,
high-end CISC architecture image can
processing,
be used videowith
processing, etc.
applications like telecommunication, image low-end applications like home
CISC architecture can be used with low-end applications like home automation, security system, etc.
processing, video processing, etc. automation, security system, etc.
It has fixed format instruction.

It has fixed format instruction. It has variable format instruction.

The program written for RISC architecture Program written for CISC architecture
needs to take more space in memory. tends to take less space in memory.

Example of RISC: ARM, PA-RISC, Power Examples of CISC: VAX, Motorola

Architecture, Alpha, AVR, ARC and the 68000 family, System/360, AMD and
SPARC. the Intel x86 CPUs.
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End of chapter Six

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