Digital

UNIT- I Design
Using
Verilog
Adopted from
T. R. Padmanabhan and B. Bala Tripura
Sundari,
Design through Verilog HDL –Wiley, 2009.

Prepared BY
D. Khalandar Basha
Assoc Prof., IARE
 Un i t - I

Unit - I
INTRODUCTION TO VERILOG:
o Verilogas HDL
o Levels of design Description
o Concurrency
o Simulation and Synthesis
o Functional Verification
o System Tasks
o Programming Language Interface (PLI)
o Module
o Simulation and Synthesis Tools
o Test Benches.

LANGUAGE CONSTRUCTS AND CONVENTIONS:

o Introduction, Keywords, Identifiers, White Space Characters, Comments,
o Numbers
o Strings
o Logic Values
o Strengths
o Data Types
o Scalars and Vectors
o Parameters
o Operators.
 Un i t - I

Objectives and Outcomes

Objective: To make the student learn and understand

H

o Acquire abasic knowledge of the Verilog HDL

I ARE ,

o Language constructs and conventions in Verilog

o Basic Concepts of Verilog HDL like Data Types, System Tasks and
B ash a ,

Compiler Directives.

Outcomes: The student will be able to

Khal andar

o Define basic terms in HDL

o Knows Syntax and lexical conventions
o Remembers Data types, operators
Remember testbenches for simulation and verification
D .

o
B y
Prepared
Y D .
 VERILOG AS AN HDL

o Verilog aimed at providing a functionally tested and a verified

H
I ARE ,

design description for the target FPGA or ASIC.

B ash a ,
Khal andar
D .
B y
Prepared
Y D .
 LEVELS OF DESIGN DESCRIPTION
H

Gate Level
I ARE ,
B ash a ,

Data Flow
Khal andar

Behavioral
Level

Circuit
D .

Level or
B y

switch level
Prepared
Y D .
Circuit Level or switch level

o At the circuit level, a switch is the basic element

with which digital circuits are built.

o Switches can be combined to form inverters and other gates at

the next higher level of abstraction.
Gate Level

o At the next higher level of abstraction,

design is carried out in terms of basic gates.
o All the basic gates are available as ready modules
called “Primitives”.
Data Flow

o Data flow is the next higher level of abstraction.

o All possible operations on signals and variables are

represented here in terms of assignments

y = (ab+cd)
Behavioral Level

o Behavioral level constitutes the highest level of design

description; it is essentially at the system level itself.

o With the assignment possibilities, looping constructs

and conditional branching possible, the design
description essentially looks like a “C” program.
Verilog Language Concepts

o Concurrency
o Simulation and Synthesis
o Functional Verification
o System Tasks
o Programming Language Interface (PLI)
 Concurrency

o In an electronic circuit all the units are to be active and

H

functioning concurrently. The voltages and currents in the

I ARE ,

different elements in the circuit can change simultaneously. In

B ash a ,

turn the logic levels too can change.

o Simulation of such a circuit in an HDL calls for concurrency

Khal andar

of operation.

o All the activities scheduled at one time step are completed and
D .

then the simulator.

B y
Prepared
Y D .
 Simulation and
Synthesis
o The design that is specified and entered as described earlier is
H
I ARE ,

simulated for functionality and fully debugged.

o Translation of the debugged design into the corresponding
B ash a ,

hardware circuit (using an FPGA or an ASIC) is called

Khal andar

“synthesis.”
o The circuits realized from them are essentially direct
translations of functions into circuit elements.
D .
B y
Prepared
Y D .
 Functional Verification

Testing is an essential ingredient of the VLSI design process as

H

o
I ARE ,

with any hardware circuit.

o It has two dimensions to it – functional tests and timing tests.
B ash a ,

o Testing or functional verification is carried out by setting up a

“test bench” for the design.
Khal andar
D .
B y
Prepared
Y D .
 System Tasks

o A number of system tasks are available in Verilog.

H

o Though used in a design description, they are not part of it.

I ARE ,

o Some tasks facilitate control and flow of the testing process.

o A set of system functions add to the flexibility of test benches:
B ash a ,

They are of three categories:

> Functions that keep track of the progress of simulation time
Khal andar

>Functions to convert data or values of variables from one

format to another
> Functions to generate random numbers with specific
distributions.
D .

o There are other numerous system tasks and functions

B y
Prepared
Y D .
 Programming Language Interface
(PLI)
o Programming Language Interface (PLI) is away to provide
H
I ARE ,

Application Program Interface (API) toVerilog HDL.

Essentially it is a mechanism to invoke a C function from a

B ash a ,

Verilog code.
Khal andar

o PLI is primarily used for doing the things which would not
have been possible otherwise using Verilog syntax.
D .
B y
Prepared
Y D .
 MODULE

o Any Verilog program begins with a keyword – called a

H

“module.”
I ARE ,

o A module is the name given to any system considering it as a

blackbox with input and output terminals as shown in Figure
B ash a ,

o The terminals of the module are referred to as ‘ports ’.

Khal andar
D .
B y
Prepared
Y D .
 Cont …

o The ports attached to a module can be of three types:

H
I ARE ,

> input ports through which one gets entry into the module
> output ports through which one exits the module.
B ash a ,

> inout ports: These represent ports through which one gets entry into the
module or exits the module
Khal andar

o All the constructs in Verilog are centred on the module.

D .
B y
Prepared
Y D .
 MODULE SYNTAX

o module module_name (port_list);

H
I ARE ,

Input, output, inout declaration

Intermediate variable declarations
B ash a ,

Functional Description
Khal andar

(gate / switch / data flow / Behv.)

endmodule
D .
B y
Prepared
Y D .
 SIMULATION AND SYNTHESIS TOOLS

o A variety of Software tools related to VLSI design is available.

H
I ARE ,

o Two of them are

- Modelsim and
B ash a ,

- Leonardo Spectrum of MentorGraphics.

Khal andar

o Modelsim has been used to simulate the designs.

o Leonardo Spectrum has been used to obtain the synthesized

circuits
D .
B y
Prepared
Y D .
 TEST BENCH SYNTAX

o Atest bench is HDL code that allows you to provide a

H

documented, repeatable set of stimuli.

I ARE ,

o module tb_module_name ;
B ash a ,

Input, output, inout declaration

Khal andar

Intermediate variable declarations

Stimulus (initial / always)

D .
B y

endmodule
Prepared
Y D .
 LANGUAGE CONSTRUCTS AND
CONVENTIONS IN VERILOG
o CASE SENSITIVITY
H
I ARE ,

Verilog is a case-sensitive language like C

o KEYWORDS
B ash a ,

o The keywords define the language constructs. A keyword

signifies an activity to be carried out, initiated, or terminated
Khal andar

o All keywords in Verilog are in small letters

D .
B y
Prepared
Y D .
 IDENTIFIERS

o IDENTIFIERS
H
I ARE ,

o Any program requires blocks of statements, signals, etc., to

be identified with an attached nametag. Such nametags are
B ash a ,

identifiers

All characters of the alphabet or an underscore can be used

Khal andar

o
as the first character. Subsequent characters can be of

alphanumeric type, or the underscore (_), or the dollar ($)

D .

sign
B y
Prepared
Y D .
 WHITE SPACE CHARACTERS , COMMENTS

WHITE SPACE CHARACTERS

H

o
I ARE ,

o Blanks (\b), tabs (\t), newlines (\n), and form feed form the
B ash a ,

white space characters in Verilog

o COMMENTS
Khal andar

o A single line comment begins with “//”

o multiline comments “/*” signifies the beginning of a

comment and “ */” its end.
D .
B y
Prepared
Y D .
 NUMBERS, STRINGS

o NUMBERS
H

Integer Numbers : the number is taken as 32 bits wide.

I ARE ,

o 25, 253, –253

o - 8 'h f 4
B ash a ,

Real Numbers: Real numbers can be specified in decimal or

scientific notation
Khal andar

4.3, 4.3e2

o STRINGS : A string is a sequence of characters enclosed

D .

within double quotes

“This is a string”
B y

o
Prepared
Y D .
 LOGIC VALUES

o 1 signifies the 1 or high or true level

H
I ARE ,

o 0 signifies the 0 or low or false level.

o Two additional levels are also possible designated as x and z.
B ash a ,

o x represents an unknown or an uninitialized value. This corresponds to

the don’tcare case in logic circuits.
Khal andar

o z represents / signifies a high impedance state

D .
B y
Prepared
Y D .
 STRENGTHS
Declaration
Strength Name Strength Level Element Modelled
Abbreviation
H

Supply Drive 7 Power supply connections. supply

I ARE ,

Strong Drive 6 Default gate & assign output strong

strength.
B ash a ,

Pull Drive 5 Gate & assign output pull

strength.
Large Capacitor 4 Size of trireg net capacitor. large
Khal andar

Weak Capacitor 3 Gate & assign output weak

strength.
Medium 2 Size of trireg net capacitor. medium
D .

Capacitor
B y

Small Capacitor 1 Size of trireg net capacitor. small

Prepared

High Impedence 0 Not Applicable. highz

Y D .
 Data Types

o The data handled in Verilog fall into two categories:

H
I ARE ,

(i) Net data type

(ii) Variable data type
B ash a ,

o The two types differ in the way they are used as well as with
regard to theirrespective hardware structures.
Khal andar
D .
B y
Prepared
Y D .
 Net data type

A net signifies a connection from one circuit unit to another,

H

o
I ARE ,

which carries the value of the signal it is connected to and

transmits to the circuit blocks connected to it.
B ash a ,

o If the driving end of a net is left floating, the net goes to the
high impedance state.
Khal andar

o Various nets supported in Verilog

WIRE / TRI WAND / TRIAND
D .

WOR / TRIOR TRI1

TRI0 TRIREG -- Infers a capacitance
B y

SUPPLY1 -- For Vdd SUPPLY0 -- For Vss

Prepared
Y D .
 DIFFERENCES BETWEEN WIRE
AND TRI
wire: It represents a simple wire doing an interconnection.
H

o
I ARE ,

Only one output is connected to a wire and is driven by that.

B ash a ,

o tri: It represents a simple signal line as a wire. Unlike the wire,

atri can be driven by more than one signal outputs.
Khal andar
D .
B y
Prepared
Y D .
 Contention

WIR 0 1 X Z WAN 0 1 X Z
H

E D
I ARE ,

/TRI /
TRIAN
0 0 X X 0 D 0
1 X 1 X 1 0 0 0 0 1
B ash a ,

X X X X X 1
X 00 1X X X
X
Z 0 1 X Z Z 0 1 X Z
Khal andar

WOR 0 1 X Z TRI1( 0 1 X Z
/TRIO 0
R )
0 0 X X 0
0 0 1 X 0
D .

1
1 1 1 1 1 1 X 1 X
B y

X X X X
X X 1 X X X
Prepared

Z 0 1 X 1(0)
Z 0 1 X Z
Y D .
 Variable Data Type

o A variable is an abstraction for a storage device

H
I ARE ,

o reg
o time
o integer
B ash a ,

o real
o Realtime
Khal andar

o MEMORY
o Reg [15:0] memory[511:0];
o an array called “memory”; it has 512 locations.
D .
B y

oEach location is 16 bits wide

Prepared
Y D .
 Scalars and Vectors

Entities representing single bits — whether the bit is stored,

H

o
I ARE ,

changed, or transferred — are called “scalars.”

o Multiple lines carry signals in a cluster treated as a “vector.”
B ash a ,

reg[2:0] b;
reg[4:2] c;
Khal andar

wire[-2:2] d ;

o All the above declarations are vectors.

D .

If range is not specifies it is treated as scalars

B y

o
Prepared
Y D .
 Parameters,
Operators.
PARAMETERS
H

All constants can be declared as parameters at the outset

I ARE ,

in a Verilog module
o parameter word_size = 16;
B ash a ,

o parameter word_size = 16, mem_size = 256;

Khal andar

OPERATORS
o Unary: - for example, ~a.
o Binary: - for example, a&b.
D .

o Ternary: - for example, a?b:c

B y
Prepared
Y D .
 Digital
Design
Through
Verilog
Adopted from
T. R. Padmanabhan and B. Bala Tripura
Sundari,
Design through Verilog HDL –Wiley, 2009.

Prepared BY
D. Khalandar Basha
Assoc Prof., IARE
 Un i t - II

Unit - II

GATE LEVEL MODELING:

o Introduction
o AND Gate Primitive
o Module Structure
o Other Gate Primitives
o Illustrative Examples
o Tri-State Gates
o Array of Instances of Primitives
o Design of Flip - Flops with gate primitives
o Delays
o Strengths and Contention Resolution,
o Net Types
o Design of Ba sic Circuits.
MODELING AT DATA FLOW LEVEL:
o Introduction
o Continuous Assignment Structures
o Delays and Continuous Assignments
o Assignment to Vectors, Operators .
 Un i t - II

GATE LEVEL MODELING

o All the basic gates are available as “Primitives” in Verilog.

 Un i t - II

Verilog module for AOI logic

module
o
aoi_gate(o,a1,a2,b1,b2);
input a1,a2,b1,b2; output o;
wire o1,o2;
and g1(o1,a1,a2);
and g2(o2,b1,b2);
nor g3(o,o1,o2);
endmodule
o module aoi_st;
reg a1,a2,b1,b2;
wire o;
initial
begin b1 = 0; b2 = 0;
a1 = 0; a2 = 0;
#3 a1 = 1; a2 = 1; b1 = 1; b2 = 0;
end
initial #100 $stop;
initial $monitor($time , " o = %b , a1 = %b , a2 = %b , b1 = %b ,b2 = %b
",o,a1,a2,b1,b2);
aoi_gate gg(o,a1,a2,b1,b2);
endmodule
 Un i t - II

TRI-STATE GATES

o Four types of tri-state buffers are available in Verilog as

primitives
 Un i t - II

ARRAY OF INSTANCES OF PRIMITIVES

o and gate [7 : 4 ] (a,b, c);

o and gate [7] (a[3], b[3], c[3]),

gate [6] (a[2], b[2], c[2]),
gate [5] (a[1], b[1], c[1]),
gate [4] (a[0], b[0], c[0]);

Syntax: and gate[mm : nn](a, b, c);

 Un i t - II

DESIGN OF FLIP-FLOPS WITH GATE PRIMITIVES

o Simple Latch
module sbrbff(sb,rb,q,qb);
input sb,rb;
output q,qb;

nand(q,sb,qb);
nand(qb,rb,q);

endmodule
 Un i t - II

RS Flip-Flop module

o module srff(s,r,q,qb);

input s,r;
output q,qb;
wire ss,rr;

not(ss,s),(rr,r);
nand(q,ss,qb);
nand(qb,rr,q);

endmodule
 Un i t - II

A Clocked RS Flip-Flop
module
o module srffcplev(cp,s,r,q,qb);

input cp,s,r;
output q,qb;
wire ss,rr;

nand (ss,s,cp),
(rr,r,cp),
(q,ss,qb),
(qb,rr,q);
endmodule
 Un i t - II

D-Latch module

o module dlatch(en,d,q,qb);
input d,en;
output q,qb;
wire dd;
wire s,r;

not n1(dd,d);
nand (sb,d,en);
nand g2(rb,dd,en);
sbrbffff(sb,rb,q,qb);
endmodule
 Un i t - II

DELAYS

o Net Delay
wire #2 nn;
// nn is declared as a net with a propagation delay of 2
time steps
wire # (2, 1) nm;
//the positive (0 to 1) transition has a delay of 2 time steps
//The negative (1 to 0) transition has a delay of 1 time step

o Gate Delay
and #3 g( a,b, c);
and #(2, 1) g(a,b, c);
 Un i t - II

Delays with Tri-state Gates

 Un i t - II

min, typical, max delays

o and #(2:3:4) g1(a0, a1, a2);

// min,typical, max delays

o and #(1:2:3, 2:4:6) g2(b0, b1, b2);

o bufif1 #(1:2:3, 2:4:6, 3:6:9) g3 (a0, b0, c0);

o wire #(1:2:3) a;
 Un i t - II

STRENGTHS AND CONTENTION RESOLUTION

 Un i t - II

Net Charges

o net can have a capacitor associated with it, which can store the
signal level even after the
signal source dries up (i.e., tri-stated).

o Such nets are declared with the

o keyword trireg.
 Un i t - II

Signal strength names and weights

 Un i t - II

MODELING AT DATA FLOW LEVEL

o CONTINUOUS ASSIGNMENT STRUCTURES

assign c = a && b;

o Combining Assignment and Net Declarations

wire c;
assign c = a & b;
can be combined as
wire c = a & b;

o Continuous Assignments and Strengths

wire (pull1, strong0)g = ~g1;
 Un i t - II

Data flow module for AOI

o module aoi2(g, a, b, c, d);

output g;
input a, b, c, d;
wire e, f, g1, g;
assign e = a && b, f = c && d, g1 = e||f, g=~g1;
endmodule

o module aoi3(g, a, b, c, d);

output g;
input a, b, c, d;
wire g;
wire e = a && b;
wire f = c && d;
wire g1 = e | | f ;
assign g = ~g1;
endmodule
 Un i t - II

DELAYS AND CONCATENATION

DELAYS AND CONTINUOUS ASSIGNMENTS

o assign #2 c = a & b;

o wire #2 c;
o assign c = a & b;

CONCATENATION OF VECTORS
{a, b, c}
{a(7:4), b(2:0)}
{2{p}} = {p, p}
{2{p}, q} = {p,p, q}
{a, 3 {2{b , c}, d}} = {a,b, c,b, c, d,b, c,b, c, d,b, c,b, c, d }
 Un i t - II

OPERATORS
 Un i t - II

Unary Operators
 Un i t - II

Binary Operators

o Arithmetic operators and their symbols

o Binary logical operators and their symbols

o Relational operators and their symbols

 Un i t - II

Cont..

o Equality operators and their symbols

 Un i t - II

cont…

o Bit-wise logical operators and their symbols

o Shift type operators and their symbols

 Un i t - II

Ternary operator

oA ?B:C

o assign y = w ? x : z;

o Assign d = (f == add) ? (a+b) : ((f = sub) ? (a-b) :

((f==compl) ? ~a : ~b;
 Un i t - II

Operator Priority

o The table brings out the order of precedence. The order of

precedence decides the priority for sequence of execution and
circuit realization in any assignment
o statement.
 Digital
Design
Using
Verilog

Adopted from
Wiley,
T. R. Padmanabhan and B. Bala
Tripura Sundari, Design through
Verilog HDL – 2009.

Prepared by
D. Khalandar Basha
Assoc Prof., IARE
UNIT -
III
o BEHAVIORAL MODELING:
• Introduction
• Operations and Assignments
• Functional Bifurcation
• Initial Construct, Always Construct
• Assignments with Delays Wait Construct
• Multiple Always Blocks
• Designs at Behavioral Level
• Blocking and Non-Blocking Assignments
• The case statement
• Simulation Flow
• if and if-else constructs
• assign-deassign construct, repeat construct,for loop, the disable construct,
while loop,forever loop, parallel blocks,force-release construct, Event.
BEHAVIORAL MODELING

BEHAVIORAL MODELING
o Behavioral level modeling constitutes design
description at an abstract level.
o One can visualize the circuit in terms of its key
modular functions and their behavior; it can be
described at a functional level itself instead of
getting bogged down with implementation details.
OPERATIONS AND ASSIGNMENTS
o The design description at the behavioral level is done
through a sequence of assignments.

o These are called ‘procedural assignments’ – in contrast to

the continuous assignments at the data flow level.

o All the procedural assignments are executed sequentially

in the same order as they appear in the design
description.
FUNCTIONAL BIFURCATION
• Design description at the behavioral level is done in
terms of procedures of two types;
• one involves functional description and interlinks of
functional units. It is carried out through a series of
blocks under an “always”.
• The second concerns simulation – its starting point,
steering the simulation flow, observing the process
variables, and stopping of the simulation process; all
these can be carried out under the “always” banner, an
“initial” banner, or their combinations.
procedure-block structure
o A procedure-block of either type - initial or always
- can have a structure shown in Figure
BEGIN - END CONSTRUCT
o If a procedural block has only one assignment to be
carried out, it can be specified
o as initial #2 a=0;

o More than one procedural assignment is to be carried out

in an initial block. All such
o assignments are grouped together between “begin” and
“end” declarations.
o Every begin declaration must have its associated end
declaration.
o begin – end constructs can be nested as many times as
desired.
NESTED BEGIN – END
BLOCKS
INITIAL CONSTRUCT

• A set of procedural assignments within an initial construct are

executed only Once

• In any assignment statement the left-hand side has to be a storage

type of element (and not a net). It can be areg, integer, or real type
of variable. The right-hand side can be a storage type of variable or
anet.
o initial
o begin
o a = 1'b0;
o b = 1'b0;
o #2 a = 1'b1;
o #3 b = 1'b1;
o #100$stop;
o end
MULTIPLE INITIAL BLOCKS
o module nil1;
o initial
o
reg a, b;
o
begin
o
a = 1'b0; b = 1'b0;
$display ($time, "display : a = %b, b = %b", a, b);
o
#2 a = 1'b1;
o
o
end
initial #100$stop;
o
initial
o
begin #2 b = 1'b1;
o
end
o

o endmodule
ALWAYS CONSTRUCT
o The always process signifies activities to be executed on
an “always basis.”
o Its essential characteristics are:
• Any behavioral level design description is done using an
always block.
• The process has to be flagged off by an event or a
change in a net or areg. Otherwise it ends in a stalemate.
• The process can have one assignment statement or
multiple assignment statements.
• Normally the statements are executed sequentially in the
order they appear.
EVENT CONTROL
oThe always block is executed repeatedly and endlessly. It
is necessary to specify a condition or a set of conditions,
which will steer the system to the execution of the block.
Alternately such a flagging-off can be done by
specifying an event preceded by the symbol “@”.
o @(negedge clk) :executes the following block at the negative edge of clk.
o @(posedgeclk) : executes the following block at the positive edge of the
clk.
o @clk : executes the following block at both the edges of clk.
o @(prtor clr) :
o @(posedgeclk1 ornegedge clk2) :
o @ (a or b or c) can also write as @ (a or b or c) @ (a,b, c) @ (a, b or
c)
 EXAMPLE
COUNTER
o module counterup(a,clk,N);
input clk;
input[3:0]N;
output[3:0]a;

reg[3:0]a;

initial a=4'b0000;
always@(negedge clk) a=(a==N)?4'b0000:a+1'b1;

o endmodule
ASSIGNMENTS WITH DELAYS
o always #3 b = a;
o Values of a at the 3rd, 6th, 9th, etc., ns are sampled and assigned to
b.
o Initial
o begin
o a = 1’b1;
o b = 1’b0;
o #1 a = 1’b0;
o #3 a = 1’b1;
o #1 a = 1’b0;
o #2 a = 1’b1;
o #3 a = 1’b0;
o end
INTRA-ASSIGNMENT DELAYS
o The “intra-assignment” delay carries out the assignment
in two parts.
o An assignment with an intra-assignment has the form
o A = # dl expression;
o Here the expression is scheduled to be evaluated as soon
as it is encountered.
o However, the result of the evaluation is assigned to the
right-hand side quantity a after a delay specified by dl.
o dl can be an integer or a constant expression
o always #2 a = a + 1;
o always #b a = a + 1;
o always #(b + c) a = a + 1;
ZERO DELAY
o Adelay of 0 ns does not really cause any delay.
o However, it ensures that the assignment following is
executed last in the concerned time slot.

o always
o begin a = 1;
o #0 a = 0;
o end
WAIT CONSTRUCT
o The wait construct makes the simulator wait for the
specified expression to be true before proceeding with
the following assignment or group of assignments.
o Its syntax has the form
o wait (alpha) assignment1;
o alpha can be a variable, the value on a net, or an
expression involving them.
o @clk a = b; assigns the value of b to a when clk changes;
o wait (clk) #2 a = b; the simulator waits for the clock to
be high and then assigns b to a
BLOCKING AND NONBLOCKING ASSIGNMENTS

o All assignment within an initial or an always block done

through an equality (“=”) operator. These are executed
sequentially. Such assignments block the execution of the
following lot of assignments at any time step. Hence they are
called “blocking assignments” .

o If the assignments are to be effected concurrently A facility

called the “nonblocking assignment” is available for such
situations. The symbol “ < = ” signifies a non- blocking
assignment. The main characteristic of a nonblocking
assignment is that its execution is concurrent
CONT…

o For all the non-blocking assignments in a block, the

right-hand sides are evaluated first. Subsequently the
specified assignments are scheduled.

What will happen if the following statements are

o
executed
o A <= B; // A, B will swapped
o B <= A ;

o And
o A = B;
oB=A; // A, B will have same value
NONBLOCKING ASSIGNMENTS AND DELAYS
o The principle of Delays of the intra-assignment type operation is
similar to that with blocking assignments.
o always @ ( a orb)
o #3 c1 = a&b;
o which has a delay of 3 ns for the blocking assignment to c1. If a orb
changes, the always block is activated. Three ns later, (a&b) is
evaluated and assigned to c1. The event “(a or b)” will be
checked for change or trigger again. If a or b changes, all the
activities are frozen for 3 ns. If a or b changes in the interim
period, the block is not activated. Hence the module does not depict
the desired output.
o always @ ( a orb)
o c2 = #3 a&b;
o The always block is activated if a or b changes. (a & b) is evaluated
immediately but assigned to c2 only after 3 ns. Only after
the delayed assignment to c2, the event (a orb) checked for change.
If a orb changes in the interim period, the block is not activated.
o always @(a orb)
o #3 c3 <= a&b;
o The block is entered if the value of a orb changes but the
evaluation of a&b and the assignment to c3 take place with a
time delay of 3ns. If a orb changes in the interim period, the
block is not activated.

o always @(a orb)

o c4 <= #3 a&b;
o represents the best alternative with time delay. The always block is activated if a orb
changes. (a&b) is evaluated immediately and scheduled for assignment to c4 with a
delay of 3 ns. Without waiting for the assignment to take effect (i.e., at the same time
step as the entry to the block), control is returned to the event control operator.
Further changes to a orb - if any - are again taken cognizance of.
THE CASE STATEMENT
simple construct for multiple branching in a module. The
o
keywords case, endcase, and default are associated with
the case construct.
o Format of the case construct is
o Case (expression)
o Ref1 : statement1;
o Ref2 : statement2;
o Ref3 : statement3;
o .. .
o
. . .
o default: statementd;
o endcase
EXAMPLE
o module dec2_4beh(o,i);
o output[3:0]o;
o input[1:0]i;
o reg[3:0]o;
o always@(i)
o begin
o case(i)
o 2'b00:o=4'h0;
o 2'b01:o=4'h1;
o 2'b10:o=4'h2;
o 2'b11:o=4'h4;

o default: begin $display

("error");
o o=4'h0;
 CASEX AND
CASEZ
o The case statement executes a multiway branching where
every bit of the case expression contributes to the
branching decision. The statement has two variants
where some of the bits of the case expression can be
selectively treated as don’t cares – that is, ignored.

o Casez allows z to be treated as a don’t care. “?” character

also can be used in place of z.

o casex treats x orz as a don’t care.

SIMULATION FLOW
o In Verilog the parallel processing is structured through
the following [IEEE]:
o Simulation time: Simulation is carried out in simulation time.
o At every simulation step a number of active events are sequentially carried
out.
o The simulator maintains an event queue – called the “Stratified Event
Queue” – with an active segment at itstop. The topmost event in the active
segment of the queue is taken up for execution next.
o The active event can be of an update type or evaluation type. The evaluation
event can be for evaluation of variables, values onnets, expressions, etc.
Refreshing the queue and rearranging it constitutes the update event.
o Any updating can call for a subsequent evaluation and viceversa.
o Only after all the active events in a time step are executed, the simulation
advances to the next time step.
o Completion of the sequence of operations above at anytime step signifies
the parallel nature of the HDL.
STRATIFIED EVENT QUEUE
o The events being carried out at any instant give rise to other events -
inherent in
o the execution process. All such events can be grouped into the following 5
types:
o Active events -
o Inactive events - The inactive events are the events lined up for
execution immediately after the execution of the active events. Events
specified with zero delay are all inactive events.
o Blocking Assignment Events - Operations and processes carried out at
previous time steps with results to be updated at the current time step are of
this category.
o Monitor Events - The Monitor events at the current time step -
$monitor and $strobe - are to be processed after the processing of the active
events, inactive events, and nonblocking assignment events.
o Future events - Events scheduled to occur at some future simulation
time are the future events.
FLOWCHART FOR THE SIMULATION FLOW.
IF AND IF-ELSE CONSTRUCTS
o The if construct checks a specific condition and decides
execution based on the result.
o assignment1;
o if (condition) assignment2;
o assignment3;

o Use of the if-else construct.

o assignment1;
o if(condition)
o begin // Alternative 1
o assignment2;
o end
o else
o begin //alternative 2
o assignment3;
o end
o assignment4;
EXAMPLE
o module demux(a,b,s);
o output [3:0]a;
o input b, [1:0]s;
o reg[3:0]a;
o always@(b or s)
o begin if(s==2'b00)
o begin a[2'b0]=b;
a[3:1]=3'bZZZ; end
o elseif(s==2'b01)
o begin a[2'd1]=b;
{a[3],a[2],a[0]}=3'bZZZ; end
o elseif(s==2'b10)

o begin a[2 'd ]=b;

ASSIGN-DEASSIGN CONSTRUCT
o The assign - deassign constructs allow continuous assignments
within a behavioral block.
o always@(posedgeclk) a = b;
o At the positive edge of clk the value of b is assigned to a, and a
remains frozen at that value until the next positive edge of clk.
Changes in b in the interval are ignored.

o As an alternative, consider the block

o always@(posedgeclk) assign c = d;
o Here at the positive edge of clk, c is assigned the value of d in a
continuous manner; subsequent changes in d are directly reflected as
changes invariable c:
o Always
o Begin
o @(posedgeclk) assign c = d;
o @(negedge clk) deassign c;
o end
o The above block signifies two activities:
o 1. At the positive edge of clk, c is assigned the value of d in a
continuous manner.
o 2. At the following negative edge of clk, the continuous assignment
to c is removed; subsequent changes to d are not passed on to c; it is
as though c is electrically disconnected from d.
REPEAT CONSTRUCT
o The repeat construct is used to repeat a specified block a specified
number of times.
o …
o repeat (a)
o begin
o assignment1;
o assignment2;
o …

o end
o …
o The quantity a can be a number or an expression evaluated to a
number.
o The following block is executed “a” times. If “a” evaluates to 0 or x
orz, the block is not executed.
FOR
LOOP
o The for loop in Verilog is quite similar to the for loop in C
o It has four parts; the sequence of execution is as follows:
o 1. Execute assignment1.
o 2. Evaluate expression.
o 3. If the expression evaluates to the true state (1), carry out
statement. Go to step 5.
o 4. If expression evaluates to the false state (0), exit the loop.
o 5. Execute assignment2. Go to step 2
o ....
o for(assignment1; expression; assignment 2)
o statement;
o . . .
THE DISABLE CONSTRUCT
o To break out of a block or loop. The disable statement
terminates a named block or task. Control is transferred
to the statement immediately following the block
o The disable construct is functionally similar to the breakin
C
o always@(posedge en)
o begin: OR_ gate
o b=1'b0;
o for(i=0;i<=3;i=i+1)
o if(a[i]==1'b1)
o begin b=1'b1;
o disable OR_gate;
o end
o end
WHILE LOOP
o The Boolean expression is evaluated. If it is true, the
statement s are executed and expression evaluated and
checked. If the expression evaluates to false, the loop is
terminated and the following statement is taken
for execution
o while(|a)
o begin
o b=1'b1;
o @(posedge clk)
o a=a- 1'b1;
o end
o b=1'b0;
FOREVER LOOP
o Repeated execution of a block in an endless manner is
best done with the forever loop (compare with repeat
where the repetition is for a fixed number of times).

o always @(posedge en)

o forever#2 clk=~clk;
PARALLEL BLOCKS
o All the procedural assignments within a begin-end block are
executed sequentially. The fork-join block is an alternate one where
all the assignments are carried out concurrently (The non-blocking
assignments too can be used for the purpose.). One can use a fork-
join block within a begin-end block or viceversa.
FORCE-RELEASE CONSTRUCT
o When debugging a design with a number of instantiations, one may
be stuck with an unexpected behavior in a localized area. Tracing
the paths of individual signals and debugging the design may prove
to be too tedious or difficult.
o In such cases suspect blocks maybe isolated, tested, and debugged
and status quo ante established. The force-release construct is for
such a localized isolation for a limited period.
o force a = 1'b0;
o forces the variable a to take the value 0 .
o forceb = c&d;
o forces the variable b to the value obtained by evaluating the expression
c&d.
EVEN
T
o The keyword event allows an abstract event to be declared. The
event is not a data type with any specific values; it is not a variable
(reg) or a net. It signifies a change that can be used as a trigger to
communicate between modules or to synchronize events in different
modules.
o The operator “” signifies the triggering. Subsequently, another
activity can be started in the module by the event change.
o . . .
o event change;
o . . .
o always
o
. . .
o . . .  change;

o . . .
o .always@change
DIGITAL DESIGN
USING VERILOG

Prepared BY
D. Khalandar
Basha
Assoc Prof.,
IARE
UNIT - IV
SWITCH LEVEL MODELING
o Basic Transistor Switches, CMOS Switch, Bi –
directional Gates, Time Delays with Switch
Primitives, Instantiations with Strengths and
Delays, Strength Contention with Trireg Nets
SYSTEM TASKS, FUNCTIONS, AND
COMPILER DIRECTIVES:
o Parameters, Path Delays, Module Parameters,
System Tasks and Functions, File – Based Tasks
and Functions, Compiler Directives, Hierarchical
Access, User-defined Primitives (UDP).
INTRODUCTION

The MOS transistor is the basic element around which a

VLSI is built. Designers familiar with logic gates and their
configurations at the circuit level may choose to do
their designs using MOS transistors.
Verilog has the provision to do the design description at the
switch level using such MOS transistors, which is the theme
of the present chapter.
Switch level modeling forms the basic level of modeling
digital circuits. The switches are available as primitives in
Verilog
BASIC SWITCH PRIMITIVES

Different switch primitives are available in Verilog

nmos switch primitives
nmos (out, in, control);
pmos switch primitives
pmos (out, in, control);
Resistive Switches

o nmos and pmos represent switches of low impedance in the

on-state. rnmos and rpmos represent the resistive
counterparts of these respectively.
rnmos (output1, input1, control1);
rpmos (output2, input2, control2);
o It inserts a definite resistance between the input
and the output signals but retains the signal value
o The rpmos and rnmos switches function as
unidirectional switches; the signal flow is from
the input to the output side.
strength levels

o Output-side strength levels for different input-side

strength values of rnmos, rpmos, and rcmos switches
pullup and pulldown

oAMOS transistor functions as a resistive element when in

the active state. Realization of resistance in this form takes
less silicon area in the IC as compared to a
resistance realized directly. pullup and pulldown
represent such resistive elements.
o pullup (x);
Here net x is pulled up to the supply1 through a resistance.
opulldown(y);
pulls y down to the supply0 level through a resistance.
The pullup and pulldown primitives can be used as loads for
switches or to connect the unused input ports to VCC or GND,
respectively.
CMOS SWITCH

o ACMOS switch is formed by connecting a PMOS and an

NMOS switch in parallel - the input leads are connected
together on the one side and the output leads are connected
together on the other side.

o The CMOS switch is instantiated as shown below.

cmos csw (out, in,N_control, P_control );
BI-DIRECTIONAL GATES

o Verilog has a set of primitives for bi-directional switches as well.

They connect the nets on either side when ON and isolate them
when OFF. The signal flow can be in either direction

o tran and rtran

The tran gate is a bi-directional gate of two
ports. When instantiated, it connects the two ports
directly.
tran (s1, s2);
connects the signal lines s1 and s2.
Either line can be input, inout or output.
rtran is the resistive counterpart of tran.
Cont …

tranif1 and rtranif1

o tranif1 is a bi-directional switch turned ON/OFF through a
control line(c). It is in the ON-state when the control signal
is at 1 (high) state
tranif1 (s1, s2, c );
tranif0 and rtranif0
o tranif0 and rtranif0 are again bi-directional
switches. The switch is OFF if the control line is in
the 1 state, and it is ON when the control
line is in the 0 state.
tranif0 (s1, s2, c);
TIME DELAYS WITH SWITCH PRIMITIVES

o nmos g1 (out, in, ctrl );

has no delay associated with it. The instantiation
o nmos (delay1) g2 (out, in, ctrl );
has delay1 as the delay for the output to rise, fall, and turn OFF.
o nmos (delay_r, delay_f) g3 (out, in, ctrl );
has delay_ras the rise-time for the output. delay_f is the fall-time for the
output. The turn-off time is zero.
o nmos (delay_r, delay_f, delay_o) g4 (out, in, ctrl );
has delay_ras the rise-time for the output. delay_f is the fall-time for the
output delay_ois the time to turn OFF when the control signal ctrl goes
from 0 to 1.
Cont …

o Delays can be assigned to the other uni-directional gates in a

similar manner.
o Bi-directional switches do not delay transmission - their
rise- and fall-times are zero. They can have only turn-on and
turn-off delays associated with them.
o tran has no delay associated with it.
o tranif1 (delay_r, delay_f) g5 (out, in, ctrl );
When control changes from 0 to 1, the switch turns on with a delay of delay_r.
When control changes from 1 to 0, the switch turns off with a delay of delay_f.
o transif1 (delay0) g2 (out, in, ctrl );
represents an instantiation with delay0 as the delay for the switch to turn on when
control changes from 0 to 1, with the same delay for it to turn off when control
changes from 1 to 0
INSTANTIATIONS WITH STRENGTHS AND DELAYS

nmos (strong1, strong0) (delay_r, delay_f, delay_o ) gg (s1,

s2, ctrl) ;
rnmos, pmos, and rpmos switches too can be instantiated in the general form in
the same manner. The general instantiation for the bi-directional gates too can be
done similarly.

STRENGTH CONTENTION WITH TRIREG NETS

o nets declared as trireg can have capacitive storage. Such
storage can be assigned one of three strengths - large,
medium, or small.
o Driving such a net from different sources can lead to
contention
PARAMETERS

o Constants signifying timing values, ranges of variables,

wires, etc., can be specified in terms of assigned names.
Such assigned names are called parameters.
o Two types of parameters are of use in modules
o Parameters related to timings, time delays, rise and fall times, etc.,
are technology-specific and used during simulation. Parameter values
can be assigned or overridden with the keyword “specparam”
preceding the assignments.
o Parameters related to design, bus width, and register size are of a
different category. They are related to the size or dimension of a
specific design; they are technology-independent. Assignment or
overriding is with assignments following the keyword “defparam” .
PATH DELAYS

o Verilog has the provision to specify and check delays associated

with total paths – from any input to any output of a module. Such
paths and delays are at the chip or system level. They are referred
to as “module path delays.”
o Specify Blocks
Module paths are specified and values assigned to their delays
through specify blocks. They are used to specify rise time, fall
time, path delays pulse widths.
specify
specparam rise_time = 5, fall_time = 6;
(a =>b) = (rise_time, fall_time);
(c => d) = (6, 7);
endspecify
Module Paths

o Module paths can be specified in different ways inside a

specify block. The simplest has the form A*>B
o Here “A” is the source and “B” the destination.
specify
(a,b*>s)=1;
(a,b*>ca)=2;
endspecify
Conditional Pin-to-Pin Delays

o The pin topin path of a signal may change depending on the

value of another signal; in turn the number of circuit
elements in the alternate path may differ.
specify
if(f==2'b00)(a=>d)=1;
if(f >2'b00)(a=>d)=2;
(b,cci*>co)=1;
endspecify
MODULE PARAMETERS

o Module parameters are associated with size of bus, register,

memory, ALU, and so on. They can be specified within the
concerned module but their value can be altered during
instantiation. The alterations can be brought about through
assignments made with defparam. Such defparam
assignments can appear anywhere in a module.
SYSTEM TASKS AND FUNCTIONS
o A “$” sign preceding a word or a word group signifies a system task or a
system function
o Output Tasks
$monitor and $display

o Display Tasks
The $display task, whenever encountered, displays the arguments in the
desired format; and the display advances to a newline. $write task carries
out the desired display but does not advance to the new line

$strobe Task
o When a variable or a set of variables is sampled and its value displayed,
the $strobe task can be used; it senses the value of the specified
variables and displays them.
$monitor Task
o $monitor task is activated and displays the arguments specified
whenever any of the arguments changes

o $stop and $finish Tasks

The $stop task suspends simulation.
$finish stops simulation, closes the simulation environment, and
reverts to the operating system .

$random Function
o One can start with a seed number (optional) and generate a
random number repeatedly. Such random number sequences can
be fruitfully used for testing.
FILE-BASED TASKS AND FUNCTIONS
o To carry out any file-based task, the file has to be opened, reading,
writing, etc., completed and the file closed. The keywords for all file-
based tasks start with the letter f to distinguish them from the other
tasks
o All the system tasks to output information can be used to output to a file.
$display, $strobe, $monitor, etc., are of this category. The respective
keywords to output to the file are $fdisplay, $fstrobe, $fmonitor.
o The first field of the task statement is an argument - the file descriptor.
The subsequent fields are identical to the corresponding nonfile tasks.
COMPILER DIRECTIVES

o They allow for macros, inclusion of files, and timescale-

related parameters for simulation. All compiler directives
are preceded by the ‘`’ .
o `define Directive
The `define directive is used to define and associate the desired
text with the macro name
`define add 2'b00

Time-Related Tasks
o The `timescale compiler directive allows the time scale to be specified
for the design. The `timescale directive has two components
o `timescale 1 ms/100 μs
HIERARCHICAL ACCESS

o A Verilog design will normally have a module or

two at the apex level. A number of modules
and UDPs will be instantiated within it.
o $display("fad.a = %0d, fad.b = %0d, fad.fad = %0d", fad.a,fad.b,fad.fad);
USER-DEFINED PRIMITIVES (UDP)

o The primitives available in Verilog are all of the gate or

switch types. Verilog has the provision for the user to define
primitives – called “user defined primitive (UDP)” and use
them.
o A UDP can be defined anywhere in a sourcetext and
instantiated in any of the modules. Their definition is in the
form of atable in a specific format.
o UDPs are basically of two types – combinational and
sequential. A combinational UDP is used to define a
combinational scalar function and a sequential UDP for a
sequential function
Combinational UDPs
o A combinational UDP accepts a set of scalar inputs and gives a scalar
output. An inout declaration is not supported by a UDP.
o The UDP definition is on par with that of a module; that is, it is defined
independently like a module and can be used in any other mo
primitive udp_and (out, in1, in2);
output out;
input in1, in2;
table
// In1 In2 Out
0 0: 0;
0 1: 0;
1 0: 0;
1 1: 1;
endtable
endprimitivedule
Sequential UDPs

o Any sequential circuit has a set of possible states. When it is in one of

the specified states, the next state to betaken is described as a function
of the input logic variables and the present state A sequential UDP can
accommodate all these.
primitive dff_pos(q,din,clk,clr);
output q;
input din,clk,clr;
reg q;
table
o // din clk clr qp qn Whatever be the present
0 (01) 0: ?: 0; // state of the output, at the
1 (01) 0: ?: 1; // positive edge of clk input
? (10) 0: ?: -; // value is latched and
endtable
endprimitive
Digital usin
Design g
Verilog
 Sequential Circuit
Description
. This chapter concentrates on:
. Using Verilog constructs for description of sequential circuits
. Discussion of using gate level and assignments and procedural statements for
describing memory elements.

126
Sequential Models

 In digital circuits, storage of data is done either by feedback, or by gate capacitances

that are refreshed frequently.

127
Sequential Models 128

Sequential
Models

Feedback
Model Capacitive Implicit
Model Model
Feedback Model 129

Sequential
Models

Feedback
Model Capacitive Implicit
Model Model
Feedback Model
. Basic Feedback

state (one
A - -bit)
Memory element
two

Feedback Line

130
Capacitive Model 131

Sequential
Models

Feedback
Model Capacitive Implicit
Model Model
 Capacitive Model
When c 1 the value of D
saved in the input gate
becomes is of the
inverter
and when c 0 this value
becomes
be saved until the next time thatwill
becomes 1 again. c

The complement
of the stored data

Capacitive Storage
.

132
 133

Implicit Model

Sequential
Models

Capacitive
Feedback Implicit
Model
Model Model
 Implicit Verilog offers language constructs that
Model
Feedback and capacitive models
are technology dependent and are technology independent and allow
have the problem of being too much more efficient simulation of
detailed and too slow to circuits with a large number of
simulate. storage elements.

1S Q

1R
C1
. An SR-Latch Notation

134
Basic Memory Components

Basic Memory
Components

Gate Level Primitives User Defined

Sequential Primitives

Memory Elements Behavioral

Using Memory Elements
Assignments
Flip-flop Timing Memory Vectors
and Arrays
135
Gate Level Primitives

Basic Memory
Components
User Defined
Gate Level Primitives
Sequential Primitives

Memory Elements Behavioral

Using Assignments Memory Elements

Flip-flop Timing Memory Vectors

and Arrays
136
 Gate Level Primitives
latch 1-bit Storage
Element

g1

g2

137
. Cross-Coupled NOR Latch
 Gate Level Primitives
Base of most static
memory components

、 timescale 1ns/100ps

module latch (input s, r, output q, q_b

); nor #(4)
g1 ( q_b, s, q ),
g2 ( q, r, q_b ); q and q_b outputs are
endmodule initially X and remain at
this ambiguous state for
as long as s and r

. SR-Latch Verilog Code remain 0.

Simultaneous assertion
of both inputs results in 138
loss of memory.
 Gate Level
Control Gates

Clock Primitives
latch p
Input

. All NAND Clocked SR-Latch

139
 Gate Level Primitives Delay values can
be
controlled when the
`timescale 1ns/100ps is instantiated.
latch
module latch_p #(parameter tplh=3, tphl=5)
(input s, r, c, output q, q_b );
wire _s, _r;
Set and Reset inputs to the
nand cross_coupled core of this
#(tplh,tphl) memory element
g1 ( _s, s, c ),
g2 ( _r, r, c ),
g3 ( q, _s, q_b ),
g4 ( q_b, _r,
q );
endmodule

. All NAND Clocked Latch 140

 Gate Level Primitives

. SR Latch Simulation This delay is due to a fall of 3ns

and arise of 5 ns in the NAND
gates of the circuit. 141
 Gate Level Primitives
Master Slave

. Master-Slave D Flip-Flop

142
 Gate Level
Primitives
`timescale 1ns/100ps
module master_slave (input d, c, output q,
q_b );
wire qm, qm_b;
defparam master.tplh=4,
slave.tpl =4, master.tphl=4, Hierarchical Naming
h slave.tphl=4;
latch_
p master ( d, ~d, c, qm,
qm_b ),
slave ( qm, qm_b, ~c, q,
q_b ); endmodule

. Master-Slave D Flip-Flop Verilog Code

143
User Defined
Sequential
Primitives
Basic Memory
Components User Defined
Gate Level Primitives
Sequential Primitives

Memory Elements Behavioral

Using Memory Elements
Assignments
Memory Vectors
Flip-flop Timing and Arrays
144
 User Defined
Sequential Primitives
. Verilog provides language constructs for defining sequential UDPs:
. Faster Simulation of memory elements
. Correspondence to specific component libraries

145
 User Defined Sequential
Primitives
primitive latch( q, s, r,
c ); output q;
reg q;
input s, r, c;
initial q=1'b0;
table
// s r c q q+ ;
// ------:---:----;
? ?0 :? :- ;
00 1 : ? :- ; Table defining the latch
0 1 1 : ? :0 ; output
1 0 1 : ? : 1 ;
endtable
endprimitive

146
. Sequential UDP Defining a Latch
 User Defined Sequential
Primitives
primitive latch( q, s, r, c );
.............
............. Column for specifying
table present state
// s r c q
q+ ;
// Signifies no
“ ”

------:---:----; change
? ?0:?:- ;
0 0 1 : ? :-
; 0 1 1 : ? :
0 ; 10 1 : ?
: 1 ;
endtable Signifies any
“ ”

value
endprimitive

. Sequential UDP Defining a Latch 147

Memory Elements Using
Assignments
Basic Memory
Components
User Defined
Gate Level Primitives
Sequential Primitives
Memory Elements Behavioral
Using Assignments Memory Elements

Memory Vectors
Flip-flop Timing
and Arrays
148
 Memory Elements Using
When a block s ’

clock input is 0 ,

it puts its output back

master_slave
Assignment
to itself (feedback),

s
and when its clock is
1 it puts its data input
into its output.

149
. Master-Slave Using Two Feedback Blocks
 Memory Elements
Using
Assignments
`timescale 1ns/100ps

module master_slave_p #(parameter delay=3)

(input d, c, output q);
wire qm;
assign #(delay) qm = c ? d : The feedback of qm
qm; output back to its input
assign #(delay) q = ~c ? qm :
q; endmodule
Each assign statement
implements a latch
Complementary
. Assign Statements Implementin mLpolgeiClocks:
sd acs er-slave
flip-flop
150
Behavioral Memory
Elements

Basic Memory
Components
User Defined
Gate Level Sequential Primitives
Primitives
Behavioral
Memory Elements Memory Elements
Using Assignments
Memory Vectors
Flip-flop Timing and Arrays
151
 Behavioral Memory
Elements
. Behavioral Coding:
. A more abstract and easier way of writing Verilog code for a latch or
flip-flop.
. The storage of data and its sensitivity to its clock and other control inputs will be
implied in the way model is written.

152
Behavioral Memory Elements153

Behavioral
Memory
Elements

Latch
Flip -flop
Modeling
Modeling
Flip-flop
with Set-Reset Other
Storage Element
Control Modeling Styles
Latch Modeling 154

Behavioral
Memory
Elements

Latch
Flip-flop
Modeling
Modeling
Flip-flop
with Set-Reset Other
Storage Element
Control Modeling Styles
While c is 1
changes on d directly q
affect
Latch Modeling
and q_b outputs.
A Storage
unit
Level Sensitive c:

`timescale1ns 10 p A
to Latch
/ 0 s
module latchinpu d, outpu reg q,
alway @( (ot d c, t q_b );
s
if ( c c r )
)
begin
#4 q = input is read and
d;
#3 q_b = After 4nstod
assigned
end ~d; q output.
endmodule
If d changes between the
time q and q_b
it is read
for
erroneous results
Type Latch Verilog Code happen.
.
A D- After another wait of 3ns, d is
read again 155
~d is
and
to q_b output. assigned
 Latch Modeling Corrects the
timing of
problem
`timescale 1ns/100ps blocking
assignments.

module latch (input d, c, output reg q, q_b );

always @( c or d )
if ( c )
begin
q <= #4 d;
q_b <= #3 ~d;
end
endmodule

Non -blocking assignments

Latch Model Using Nonblocking Assignments
.
With intra- statement
156 delay

controls
 Latch Modeling

. Testing Latch with Nonblocking Assignments

Storing a 0
at 50
157

Storing a 1 time
at time 30
Flip-flop Modeling 158

Behavioral
Memory
Elements

Latch Flip -flop

Modeling Modeling
Other
Flip-flop
with Set-Reset
Storage Element
Control Modeling Styles
 With each clock
edge,block
the entire procedural
is Fli-flop Modeling
executed once from begin
to
A basic edge trigger
end.
p flip-flop model at
the behavioral
`timescale 1ns/100ps
level
module d_ff (input d, clk, output reg q, q_b
); always @( posedge clk
) begin
q <= #4 d; Sensitive to
q_b <= #3 ~d; positive
the edge of the
clock
end Assignments to q and q_b
endmodul are reached immediately
e afterflow always block begins.
the
in

. Positive Edge Trigger Flip-Flop

The actual assignments 159
of values are delayed.
 During the cl is 1 (from 60ns to
Fli-flop Modeling time
80ns exclusive k 60 and inclusive of
80),
of changes d do not affect
p on of
state -flop the
flip

Simulation of a Positive Edge Flip

. At 60ns, on the positive edge
-Flop
clock,ofthe value d is read
of q_b for
scheduled into q and and
64ns and 63ns respectively.
times
160
Flip-flop with 161

- Reset
Set Control
Behavioral
Memory
Elements

Latch
Modeling Flip-flop
Modeling
-flop
Flip Other
with Set-Reset
Storage Element
Control Modeling Styles
 Flip-flop With Set-Reset
Control
`timescale 1ns/100ps

module d ff sr_Synch (input d, s, r, clk, output reg q, q_b );

always @(posedge clk) begin
if( s ) begin
q <= #4 1'b1;
q_b <= #3 1'b0;
end else if( r ) begin
q <= #4 1'b0;
q_b <= #3 1'b1;
end else begin
q <= #4 d;
q_b <= #3 ~d;
end
end
endmodule

. D Type Flip-Flop with Synchronous Control 162

 Flip-flop With Set-Reset
Control
module d_ff_sr_Synch (input d, s, r, clk,
output reg q, q_b );
always @(posedge clk)
begin if( s ) begin The flow into always block
is only initiated by the posedgeof
end else if( r ) clk
begin
end else
begin These if-statements with
s andr conditions are only
end examined after the positive
end edge of the clock
endmo
dule
Synchronous s and r control
inputs

. D Type Flip-Flop with Synchronous Control (Continued) 163

Flip-flop With Set- Reset
Control
if( s ) begin
q <= #4 1'b1;
q_b <= #3 1'b0;
end else if( r ) begin
q <= #4 1'b0;
q_b <= #3 1'b1;
end else begin
These if-statements with
q <= #4 d; s andr conditions are only
q_b <= #3 ~d; examined after the positive
end edge of the clock

. D Type Flip-Flop with Synchronous Control (Continued) 164

 Flip-flop With Set-Reset
Control
`timescale 1ns/100ps
module d ff sr_Asynch (input d, s, r, clk, output reg q, q_b );
always @ ( posedge clk, posedges, posedge r )
begin
if( s ) begin
q <= #4 1'b1;
q_b <= #3 1'b0;
end else if( r ) begin
q <= #4 1'b0;
q_b <= #3 1'b1;
end else begin
q <= #4 d;
q_b <= #3 ~d;
end
end
endmodule

. D-type Flip-Flop with Asynchronous Control 165

 Flip-flop With Set-Reset
Control
module d_ff_sr_Asynch (input d, s, r, clk,
output reg q, q_b );
always @( posedge clk posedge s, posedge r )
,

begin if( s ) begin

....................
end else if( r ) The sensitivity list of the always
begin block
end else begin
Asynchronous
end set and reset inputs
end
endmodule

. D-type Flip-Flop with Asynchronous Control (Continued) 166

 Flip-flop With Set-Reset
Control
if( s ) begin
q <= #4 1'b1;
q_b <= #3 1'b0;
end else if( r ) begin
q <= #4 1'b0;
q_b <= #3 1'b1; This flip-flop is sensitive to the
end else begin edge of clock, but to the levels
q <= #4 d; of s andr .
q_b <= #3 ~d;
end
....................

. D-type Flip-Flop with Asynchronous Control (Continued) 167

 Fli-flop With Set- changes
Before 120 ns, changes to q
Rese
s
triggered byisthe clockbecome active and
to the
and cause -flop
r

pand 4 一 and
Control
Syncb
same.
4 一 are
flip
A5yncb the t output.

. Comparing Synchronous and Asynchronous Flip-Flop Controls

4 一 changes occur
independent
A5yncb of the clock 5

4 一 Syncbwill waits for the edge when

or r becomes active 168

the clockofto set or reset

Other Storage Element Modeling
169

Styles
Behavioral
Memory
Elements

Latch
Flip -flop
Modeling
Modeling
Flip-flop
Other
with Set-Reset
Storage Element
Control Modeling Styles
 Other Storage Element
Modeling Styles
A latch using a wai
`timescale statement instead
t of an
1ns/100ps event control
module latch (input d, c, output reg q, q_b ); statement

always begin Blocks the flow of procedural

wait ( c ); block when
c is 0 .
#4 q <=
_bq<= ~d; and remains at
d; #3 If
this becomes
c 1
value, the body of the
end
statement repeats itself every
always
endmodule 7
ns.

If the
Latch Using wait, a Potentially Dangerous delay control statements are
Model
omitted, then the looping of
the
.

always block happens in zero

causing an infinite loop in time, 170

simulation.
Flip-flop Timing

Basic Memory
Components

Gate Level Primitives User Defined

Sequential Primitives

Memory Elements Behavioral

Using Assignments Memory Elements
Memory Vectors
Flip-flop and Arrays
Timing
171
Flip-flop Timing 172

Flip-flop
Timing

Width
Setup Hold And
Time Time Period
 173

Setup Time

Flip-flop
Timing

Width
Setup Hold
And
Time Time
Period
 Setup Time
. Setup Time
. The Minimum necessary time that a data input requires to setup before it is
clocked into a flip-flop.
. Verilog construct for checking the setup time: $setup task
. The $setup task:
. Takes flip-flop data input, active clock edge and the setup time as its parameters.
. Is used within a specify block.

174
 Continuously checks
timing distance between
$setup task within a specify changes on d
Setup Time
block and the positive edge of clk.
If this adistance is message
violation less thanwill
5ns,be
`timescale issued.
1ns/100ps
module d_ff ( input d, clk, s, r, output reg q,
q_b );
specify
$setup ( d, posedge clk, 5 );
endspecify
always @( posedgeclk or posedge s or posedge
rbegin
)

end
endmodul
e Positive edge trigger flip-flop and
Asynchronous set and
reset
controls
. Flip-Flop with Setup Time
175
 Setup Time
always @( posedge clk orposedge s or posedge r )
begin
if( s ) begin
q <= #4 1'b1;
q_b <= #3 1'b0;
end else if( r ) begin
q <= #4 1'b0;
q_b <= #3 1'b1;
end else begin
q <= #4 d;
q_b <= #3 ~d;
end
end
endmodule

176
.
Flip-Flop with Setup Time
(Continued)
 The d input changes at 57ns and

Setup Time
the data is clocked into the flip-
flop at 60ns,
only 3ns after d.

.
Setup Time Violation
The simulation run reports
the violation.

177
 178

Hold Time

Flip-flop
Timing

Hold Width
Setup
And
Time Time
Period
 Hold Time
. Hold Time
. The Minimum necessary time a flip-flop data input must stay stable (holds its
value) after it is clocked.
. Verilog construct for checking the setup time: $hold task
. The $setup task:
. Takes flip-flop data input, active clock edge and the required hold time as its
parameters.
. Is used within a specify block.

179
 Hold Time
`timescale 1ns/100ps

module d_ff ( input d, clk, s,r, output regFliqp fqlo_pbw);ithhold time of 3ns.
specify
$hold ( posedge clk, d, 3 );
endspecify
always @( posedge clk or posedge s or posedge
r ) begin

end
endmodule

. Flip-Flop with Hold Time

180
 Hold The clock samples the d value of 1
at 20ns. At 22ns, d changes.
Time This violates the minimum
required hold time
ns. of 3

. Hold Time Violation

181
 Hold Time

. The Verilog $setuphold task combines setup and hold timing checks.
. Example:
. $setuphold (posedgeclk, d, 5, 3)

182
Width And Period 183

Flip-flop
Timing

Width
Setup
Time Hold
And
Time Period
 Width And Period
. Verilog $width and $period check for minimum pulse width and period.

. Pulse Width: Checks the time from a specified edge of a reference signal to its
opposite edge.

. Period: Checks the time from a specified edge of a reference signal to the same edge.

184
 Width And
Period
specify
$setuphold ( posedge clk, d, 5, 3 );
$width (posedge r, 4);
$width (posedge s, 4);
$period (negedge clk, 43);
endspecify

always @( posedge clk or posedge s or posedge r )

if( s ) q <= #4 1'b1;
else if( r ) q <= #4 1'b0;
else q <= #4 d;

185

. Setup, Hold, Width, and Period Checks (Continued)

Controllers

Component
Description

Data
Components Controllers

186
Controllers

Decisions
Based on :Inputs ,
Outputs ,State

Issue Control Signal

Set Next State

. Controller Outline Go to Next State

187
 Controllers
. Controller:

. Is wired into data part to control its flow of data.

. The inputs to controller determine its next states and outputs.
. Monitors its inputs and makes decisions as to when and what output signals to
assert.
. Keeps the history of circuit data by switching to appropriate states.
. Two examples to illustrate the features of Verilog for describing state machines:
. Synchronizer
. Sequence Detector

188
Controllers

Controllers

Sequence
Detector
Synchronizer

189
Synchronizer

Controllers

Sequence
Synchronizer Detector

190
 Synchronizer

Clk

adata

synched

. Synchronizing adata

191
Synchronizer

`timescale 1ns/100ps
module Synchronizer (input clk, adata,
output reg synched);
always @(posedge clk)
if (adata == 0) synched <= 0;
else synched <= 1;
endmodule If a 1 is Detected on
adata on the rising
edge of clock,
A Simple Synchronization Circuit
.
synched becomes 1
and
remains 1
for atleast one
clock period
192
Sequence Detector

Controllers

Synthesizer Sequence
Detector

193
Sequence Detector
When the sequence
is detected, the w
Searches on Output becomes 1
it’sa input stays 1 and
for a complete
for the clock cycle
110
Sequence If 110 is detected
on a, then w gets
a w
1, else w gets 0 .

clk
. State Machine Description

194
 Sequence Detector
A Moore Machine
Sequence Detector
States are named: The State in which the
s0 , s1 , s2 , s3 110 sequence is
0 1 detected.
reset
1 1 0

S0 S1 S2 S3
0 0 0 0 1
1
Initia
l 0
State
It Takes atleast
3 clock periods to
. Sequence Detector State Machine get
to the s3 state

195
Sequence Detector
module Detector110 (input a, clk, reset, output w);
parameter [1:0] s0=2'b00, s1=2'b01, s2=2'b10, s3=2'b11;
reg [1:0] current;

always @(posedge clk) begin

if (reset) current = s0;
else
case (current)
s0: if (a) current <= s1; else current <= s0;
s1: if (a) current <= s2; else current <= s0;
s2: if (a) current <= s2; else current <= s3;
s3: if (a) current <= s1; else current <= s0;
endcase
end
assign w = (current == s3) ? 1 : 0;

endmodule

. Verilog Code for 110 Detector 196

State Machine Coding

State Machine
Coding

Moore Machines Mealy Machines

A More Modular
Huffman
Style
Coding
Style
A ROM Based
Controller

197
Moore Machines

State Machine
Coding

Moore Machines Mealy Machines

A More Modular
Huffman
Style
Coding
Style
A ROM Based
Controller

198
 Moore Machines
. Moore Machine :
.
A state machine in which all outputs are carefully synchronized with the
circuit
clock.
.
In the state diagram form, each state of the machine specifies its
outputs
independent of circuit .
. inputs
In Verilog code of a state machine, only circuit state variables participate in
the
output expression of the
circuit.

199
Mealy Machines

State Machine
Coding

Moore Machines Mealy Machines

A More Modular
Huffman
Style
Coding
Style
A ROM Based
Controller

200
 Mealy Machines
. Mealy Machine :
. Is different from a Moore machine in that its output depends on its current state
and inputs while in that state.
. State transitions and clocking and resetting the machine are no different from
those of a Moore machine. The same coding techniques are used.

201