Flip Flop

Types of Logic Circuits

• Combinational Logic circuits:
• The outputs at any instant of time depend only on the input signals present at
that time.
• The output does not depend upon any past inputs or outputs.

x1 y1
x2 y2
Combinational Circuit y3
x3
x4 y4
Sequential Circuits
• Logic circuits whose outputs at instant of time depend not only on the
present inputs but also on the past outputs.
• Here the output signals are fed back to the input side.

Sequential
Circuit
Latches
• The simplest type of Sequential circuit has only 2 states.
• It is a memory cell which is capable of storing 1 bit of information, o
or 1.
• This sequential circuit is called Latch since 1 bit of information can be
locked or latched.
Latches

x1 G1 Q

x2 G2 Q’
• Flip Flops-

• A Flip Flop is a memory element that is capable of storing one

bit of information.
• A flip flop has two outputs as shown
• A flip flop can maintain a binary state for an unlimited period of
time as long as-
• Power is supplied to the circuit.
• Or until it is directed by an input signal to switch states.
• A flip flop is also called as Bistable Multivibrator because it
has two stable states either 0 or 1.
Types of Flip Flops
• Flip flops are of different types depending on how their inputs
and clock pulses cause transition between two states.
• There are 4 basic types of flip flops-
SR Flip Flop
• SR flip flop is the simplest type of flip flops.
• It stands for Set Reset flip flop.
• It is a clocked flip flop.
Methods for constructing FlipFLops
1. Construction of SR Flip Flop By
Using NOR Latch-
• This method of constructing SR Flip Flop uses-
• NOR latch
• Two AND gates
2. Construction of SR Flip Flop By
Using NAND Latch
• This method of constructing SR Flip Flop uses-
• NAND latch
• Two NAND gates
Logic Symbol for SR Flip flop
Truth Table for SR Flip Flop
INPUTS OUTPUTS

Qn Qn+1
S R
(Present State) (Next State)

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 1

1 0 1 1

1 1 0 Indeterminate

1 1 1 Indeterminate
The above truth table can be
reduced as
INPUTS OUTPUTS REMARKS

Qn Qn+1
S R States and Conditions
(Present State) (Next State)

0 0 X Qn Hold State condition S = R = 0

Reset state condition S = 0 , R

0 1 X 0
=1

Set state condition S = 1 , R =

1 0 X 1
0

Indeterminat Indeterminate state condition

1 1 X
e S=R=1
JK Flip Flop
• JK flip flop is a refined & improved version of SR Flip Flop
• It has been introduced to solve the problem of indeterminate
state that occurs in SR flip flop when both the inputs are 1.
• In JK flip flop,
• Input J behaves like input S of SR flip flop which was meant to set the flip flop.
• Input K behaves like input R of SR flip flop which was meant to reset the flip
flop.
Construction of JK Flip Flop
 Construction of JK Flip Flop By Using SR
Flip Flop Constructed From NOR Latch
This method of constructing JK Flip Flop uses-
• SR Flip Flop constructed from NOR latch
• Two other connections
Logic Symbol
 Truth Table

Truth Table for JK Flip FLop

INPUTS OUTPUTS

Qn Qn+1
J K
(Present State) (Next State)

0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
Reduced Truth table
INPUTS OUTPUTS REMARKS

Qn Qn+1
J K States and Conditions
(Present State) (Next State)

0 0 X Qn Hold State condition J = K = 0

Reset state condition J = 0 , K =

0 1 X 0
1

1 0 X 1 Set state condition J = 1 , K = 0

1 1 X Q’n Toggle state condition J = K = 1

Construction of JK Flip Flop By Using SR
Flip Flop Constructed From NAND Latch
This method of constructing JK Flip Flop uses-
• SR Flip Flop constructed from NAND latch
• Two other connections
D Flip Flop / Delay, Data flip flop
• The D flip-flop is obtained by modifying circuit of clocked
SR flip-flop. The complement of the D input is connected to
the R input, while the D input is connected to the S input.
• When the value of Clock pulse is “1,” the D input is
transferred to the flip flop.
• When clock pulse is high the flip-flop is enabled.
• The flip flop output is 1 with D= 1 and
• output is 0 with D = 0.
• Therefore, D Flip-Flop is said as Delay Flip-Flop or Data
Flip-Flop or Transparent Flip-Flop.
The graphical representation, circuit diagram,
truth table, excitation table of D Flip Flop
Truth table of D Flip-Flop:
Characteristic Table of D Flip-Flop:
CP D Qn

0 X Qn

1 0 0

1 1 1
D Qn Qn+1
0 0 0
1 0 1
0 1 0
1 1 1
T Flip Flop
• T Flip-flop is simplified form of J-K flip flop.
• Because the J and K inputs are coupled, the device is
often referred to as a single input J-K flip flop.
• With the clock pulse to be high the
• input T= 0, output remains in same state.
• If input T= 1, the output toggles.
Truth Table of T Flop Flop

CP T Qn
0 X Qn
1 0 No Change
1 1 Toggle
Qn Qn+1 T
0 0 0
0 1 1
1 0 1
1 1 0
Master Slave Flip Flop
Race Round Condition
• In "JK Flip Flop", when both the inputs and CLK set to 1
for a long time, then Q output toggle until the CLK is 1.
• Thus, the uncertain or unreliable output produces. This
problem is referred to as a race-round condition in JK
flip-flop and avoided by ensuring that the CLK set to 1
only for a very short time.
• When the clock pulse is true, the slave flip flop will be in
the isolated state, and the system's state may be
affected by the J and K inputs. The "slave" remains
isolated until the CP is 1. When the CP set to 0, the
master flip-flop passes the information to the slave flip
flop to obtain the output.
• The master flip flop responds first from the slave
because the master flip flop is the positive level trigger,
and the slave flip flop is the negative level trigger.
• The output Q'=1 of the master flip flop is passed to the
slave flip flop as an input K when the input J set to 0 and
K set to 1. The clock forces the slave flip flop to work as
reset, and then the slave copies the master flip flop.
• When J=1, and K=0, the output Q=1 is passed to the J
input of the slave. The clock's negative transition sets
the slave and copies the master.
• The master flip flop toggles on the clock's positive
transition when the inputs J and K set to 1. At that time,
the slave flip flop toggles on the clock's negative
transition.
• The flip flop will be disabled, and Q remains unchanged
when both the inputs of the JK flip flop set to 0.
• A master-slave flip-flop contains two clocked flip-flops.
• The first is called a master and the second is a slave.
• When the clock is high the master is active. The output of the master is
set or reset according to the state of the input.
• As the slave is in active during this period its output remains in the
previous state. When the clock becomes low the output of the slave
flip-flop changes because it becomes active during the low clock
period.
• The final output of the master-slave flip-flop is the output of the slave
flip-flop.
• So the output of master-slave flip flop is available at the end of a clock
pulse.