ECCE4227: Embedded Systems

Chapter 10: Interrupts

 Content

 Upon completion of this chapter, you will be able to:

 Compare polling vs. interrupts.
 Explain the purpose of Interrupt Service Routine (ISR).
 Understand the role of Interrupt Vector Table (IVT).
 List major interrupts of AVR.
 Describe the external hardware interrupts of the AVR.
 Program AVR external interrupts in C.

2
 Interrupts: Definition
Interrupt is a mechanism that allows
modules such as I/O and memory to
interrupt the normal processing of the
processor
Progra
ms

Analogy:
Teacher and Students CPU

Memor
I/O
y

3
Polling vs. Interrupt

4
 Polling vs. Interrupt [cont.]
Using polling,
 The CPU must continually check the device’s status.

Using interrupt:
 A device will send an interrupt signal when needed.
 In response, the CPU will execute an interrupt service
routine (ISR),
 Then, the CPU resumes its normal execution.

5
 Polling vs. Interrupt [cont.]

How is an interrupt serviced?

1. Stop fetching the next instruction and save PC
2. Find the address of the ISR of the interrupting
device (using Interrupt Vector Table IVT)
3. Execute the function
4. Resume normal execution by retrieving PC

6
 Polling vs. Interrupt [cont.]

Polling Interrupt
 Ties  Efficient
CPU use
down the CPU
 Has priority
 Can be masked

main( )
while (true)
{
{
Do your common task
if(PIND == 0)
}
//do something;
whenever PIND is 0 then
}
do something

7
 Interrupt Sources

Microcontroller has various on-chip peripheral

devices (interrupt sources) that can interrupt the
main program:
 External switches
 Timers
 Serial ports
 PWM
 ADC

8
 Interrupt Controllers

Peripherals
Timers
IRQ0
CPU IRQ1 I/Os
Interrupt IRQ2
Controller IRQ3 USART

….
IRQn SPI

9
 Interrupt control unit in AVR

SREG I T HRAM S V EEPROM

N Z C Timers
PROGRAM
ROM

Program
Bus Bus
CPU

SREG

EIMSK
PCICR
PCMSK0
PCMSK1 Other
OSC PCMSK2 Ports
Peripherals
Interrupt Unit
TIMSK0
TIMSK1
TIMSK2 I/O
PINS
10
 Interrupt Service Routine (ISR)

ISR: Interrupt Service Routine

 The function that is executed when an interrupt is
enabled

IVT: Interrupt Vector Table

 A table that keeps the address of each ISR in the
instruction memory

11
 Interrupt Service Routine (ISR)

Interrupts can occur at any time during

processing

Interrupt Occurred

Interrupt Serviced ISR

Depending on the interrupts priority Main Program

the processor may transfer control to
ISR immediately, later, or never! 12
 Interrupt Service Routine (ISR)

1(a): P is executing its main program Program memory μP Data memory

ISR
1(b): P1 receives input data in a register 16: LDS R0, 0x8000
17: # modifies R0 System bus
with address 0x8000.
18: STS 0x8001, R0
19: RETI # ISR return
... Int P1 P2
Main program
... PC 0x8000 0x8001
100: instruction
101: instruction

13
 Interrupt Service Routine (ISR)

2: P1 asserts Int to request servicing by Program memory μP Data memory

the microprocessor ISR
16: LDS R0, 0x8000
17: # modifies R0 System bus
18: STS 0x8001, R0
19: RETI # ISR return
... Int P1 P2
Main program 1
... PC 0x8000 0x8001
100: instruction
101: instruction

14
 Interrupt Service Routine (ISR)

3: After completing instruction at 100, Program memory μP Data memory

P sees Int asserted, saves the PC’s ISR
value of 100, and sets PC to the ISR 16: LDS R0, 0x8000
17: # modifies R0 System bus
fixed location of 16.
18: STS 0x8001, R0
19: RETI # ISR return
... Int P1 P2
Main program
... PC 0x8000 0x8001
100: instruction
101: instruction 100

15
 Interrupt Service Routine (ISR)

4(a): The ISR reads data from 0x8000, Program memory μP Data memory
modifies the data, and writes the ISR
resulting data to 0x8001. 16: LDS R0, 0x8000
17: # modifies R0 System bus
4(b): After being read, P1 deasserts Int. 18: STS 0x8001, R0
19: RETI # ISR return
... Int P1 P2
Main program 0
... PC 0x8000 0x8001
100: instruction
101: instruction 100

16
 Interrupt Service Routine (ISR)

5: The ISR returns, thus restoring PC to Program memory μP Data memory

100+1=101, where P resumes ISR
executing. 16: LDS R0, 0x8000
17: # modifies R0 System bus
18: STS 0x8001, R0
19: RETI # ISR return
... Int P1 P2
Main program
... PC 0x8000 0x8001
100: instruction +1
101: instruction 100

17
Interrupt Vector Table (IVT)

Highest
priority

Lowest
priority
18
 Interrupt Vector Table (IVT) [cont.]
Vector Number
 An interrupt with a lower ‘Vector No.’ has a higher priority.
 Example: INT0 has a higher priority than INT1.

Program Address
 The fixed memory location for a given interrupt handler.

Interrupt Vector Name

 This is the interrupt name to be used with C macro ISR().

19
 Enabling Interrupt
Interrupts can be enabled or disabled by the
programmer

 Enabled Bit7 (I=1) in SREG (status register)

 Disabled on reset (I=0)

In addition to Bit7 (I) in SREG each interrupt

should be enabled independently
20
 Enabling Interrupt [cont.]

Interrupt Enable, Flag bits

 Each interrupt source has an ENABLE bit that allows
an interrupt to be generated if interrupt condition is
met. By default, interrupts are NOT enabled.
 Each interrupt source also has a FLAG bit that
indicates if the interrupt has occurred.
 Each interrupt source also has a PRIORITY bit that
allows it to be assigned a low or high priority.

21
 Interrupt Priority

What if two or more interrupts occur at the same

time?
The interrupt with lower ISR address is prioritized
(external INT0 has the highest priority)

When an interrupt is serviced, the ENABLE bit is

cleared automatically (i.e. set to zero) to disable
that interrupt
Will be enabled when returning from the ISR

22
 How to Program Interrupt

Follow the five steps to program an interrupt:

1. Include the AVR interrupt library <avr/interrupt.h>
2. Use C macro ISR() to define the interrupt handler and
update IVT
3. Enable the specific interrupt
4. Configure details of the interrupt by setting relevant
registers
5. Enable the interrupt subsystem globally using the function
sei()

23
 How to Program Interrupt [cont.]

The C macro ISR() is used to define the handler

for a given interrupt.
Its syntax is given as:
ISR (interrupt_vector_name)
{
// … body of ISR
}

where interrupt_vector_name is given in IVT.

24
 External
Interrupts
S
C
E
l
h

Types of External Interrupts

i
C
a
d
p
e
C
-8

2
:
E
I6
4
n
t
2
Two external interrupts
e
2
r
r
7
u
p
-t can be triggered:
F  INT0
L
1
 INT1
6

Key steps in using external interrupts:

1. Enable the interrupt
2. Specify what types of event to trigger the interrupt
26
 Types of Triggers

Interrupts can be edge-triggered or level-

triggered
 Edge trigger: activated when
a change in signal level occurs
 Level trigger: activated when
a signal has a specific value

INT0 and INT1 can be programmed to be edge

or level triggered
 Low-level active by default
27
 External Interrupts in AVR
Specify the events that trigger an external
interrupt by configuring the register MCU Control
Register (MCUCR) (INT0 and INT1).

01 00

28
 Enabling the External Interrupt
 To enable an external interrupt, set the corresponding
flag in General Interrupt Control Register (GICR).

 Example:
 To enable INT1 on pin D.3, we can write
 GICR |= (1 << INT1);
 To enable both INT1 and INT0 sources, we can write
 GICR |= (1 << INT1) | (1 << INT0);

 Note that INT1, INT0, and GICR names are already defined
in <avr/io.h> using ‘#define INT1 7’ and ‘#define INT0 6’
29
 Example 1

 Write a C program to toggle port B whenever a switch is

flipped. The program should use an external interrupt.
 Let’s use interrupt INT1. This interrupt is triggered on pin
PD.3.
 To enable interrupt INT1:
 GICR |= (1 << INT1);
 To specify that INT1 is triggered on any change in pin
PD.3:
 MCUCR |= (1 << ISC10); #define ISC10 3
 Then, we write interrupt handler and enable interrupt
subsystem.

30
 Example 1 (C Code)

|
|

31
 Example 2
 Assume that the INT0 pin is connected to a switch that is
normally high. Write a program that toggles PORTB.5, whenever
INT0 pin goes low.
#include <avr/io.h>
#include <avr/interrupt.h>

ISR (INT0_vect) // ISR for external

interrupt 0
{ PORTB ^= (1<<5); // toggle PORTB.5 }

int main ()
{
DDRB |= 1<<5; // PB5 as an output
MCUCR |= 1<<ISC01; // Set INT0 falling-edge
triggered

GICR |= (1<<INT0); // Enable INT0

sei (); //
Enable global interrupt 32
 Example 3
 Consider a switch connected to the external interrupt
pin INT0 of an ATMega8 AVR as shown in the figure
 A 7-segment display with decoder is connected to port PB0-
PB3 on the same AVR.
 We require that a program waits for the switch to be pressed
to start an ISR.
 In the ISR, it simply increments the number displayed on the
7-segment display

PB0
PB1
PB2
PB3

33
 Example 3 (C Code)
#include <avr/io.h>
#include <avr/interrupt.h>

Char count = 0 // global variable

ISR (INT0_vect) //ISR for external interrupt 0

{
count++;
if (count==10) count =0;
PORTB = count; //Display count on
toggle PORTB
}

int main ()
{
DDRB = 0x0F; // PB0-PB3 as an
output
MCUCR |= 1<<ISC01; // INT0 is falling-edge
triggered
GICR |= (1<<INT0); //enable external interrupt 34
0
 RECOMMENDED PROBLEMS

PROBLEMS HIGHLIGHTED IN RED HAVE HIGHER PRIORITY

CHAPTER-10 [Interrupts]

Problems:
S10.1 (1, 2, 4, 5, 6, 9, 12, 14, 16, 17, 25, 26) S10.2 (22,
24, 29) S10.3 (31, 32, 35, 37, 42, 45, 46).

35