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Lecture11 CompOrg&Design InstrCycle MRInstrs Fall2022

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16 views21 pages

Lecture11 CompOrg&Design InstrCycle MRInstrs Fall2022

Uploaded by

Sohaib
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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CE 222: Computer

Organization and
Assembly Language
Basic Computer Organization and Design

Dr. Fahad Bin Muslim

1
Outlines
• Instruction Cycle
• Memory-Reference Instructions

2
References
• Chapter 5, Morris Mano, “Computer System
Architecture”

3
Instruction Cycle

4
Instruction Cycle
• In the basic computer, each instruction cycle
consists of the following phases:
1. Fetch instruction from memory
2. Decode it
3. Read effective address from memory incase of indirect
address
4. Execute the instruction
• After step 4, control goes back to step 1
• The process repeats indefinitely unless a HALT
instruction is encountered

5
Fetch and Decode
• The microoperations for the fetch and decode
phases can be specified by the following register
transfer statements:

6
Register Transfer: Fetch
Phase

7
Determining the type of
Instruction
• The timing signal active after
decoding is
• During this time, the control
unit determines the type of
instruction read from the
memory using the flowchart
• The cases are symbolized
here:

8
Register-Reference
Instructions

IR(7800)

9
Memory-Reference
Instructions

10
Effective Address
• Based on the flowchart discussed
before, effective instruction address is
placed in AR either during timing signal
• The M-R execution starts hence at
• The actual execution of each
instruction requires sequence of
microoperations since data in memory
cannot be directly processed without
reading it in some register where logic
circuits can work on it
• The required decoded output from
operation decoder for each operation
is shown

11
AND to AC

12
ADD to AC

13
LDA: Load to AC

14
STA: Store AC

15
BUN: Branch
Unconditionally

16
BSA: Branch and Save Return
Address

𝐷5 𝑇 4 :

17
BSA Example
• Return Address: 21
• BSA instruction
performs function
called subroutine call
• BUN instruction at the
end of the SR performs
SR return
• In many processors,
the return address
saved either in
processor register or
memory portion called
stack
• Note that BUN do:

18
ISZ: Increment and Skip if
Zero

19
Control Flowchart: M-R
Instructions

20
Next Time
• Basic Computer Organization and Design
o Input-Output and Interrupt
o Complete Computer Description
o Design of Basic Computer

21

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