CE 222: Computer

Organization and
Assembly Language
Basic Computer Organization and Design

Dr. Abbas Ahmed

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Announcement
• Assigment-2 uploaded on MS Teams
o Deadline of submission: Monday 17th Oct during class
• Quiz-2 to take place on Thursday during class
o Topic: Problems from Chapter-4

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Outlines
• Timing and Control
• Instruction Cycle
• Memory-Reference Instructions

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References
• Chapter 5, Morris Mano, “Computer System
Architecture”

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Timing and Control

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Clock Pulses
• Timing for all registers controlled by a master clock
o Applied to all registers and FFs in the system including
those in the control unit
• The clocks change the registers states’ only when
they are enabled by a control signal generated by
the control unit
• Control inputs provided to the MUXes in the
common bus, control inputs in processor registers
and microoperations for the accumulator

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Hardwired vs Microprogrammed
Control
• Hardwired control logic implemented with gates,
FFs, decoders etc and can be optimized to produce
a fast operation
o Disadvantages are that wiring changes required for
modifications
• In microprogrammed organization, the control
information stored in a control memory that
initiates the desired sequence of microoperations
o Modifications can be done by updating the
microprogram in the control memory

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Control Unit

• 3x8 decoder to decode the opcode part of

the IR i.e. . Also called Operation decoder
• I bit transferred to the FF designated I
• Bits 0 to 11 applied to control logic gates
• Another 4x16 decoder takes in the 4-bits
(count from 0000 to 1111) from SC output
and use it to produce the timing signals
• SC can be incremented (INR) or cleared
(CLR) synchronously with the Clock

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Sequence Counter: Timing
Signals
• SC produces signals in sequence
until at ( applied to CLR input of
SC) thus causing to get high at
next +ive clk edge ()

• SC responds to +ive Clk transition

• The +ive clock transition
designated triggers only those
registers with control inputs
connected to timing signal
• Last three waveforms indicate the
sequence in with SC gets cleared

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Memory Read/Write
• A memory read/write cycle initiated at rising edge of a
timing signal
• It is assumed that the memory R/W cycle time is smaller
than the clock cycle time i.e. when initiated by timing
signal, it is completed before next +ive clock edge arrives
• The clock transition then used to load memory word into
a register
• In many processors, memory cycle longer than the
processor clock cycle
o In that case, additional wait cycles necessary until the
memory word is available

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Timing signals vs Clock
Transition

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Instruction Cycle

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Instruction Cycle
• In the basic computer, each instruction cycle
consists of the following phases:
1. Fetch instruction from memory
2. Decode it
3. Read effective address from memory incase of indirect
address
4. Execute the instruction
• After step 4, control goes back to step 1
• The process repeats indefinitely unless a HALT
instruction is encountered

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Fetch and Decode
• The microoperations for the fetch and decode
phases can be specified by the following register
transfer statements:

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Register Transfer: Fetch
Phase

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Determining the type of
Instruction
• The timing signal active after
decoding is
• During this time, the control
unit determines the type of
instruction read from the
memory using the flowchart
• The cases are symbolized
here:

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Register-Reference
Instructions

IR(7800)

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Memory-Reference
Instructions

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 Effective Address
• Based on the flowchart discussed
before, effective instruction address is
placed in AR either during timing signal
• The M-R execution starts hence at
• The actual execution of each
instruction requires sequence of
microoperations since data in memory
cannot be directly processed without
reading it in some register where logic
circuits can work on it
• The required decoded output from
operation decoder for each operation
is shown

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AND to AC

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ADD to AC

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LDA: Load to AC

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STA: Store AC

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BUN: Branch
Unconditionally

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BSA: Branch and Save Return
Address

𝐷5 𝑇 4 :

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BSA Example
• Return Address: 21
• BSA instruction
performs function
called subroutine call
• BUN instruction at the
end of the SR performs
SR return
• In many processors,
the return address
saved either in
processor register or
memory portion called
stack
• Note that BUN do:

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ISZ: Increment and Skip if
Zero

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Control Flowchart: M-R
Instructions

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Next Time
• Basic Computer Organization and Design
o Input-Output and Interrupt
o Complete Computer Description
o Design of Basic Computer

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