Overview of 8086 Microprocessor

8086 Microprocessor is an enhanced version of 8085 Microprocessor that

was designed by Intel in 1976. It is a 16-bit Microprocessor having 20
address lines and 16 data lines that provides up to 1MB storage. It consists
of powerful instruction set, which provides operations like multiplication and
division easily.
The most prominent features of a 8086 microprocessor are as follows −
 It has an instruction queue, which is capable of storing six instruction bytes
from the memory resulting in faster processing.
 It was the first 16-bit processor having 16-bit ALU, 16-bit registers, internal
data bus, and 16-bit external data bus resulting in faster processing.
 It uses two stages of pipelining, i.e. Fetch Stage and Execute Stage, which
improves performance.
 Fetch stage can prefetch up to 6 bytes of instructions and stores them in the
queue.
 Execute stage executes these instructions.
 It has 256 vectored interrupts.
 It consists of 29,000 transistors.
 Difference between 8085 and 8086 Microprocessor
1. Size − 8085 is 8-bit microprocessor, whereas 8086 is 16-bit
microprocessor.
2. Address Bus − 8085 has 16-bit address bus while 8086 has 20-bit
address bus.
3. Memory − 8085 can access up to 64Kb, whereas 8086 can access up to 1
Mb of memory.
4. Instruction − 8085 doesn’t have an instruction queue, whereas 8086 has
an instruction queue.
5. Pipelining − 8085 doesn’t support a pipelined architecture while 8086
supports a pipelined architecture.
6. I/O − 8085 can address 28 = 256 I/O's, whereas 8086 can access 216 =
65,536 I/O's.
7. Cost − The cost of 8085 is low whereas that of 8086 is high.
Why do we need 8086 microprocessor?
 The 8086 is a more advanced, efficient and fast operating microprocessor
then 8085.
 Internal Block Diagram of the 8086
Internal block diagram has been partitioned into two logical units; CS
ES/DS SS
(1) the Bus Interface Unit (BIU) (2) the Execution Unit (EU)
ADDRESS BUS
AH(8)
BH
AL(8)
BL
AX
BX Data
∑ ❑ 20 bits
CH CL registers
CX
DH DL DX
ES segment
SP (16 bit) registers
CS
BP(16 bit) Address 8
registers SS
SI(16 bit) 0
DS 8
DI(16 bit)
IP 6
BUS
CONTROL
B
UNIT
16 bits U
S
TEMPORARY REGISTERS INSTRUCTION QUEUE
EU
ALU CONTROL 1 2 3 4 5 6
UNIT 8 bits
FLAGS
EXECUTION UNIT (EU) BUS INTERFACE UNIT (BIU)
 The Execution Unit (EU)
EU contains the arithmetic and logic unit (ALU), the control unit, an internal
bus, plus a few registers
Register sets:
AX AH AL ACCUMULATOR
BX BH BL BASE REGISTER
CX CH CL COUNT REGISTER
DX DH DL DATA REGISTER
SP STACK POINTER
BP BASE POINTER
SI SOURCE INDEX
DI DESTINATION INDEX
IP INSTRUCTION POINTER
FLAGH FLAGL STATUS FLAG
CS CODE SEGMENT REGISTER
DS
DATA SEGMENT REGISTER
SS STACK SEGMENT REGISTER
ES EXTRA SEGMENT REGISTER
 The Execution Unit
It contains the arithmetic and logic unit (ALU), the control unit, an internal bus, plus a few
registers
Register sets:
8086 has four 16-bit general-purpose registers labeled as AX, BX, CX and DX. Each of these
registers can also be used as two separate and exclusive 8-bit registers also i.e., AX has two
parts AH and AL, where H and L stands for the high and low portions respectively.
AX: AL /AX is sometimes called the accumulator, but the relevance of the accumulator is less
for 8086 compared to the earlier 8085 in which one operand is implied to be in the A register
for many instructions.
BX, CX and DX:
These are the other working registers of the 8086, which means that temporary data storage,
arithmetic calculations and data manipulation can be done with these registers
Base register BX is frequently used as an address register in many based addressing modes.
Counting register CX is used as a counter in many instructions.
Data register DX is used in I/O instructions as a pointer to data by storing the address of the I/O
port.
Pointer and Index Registers : SP, BP, SI and DI are address registers, and can be used only as
16-bit registers
BP and SP : They are the Base pointer and Stack pointer respectively. SP always points to the
top of the stack, while BP can point to any location in the stack.
SI and DI These are Index registers, labeled as Source Index and Destination Index respectively.
They function as address registers in various addressing modes
 The Execution Unit contd..
Flag Register
It is a 16-bit register, of which 7 bits are unused. 6 bits are used as conditional flags. The
others are control flags. The conditional flags available are the Carry (CF), Zero (ZF), Parity
(PF), Overflow (OF) and the Sign Flag (SF).

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

× × × × OF DF IF TF SF ZF × AF × PF × CF

OF=1 if PF=1 if there is

i) there is an overflow into even number of
SF=1 if the result
the MSB (8th or 16th bit) 1s in lower 8-bits
contains a
from the bit of lower
negative number
significance, but no carry AF =1 if there
out from the MSB, CF=1 if there
ZF=1 if is carry from is a carry out
ii) there is a carry out from bit D3 into D4.
the MSB, but no carry into arithmetic or from the
the MSB. logic operation MSB
is zero,
Flag register:
Control flag
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

× × × × OF DF IF TF SF ZF × AF × PF × CF

This flag is specifically Interrupt Flag (I) – Trap Flag (T) –If TF=1,
used in string This flag is for the CPU automatically
instructions. interrupts. generates an internal
If DF=1, then access If IF=1, the interrupt after each
the string data from microprocessor will instruction, allowing a
higher memory recognize interrupt program to be inspected
location towards lower requests from the as it executes instruction
memory location. peripherals. by instruction.
If DF=0, then access If IF=0, the If TF=0, no function is
the string data from microprocessor will performed.
lower memory not recognize any
location towards interrupt requests and
higher memory will ignore them.
location.
 The Execution Unit contd..
Solved Example on carry Flag
Q. Find the status of the flags CF, SF, AF after the following instructions are executed.
MOV AL, 35H
ADD AL, 0CEH
35H 0011 0101
+ CEH 1100 1110
103H 1 0000 0011
CF = 1 since there is a carry out from D7.
SF = 0 since the sign bit (MSB) of the 8-bit destination is 0.
AF = 1 since there is an overflow from D3 to D4.

Control Flags There are three control flags ; the Trap flag, Direction flag &Interrupt flag. The
control flags have to be deliberately set or reset according to the requirements of the
program. The Trap flag (TF) is set to perform step by step execution, during debugging. The
Interrupt flag (IF) is set to enable interrupts. The Direction flag (DF) is used in string
operations.

Arithmetic Logic Unit It is the part of a computer that performs all arithmetic and logic
computations. The ALU is the most important unit of the processor. Instructions that are
fetched and decoded, are executed in the ALU. Thus the ALU has direct access to the general
purpose registers and flags.
 Bus Interface Unit (BIU)
This unit BIU is responsible for address calculations, pre-fetching instructions for the
queue and sequencing instructions one by one.
The Instruction Queue
 Instructions are found in memory, from where they are fetched and decoded as
and when they need to be executed.

 However in 8086, there is a queue which fetches instructions ahead of the

execution time and places them in a 6-byte first-in-first-out (FIFO) queue. This pre-
fetching is done when the buses are free i.e., not being used for the execution of
the current instruction.

 The advantage of pre-fetching is that when a particular instruction is to be

executed, there is a good chance of finding it in the queue (which is on-chip),
rather than having to go to memory to fetch it.

 This pre-fetching belongs to a class of ideas called pipelining, which means that
both execution and fetching take place at the same time i.e., while the execution
of one instruction is going on, the fetching of another one can be done.

 Pipelining greatly speeds up processing.

 Concept of Pipelining
8086
2000 06 MVI BL, 78H
2001 78
2002 3E MVI AL,F2H
2003 F2
2004 80 ADD BL AL=AL+BL
8085 2005 76 HLT

Pre-fetching of next opcode is done

Opcode fetch
Decode and
Decode
execution of first 3E F2 80 76 ---- ----
Execute instruction code 06
78 in ALU 6-byte Instruction queue

EU
BIU

Processor
 Memory Segmentation
The stack is used to keep aside address and data
temporarily, when a subprogram is called
Base address Extra segment use to store data in a special way
SS
A0000H
Segment Register
ES These registers are all 16-
90000H A000H SS
bit in size. Each register
9000H ES stores the base address of
7000H DS the corresponding
DS Segment.
70000H 5000H CS

Total 216=65,536=64K address

locations & each location can
CS store 1 byte data
50000H

Data segment use to store data

The code segment contains code only
50000H= 0101 0000 0000 0000 0000 20 bit address
Calculation of a physical address from the logical address for a data segment
Let a data byte is stored in a data segment, whose base address is 22220H.
Then the data segment register (DS) will contain the number 2222H.
The data at any location within this segment is referenced by an offset
(displacement) with respect to the base address.
Thus, if a data at a location has a logical address specified as 2222H : 0016H, the
number 0016H is the off set or displacement with respect to the base address.
Example for physical address calculation see figure given below

Address byte
22236H
-
Physical address -
=22220H + -
0016H - Data
22236H
OFFSET=0016H (displacement) Segment
BYTE-2
BYTE-1
Base address
BYTE-0 2222H DS Register
22220H
 Memory Segmentation contd…
The Code Segment and the Instruction Pointer
 The code segment is the area of memory where code alone is stored.
 The offsets within the code segment are referenced using the Instruction Pointer (IP),
which is a 16-bit register.
 The IP sequences the instructions, and always points to the next instruction to be
executed.
 Whenever an instruction byte has to be fetched from memory, the bus interface unit (BIU)
performs the address calculation using the contents of CS register and the IP.
 This 20-bit address is then placed on the address bus and the instruction byte is fetched.
Thus the logical address for an instruction bye is of the form CS : IP.
Example Address byte
The contents of the following segment registers are as -
given. -
CS = 1111H -
-
IP = 1232H.
Calculate the corresponding physical addresses for the BYTE-2
addressed byte in a) CS BYTE-1
Base address
Ans: The base address of the code segment is 11110H. 11110H BYTE-0 1111H
The address of the next instruction to be CS Register
executed is referenced by CS and IP which is given by
11110H + 1232H = 12342H.
 Memory Segmentation contd…
The Stack Segment and the Stack Pointer
 The stack is an area of memory that is used in a special way.
 There is a 16-bit register called Stack Pointer (SP) which points to the top of the stack.
 The upper 16 bits of its base address is available in the SS register.
 A stack address of the form 4466H : 0122H means that the SS register contains 4466H, the
stack pointer (SP) contains the number 0122H, and the physical address of the top of the
stack is 44660H + 0122H = 44782H
 The 8086 has a stack which grows downwards (i.e., to lower memory addresses).
 Thus the format SS : BP is also a logical address.
 Memory Segmentation contd…
The Data Segment and Extra Segment
 Both these segments store data, but in certain special cases (string instructions),
it may be necessary to list them separately.

 There is an Extra Segment (ES) register to store the upper 16 bits of the base
address of the extra segment.

 The offset within the data segment is also termed as an ‘effective address’.

 The effective address calculation depends on the mode of addressing.

Table Segments and Corresponding Registers Used for Specifying Offsets
Segment Offset Registers Function
CS IP Address of the next instruction
DS BX, DI, SI Address of data
SS SP, BP Addresses in the stack
ES BX, DI, SI Address of destination data
(for string instructions)
 Memory Segmentation contd…
Advantages of Segmentation

1. It allows all address registers to have the same size as the data registers (16-bit),
while allowing the use of 20-bit physical addresses.

2. All addresses in memory are re-locatable. This means that any program or data
can be loaded in any address in memory. A re-locatable program is one which
can be placed in any area of memory and executed without change. Data is also
re-locatable. Changing the base address of the corresponding segment is the
only action we need to perform, in order to re-locate. All addresses within the
program are relative to the base address, as they are of the form Base address:
off set. All processors in the x86 family have this kind of segmentation.
 Addressing Modes
For computations in assembly language, we need an opcode and operands
The way in which operands are specified in an assembly language instruction is called its
addressing mode.
Let us use the MOV instruction for understanding these modes. This has the format
MOV destination, source ………. source data is copied into the destination.

The basic assumptions in this context are

1. the operands can be in registers, in memory, or may be in the instruction itself. However
the 8086 does not have an addressing mode in which both operands are in memory
locations,
e.g. MOV [3456H], [3001H] --------------is wrong.
2. in the case of two operands, one of them can be in memory, but the other will have to be
placed in a register,
e.g. MOV [3456], BX ----------is right.
3. data types should match – i.e., the source and destination should both be either bytes or
words.
 Addressing Modes contd…
1) Register Addressing

Here both the source and destination are registers. No memory access is involved.
See the following instructions.
MOV AL, AH ;copy the content of AH to AL
MOV CH, BL ;copy the content of BL to CH

MOV SI, BX ;copy the content of BX to SI

MOV ES, AX ;copy the content of AX to ES
Note that the first two are byte operations, while the other two are word
operations.
MOV AX, BL ;gives an error as AX is 16 bit and BL is 8 bit
MOV BL, AX ;gives an error for the same reasons
 Addressing Modes contd…
2) Immediate Addressing
In this mode, the source will be a constant data
MOV AL, 45H ;copy 45H to AL
MOV BX, 34E3H ;move the hex number 34E3H to BX
MOV CL, ‘Q’ ;move the ASCII value of Q to CL
MOV PRICE, 40 ;move the hex number 40 to the memory location with label
PRICE
MOV NUMS, 0FC6H ;move the hex number 0FC6H to the memory location NUMS
Segment registers are not allowed to use this mode of addressing.
MOV DS, 2300H ;gives an error as DS is a segment register
 Addressing Modes contd…
3) Direct Addressing
Here either the source or the destination will be a memory address.
MOV AX, [2345H] ;move the word in location 2345H into AX
MOV [1089H], AL ;the byte in AL is moved to location 1086H
It is to be remembered that the addresses in the instructions are off sets within the data
segment (i.e., the logical address). We need to know the content of DS to calculate the
physical address.
The size of the registers indicate the size of the operand. Hence, in the first instruction, a
data word is referred to; while in the second, a data byte is moved. The square brackets are
necessary to indicate that the number is an address and not data. However, we may use
labels for addresses, and re-write the above two instructions.
MOV AX, PRICE
MOV COST, AL
We must then ensure that the referred addresses have been defined earlier with these
labels.
 Addressing Modes contd…
4) Register Indirect Addressing
In this mode, the address of the data is held in a register. The register acts as a
pointer to the data.
The registers must be enclosed in square brackets to indicate that they function as
pointers. We also use the term effective address for the address of the operand.
For this mode of addressing, the address registers allowed are BX, SI and DI.
EA = {[BX]/[DI]/[SI]}
MOV AL, [BX] ;move into AL the content of the location whose address is in BX
MOV [SI], CL ;move the content of CL to the address pointed by SI
MOV [DI], AX ;move the content of AX to the address pointed by DI
In the third instruction, AX contains two bytes. Hence the content of AL will be
moved to the
address pointed by DI. The content of AH will be moved to the address [DI + 1].
 Addressing Modes contd…
5) Register Relative Addressing
In relative addressing mode, a number or displacement is part of the effective address.
EA = {[BX]/[DI]/[SI]/[BP]} + 8-bit or 16-bit displacement
MOV CL, 10[BX] ;move the content of the address specified by adding the content of BX & 10.
Thus the effective address is [BX + 10 ]. Once the effective address is computed, the physical
address is calculated as the sum of the segment base address and the effective address. The
displacement can be a 16-bit signed/unsigned number or an 8-bit sign extended number.
However the displacement should not be so large as to make the effective address go beyond
the range of the maximum size of a segment. The above instruction can also be written as
MOV CL, [BX + 10]
MOV CL, [BX] + 10 or
MOV CL, [BX][10] or
MOV CL, PRICE [BX]
In the last case, PRICE has to be defined earlier as a displacement of 10.
 Addressing Modes contd…
6) Based Indexed Mode
In this mode, an index register and a base register together carry the effective
address. The content of these two registers are added and called the effective
address.
MOV AL, [BX][SI] ;move the content of the effective address pointed by [BX] and [SI]
into AL
The effective address is obtained by adding the content of BX and SI. Since the
destination register is an 8-bit register, this is a byte operation. The following is a
word operation as the source register CX is 16-bit in size.
MOV [BX][DI], CX ;move the content of CX to the effective address pointed by [BX]
and [SI]
 Addressing Modes contd…
7) Relative Based Indexed Mode
This is the case when the ‘effective address’ is specified with a base register, an
index register as well as a displacement. The ‘effective address’ is the sum of the
two registers and the displacement.
For example, the following use the relative-based indexed mode of addressing
MOV DL, 5[BX][DI] ;EA = 5 + BX + DI
MOV 5[BP][SI], AX ;EA = 5 + BP + SI
MOV CL, COST[BX][SI] ;EA = COST + BX + SI ;COST has to be defined as a
displacement earlier
Table Effective Address and Referred Segments for Various Memory Based Addressing Modes
S. No. Addressing Mode Effective address Segment

1. Direct Offset DS

2. Register Indirect [BX] DS

[SI] DS
[DI] DS
3. Register relative Disp + [BX] DS
Disp + [SI] DS
Disp + [DI] DS
Disp + [BP] SS
4. Based Indexed [BX] + [SI] DS
[BX] + [DI] DS
[BP] + [SI] SS
[BP] + [DI] SS
5. Relative Base Indexed Disp + [BX][SI] DS
Disp + [BX][DI] DS
Disp + [BP][SI] SS
Disp + [BP][DI] SS
Example :
Find the address of physical memory for the following
instructions if the content of the required registers are as
given below
SS = 2344H, DS = 4022H, BX = 0200H, BP = 1402H, SI =
4442H
CL=0101 0000 after executing MOV CL,
i) MOV CL, 1234H[SI] 1234H[SI]
ii) MOV AL, 5[SI][BP]
Solution
i) MOV CL, 1234H[SI] Data segment
This is a case of register relative addressing. The effective 0101 0000 45896H
address is obtained from the instruction, to be the sum of
the displacement and SI
Effective address = 1234H +
4442H
5676H DS=40220H
The segment base address is obtained from DS to be 40220H
Base address
The physical address is the sum of the segment base
address and the effective address. i.e.,
40220H = starting address
5676H= Effective address (offset value)
45896H=Physical address
ii) MOV AL, 5[SI][BP]
This is a case of relative based indexed mode. The effective address is calculated as
the sum of the displacement and the contents of the registers SI and BP.
Effective address = 0005H +
4442H
1402H
5849H= Effective address (offset value)
The physical address is the sum of the segment base address and the effective
address. In this case, as BP is one of the address registers, the segment referred is
the stack segment.
Physical address is 23440H (base address of the stack segment)
+ 5849H
28C89H= Physical address
 Example :
The content of DS is 345BH. The amount of data that
is to be stored in the data segment is Data segment memory chip
12K bytes. Where in memory, will this segment be
Last address
located?
375B0H
Solution
DS contains the number 345BH.
This number corresponds to the upper 4 hex digits of 12×1024
the starting (base address) of the data =12288
segment.
The base address of the segment is 345B0H.
The last address will have an off set of 12K from the
base address. 345B0H
1K = 1024 bytes. Base address
12K = 12 × 1024 = 12288 = 3000H.
The last address of the segment = 345B0H + 3000H =
375B0H.
Hence the data segment occupies the memory
addresses from 345B0H to 375B0H
 Segment Override Prefix
 The segment override prefix allows the programmer to deviate from the default
segment and offset register mechanism.
 The segment override prefix is the additional byte that appears in at the beginning
of an instruction, to select an alternative segment register.
Example:
MOV AX, [BP] access data within the stack segment by default.
But MOV AX, DS:[BP] access data within the data segment …..segment override prefix
Table: Instructions that include the segment override prefix
Instruction Default segment Accessed
segment
MOV BX, ES:[BP] SS ES
MOV BX, SS:[DI] DS SS
MOV CX, ES:[BP] DS ES
MOV CX, ES:[BP] DS ES
MOV AX, CS:[BP] DS CS
 Instruction Set of 8086
Instructions of 8086 are classified as
1. Data transfer instruction
2. Arithmetic Instruction
3. Logical Instruction
4. Flag manipulation instruction
5. Control transfer instruction
6. Shift/Rotate
7. String Instruction
8. Machine control instruction
 Instruction Contd..
1. Data transfer instructions
The data transfer instruction are MOV, PUSH, POP, XCHG, IN, OUT, LEA, LDS, LES,
LSS, LAHF and SAHF
MOV mem AL/AX
PUSH r/mem
POP r/mem : The data present in the stack memory is transferred to either 16-bit
register or memory location given in the operand and SP gets incremented by 2
XCHG r2/mem, r1:
IN A, DX : The data present in the input port is transferred to accumulator and its address is present
in the DX register given in the operand
IN A, addr8 : The data of the input port is moved to the accumulator whose memory address
is given in the instruction
OUT DX, A: The data in the accumulator is moved to the output port whose
address is specified in the DX register
OUT addr, A : The data in the accumulator is moved to the port whose address is
given in the instruction
LEA r, mem : This instruction loads the register with the effective address of the
memory location
LDS r, mem: The data is in the first two memory location is moved to the register
and from the next two memory locations is moved to DS register
LAHF: The lower byte of the data of the flag register is moved to the higher byte register of
the accumulator
 Instruction Contd..
1. Data transfer instructions
I. MOV :
This instruction copies a byte or word from source to destination.
The Source can be register, memory or immediate data.
The destination can be a register or a memory location
Format: MOV destination, source
Example:
MOV BL, 50H ; Move immediate data 50H to BL
MOV CX, [BX] ; Copy the word from memory at [BX] to CX.
MOV AX, CX ; Copy the content of CX to AX
Note: [BX] indicates the memory location at the offset address specified by BX in
the data segment.
 1. Data transfer instructions contd…
II. PUSH :
The PUSH instruction is used to store the word in a register or a memory location
into the stack.
SP is decremented by two after the execution of PUSH
Example:
PUSH CX;PUSH the content of CX into the stack
PUSH DS; PUSH the content of DS into the stack
PUSH [BX]; PUSH the word in memory at [BX] into the stack
Stack segment
Stack segment Let the content of [SP]=24004H
CX=5643H
[SP]=24004H 56H [SP-1]=24003H
Let us assume that the top
[SP-1]=24003H of the stack has memory [SP-2]=24002H
43H
[SP-2]=24002H address as 24004H
So, [SP]=24004H
After execution of
Before execution PUSH CX
of PUSH CX
 1. Data transfer instructions contd…
III. POP :
The POP instruction copies top word from the stack to a destination specified in the
instruction.
The destination can be a general purpose register, a segment register, or a memory
location.
SP is incremented by two after the execution of POP
Example:
POP BX ; POP the content of BX from the stack
POP DS ; POP the content of DS from the stack
POP [SI] ; POP a word from the stack and store it in the memory at [SI]
Stack segment
Let the content of
[SP]=24004H [SP-1]=56H BL=43H ; first the content is
[SP-1]=24003H [SP-2]=43H copied into low-order register
56H
[SP-2]=24002H Let us assume that the top BH=56H ; SP is incremented by 1
43H of the stack has memory and then content is copied in
address as 24004H high-order register
So, [SP]=24004H
Before execution After execution of
of POP BX POP BX
PUSH & POP instruction in 8085 (Extra slide)
Where is PUSH and POP instruction used?

Multiple-calling for a subroutine

 1. Data transfer instructions contd…
IV. XCHG :
The XCHG instruction exchanges the contents of a register with the contents of a
memory location.
It can’t exchange the content of two memory locations directly.
The segment register can’t be used in this instruction.
Example:
XCHG AL, BL; Exchange the content of AL and BL
XCHG CX, BX; Exchange the content of CX and BX
XCHG AX, [BX] ; Exchange the content of AX with the content of the memory [BX]

v. XLAT :
 IN and OUT instructions

monitor Processor keyboard

output device Input device

OUT instruction is used IN instruction is used
 1. Data transfer instructions contd…
vi. IN:
The IN instruction copies data from a port to the AL or AX register.
The IN instruction has two formats--- fixed port and variable port.
In fixed port type IN instruction, the 8-bit address of a port is specified directly in the
instruction. With this form, any one of 256 possible ports can be addressed.
Example:
IN AL, 80H ; Input a byte from the port with address 80H to AL
IN AX, 40H ; Input a word from the port with address 40H to AX
For the variable port type IN instruction, the port address is loaded into DX register before
the IN instruction. Since DX is 16-bit register, the port address can be any number between
0000H and FFFFH. Hence, it is possible to address 65,536 ports in this mode.
Example:
MOV DX, 0FE50H ; Initialize DX with the port address of 0FE50H
IN AL, DX ; Input a byte from the 8-bit port with port address 0FE50H into AL
IN AX, DX ; Input a word from the 16-bit port with port address 0FE50H
The drawback of fixed address is that the port address can’t be changed once the program is
stored in ROM
vii. OUT:
The OUT instruction transfer a byte from AL or a word AX to the specified address port. This
instruction has also two types—fixed port and variable port.
Ex: OUT 48H, AL ; Sends the content of AX to the port with address 48H.
 1. Data transfer instructions contd…
viii. LEA (Load effective address):
Format : LEA register, source.
This instruction determines the offset address of the variable or memory location called
source and puts this offset address in the indicated 16-bit register.
Example:
a) LEA CX, COST ; Load CX with the offset address of COST in the data segment, where
COST is the name assigned to a memory location in the data segment
b) LEA CX, [BX][SI] ; Load CX with the content which is stored in the effective address
[BX]+[SI]

ix. LDS :
This instruction loads the register and DS with words from the memory.
Format: LDS register, memory address of first word
The LDS instruction copies a word from the memory location specified in the instruction into
the register, and then copies a word from the next memory location into the DS register.
LDS instruction is useful in initializing the SI and DS register at the start of a string before
using one of the string instruction.
Example: [2000H]
LDS SI, [2000H] ; SI= [2001H]
[2002H]
DS= [2003H]
 1. Data transfer instructions contd…
x. LES and LSS:
The LES and LSS instructions are similar to the LDS instruction, except that instead of the DS
register, the ES and SS registers are loaded, along with the register specified in the instruction

xi. LAHF:
This instruction copies the lower-byte of the flag register into AH.

FLAG register AH AL

AX
xii. SAHF:
This instruction copies the content of AH in the lower-order byte of the flag register.

FLAG register AH AL

AX
 2. Arithmetic Instructions
The arithmetic instructions in 8086 are used to perform
o Addition
o Addition with carry
o Subtraction
o Subtraction with borrow
o Increment
o Decrement
o Negation (changing sign)
o Comparison
o Multiplication
o Division
o Decimal-adjust after addition
o Decimal-adjust after subtraction
o Processing of ASCII data
 2. Arithmetic Instructions contd..
i. ADD:
Format: ADD destination, source
The source may be immediate number, register or a memory location.
The destination can be register or a memory location.
Note: Source and destination both cannot be memory location.
Example:
ADD BX, 80H ; Add the immediate data 80H to BL.
ADD CX, 12B0H ; Add the immediate data 12B0H to CX.
ADD AX, CX ; Add the content of AX and CX and store the result in AX.
ADD AL, [BX] ; Add the content of AL and the byte from the memory at [BX] and store
the result in AL.

ii. ADC:
This instruction add the data source and destination with the content of carry flag and
stores the result in the destination.

iii. SUB:
Format: SUB destination, source
It subtract the number in source from number in the destination and stores the result in
destination.
Example:
SUB AL, BL ; Subtract BL from AL and store result in AL
Example of ADC
 2. Arithmetic Instructions contd..
iv. SBB: Subtract with borrow
Format: SBB destination, source
The SBB instruction subtracts the content of the source and carry flag from the content of
the destination and stores the result in the destination.

In this above example, the subtraction of 62H and F1H will result in 71H with a borrow
of 1. Next, we have to subtract 44H and 13H along with this borrow value of 1.
To facilitate this, SBB instruction has been provided to subtract two numbers along with
the borrow value
SBB E as an example instruction of this type Before After
Let us suppose, Accumulator’s
(E) 13H 13H
initial content is 44H and E
register’s initial content is 13H and (A) 44H 30H
Cy is set to 1
 2. Arithmetic Instructions contd..
v. INC:
The increment (INC) instruction adds 1 to the content of a specified register or a
memory location.
Example:
INC CL; Increment the content of CL by 1.
INC BYTE PTR [BX] ; Increment the byte in the memory at [BX] by
1.
INC WORD PTR [SI] ; Increment the word in the memory at [SI] by 1.
In these examples the term BYTE PTR and WORD PTR are assembler directives,
which are used to specify the type of data (byte or word) to be incremented in
the memory.

vi. DEC:
The decrement instruction subtract 1 from the content of a specified register or
memory location.

vii. NEG:
The negate instruction replaces the byte or word in the specified register or
memory location by it’s 2 compliment (i.e. changes the sign of a data)
 2. Arithmetic Instructions contd..
Example:
NEG AL ; Take 2’s compliment of the data in AL and store it in AL.
NEG BYTE PTR [BX] ; Take 2’s complement of the byte in the memory at [BX] and store
the result in the same place.
NEG WORD PTR [BX] ; Take 2’s complement of the word in the memory at [SI] and store
the result in the same place.

viii. CMP:
Format; CMP destination, source
This instruction compare a byte or word in the source with a byte word in the destination.
The comparison is done by subtracting the content of source from that of the destination.
Example:
After the instruction CMP AX, DX is executed, the status of CF, ZF and SF will be as follows

CF ZF SF
If Ax=DX 0 1 0
If AX>DX 0 0 0
If AX<DX 1 0 1
 2. Arithmetic Instructions contd..
ix. MUL:
The multiply instruction is used for multiplying two unsigned bytes or words.
Format: MUL source
The source can be memory location or register which is considered as multiplier.
The multiplicand is taken by default from AL and AX for byte and word type data
respectively.
Note: The result of multiplication is stored in AX for byte data type.
For the word data type, the result of multiplication is stored in AX-DX (i.e. the most
significant word of the result in DX and the least significant word of the result in AX)
Example: byte with byte multiplication
MOV AL, 23H 35×15=525=20DH;
MOV BH, FH After multiplication AX= 20DH
MUL BH
Example: word with word multiplication
The two words of 16-bits on multiplication can produce a 32-bit word.
Lower bytes of word are stored in AX and higher bytes are stored in DX
MOV AX, 90C3H
MOV BX, 12DAH 90C3×12DA=AA8FC0E;
MUL BX After multiplication AX=FC0E & DX=AA8
 2. Arithmetic Instructions contd..
x. IMUL
IMUL instruction are is used for multiplying the signed byte or word in a register or memory
location with AL or AX, and store the result in AX or AX-DX, respectively.
Example:
IMUL BL ; Multiply AL with BL and store the result in AX
IMUL AX ; Multiply AX with AX and store the result in DX-AX.

xi. DIV
The divide (DIV) instruction is used for dividing unsigned data.
Format: DIV source.
Source is a divisor which can be byte or word in a register or memory location.
The dividend is taken by default from AX and DX-AX for byte and word type data division.
Dividend Divisor Quotient Remainder
AX (16-bit) Source (8-bit) AL (8-bit) AH (8-bit)
DX-AX (32-bit) Source (16-bit) AX (16-bit) DX (16-bit)

Example:
DIV DL ; Divide the word in AX by the byte in DL. The quotient is stored in AL
and the remainder in AH
DIV CX ; Divide the double word (32-bits) in DX-AX by the word in CX. The
quotient is stored in AX and the remainder in DX
 2. Arithmetic Instructions contd..
xii. IDIV
The IDIV instruction is used for dividing signed data. The general forms and rules for IDIV is
same as those for DIV instruction.

xiii. DAA (Decimal-adjust after addition)

Decimal adjust AL after BCD addition- This instruction is used get result of addition of two
packed BCD numbers (in a packed BCD number, two decimal digits are represented as 8-bit)
as a BCD number. The result of addition must be in AL to work correctly.
Rule: If the lower nibble(four bits) in AL register is greater than 9 after addition or if AF flag is
set by the addition, the DAA instruction adds 6 to the lower nibble in AL. If the result in
upper nibble of AL is greater than 9 or if the carry flag is set by the addition, the DAA
instruction adds 60H to AL.
Example:
Let AL=01011000=58 BCD
CL=00110101=35 BCD
Consider the execution of following instructions:
ADD AL, CL; AL=100001101=8DH and AF=0 after execution
DAA : Add 0110 (decimal 6) to AL, since lower nibble in AL is greater than 9
: AL=10010011=93 BCD and CF=0
Therefore, the result of addition is 93 BCD.
 2. Arithmetic Instructions contd..
(b) Let AL=10001000=88 BCD
CL=01001001=49 BCD
Consider the execution of following instructions:
ADD AL, CL ; AL=11010001 and AF=1 after execution
; Add 0110 to AL
Al=11010111=D7H
Upper nibble 1101>9. So add 60H (0110 0000) to AL.
AL=0011 0111=37 BCD and CF=1
The final result is 137 BCD

xiv. DAS (Decimal adjust after BCD subtraction)

DAS is used to get the result in packed BCD form after subtracting two packed BCD numbers.
The result of subtraction must be in AL for DAS to work correctly. If the lower nibble in AL
after subtraction is greater than 9 or if AF is set by subtraction, the DAS instruction subtracts
6 from the lower nibble of AL. If the result in the upper nibble is now greater than 9 or if
carry flag is set, the DAS instruction subtracts 60H from AL.
Example:
(a) Let AL=86 BCD=1000 0110, CH=57 BCD=01010111
Consider the execution of following instructions:
SUB AL, CH ; AL=00101111=2F and CF=0 after execution.
DAS ; Lower nibble of the result is 1111. So DAS subtracts 06H from AL to
make AL=00101001=29 BCD and CF=0 to indicate that there is no borrow.
 2. Arithmetic Instructions contd..
(b) Let AL= 49 BCD=01001001
CH=72 BCD=01110010
Consider the execution of the following instructions:
SUB AL, CH ; AL=1101 0111=D7H and CF=1 since result is negative
DAS ; Subtract 0110 0000 (60H) from AL because upper nibble in AL is greater
than 9. This make AL=01110111=77 BCD and CF=1, indicating that a borrow is needed.

xiv. AAA (ASCII adjust after addition)

The AAA instruction must always follows the addition of two unpacked BCD operands in AL.
The AAA instruction must always follow the addition of two unpacked BCD operands in AL.
when AAA is executed, the content of AL is changed to a valid unpacked BCD number
 3. Logical Instruction
The logical instruction 8086 include AND, OR, XOR, NOT, and TEST
i. AND:
Format: AND destination, source
The AND instruction performs a logical AND operation between the corresponding bits in
the source and destination and stores the result in the destination.

ii. OR:
Format: OR destination, source
The OR instruction performs a logical OR operation between the corresponding bits in the
source and destination and stores the result in the destination.

iii. XOR:
Format: XOR destination, source
The XOR instruction performs a logical XOR operation between the corresponding bits in
the source and destination and stores the result in the destination.

iv. NOT:
The NOT instruction inverts each bit (i.e. performs 1’s compliment of the byte or word at a
specified destination). The destination can be register or a memory location.
Example:
NOT AL ; Take 1’s compliment of AL.
 3. Logical Instruction contd…
v. TEST:
This instruction ANDs the content of a source byte or a word with the content of the
specified destination byte or word. The TEST instruction is used to set flags before a
conditional jump instruction.
Format: TEST destination, source
Example:
Let AL=0111 1111=7FH
TEST AL, 80H ; AL=7FH (unchanged)
ZF=1 since (AL) AND (80H)=00H;SF=1
 4. Flag manipulation instruction
The 8086 has a few instructions exclusively for performing operations on the flags in the
flag register. They are used to set or clear specific flags in the flag register, to push or pop
the flag register content to the AH register and vice-versa. Following are flag manipulation
instructions in 8086:
LAHF: Load the low-order byte of the flag register in AH
SAHF: Store AH in the low-order byte of the flag register.
PUSHF: Push the flag register’s content onto the stack.
POPF: Pop the top word of the stack onto the flag register.
CMC: Compliment the carry flag.
CLC: Clear the carry flag (CF=0)
STC: Set the carry flag (CF=1).
CLD: Clear the direction flag (DF=0)
STD: set the direction flag (DF=1)
CLI: Clear the interrupt flag (IF=0)
STI: Set the interrupt flag (IF=1)
 5. Control Transfer instructions

Unconditional Transfer Instruction Conditional Transfer Instruction

 CALL
These instructions will cause a jump to a
 RET
label given in the instruction if the desired
condition(s) occurs in the program before
the execution of the instruction. If the jump
is not taken, Program Execution Transfer
Instructions in 8086 Microprocessor simply
goes on to the next instruction.
 Far CALL type
Example to show CALL instruction:
I am writing a program to add 2 number, multiply 2 numbers, divide 2 number.
Subroutine-1: Stack segment
Main program: Code segment 70000H MOV AL, 9H
20000H MOV AL, 9H 70001H
20001H 70002H MOV DL, 2H
20002H MOV BL, 6H 70003H
20003H 70004H MUL DL
20004H CALL 70000H 70005H RET
20005H ADD BL
20006H CALL 6000H
60000H MOV AL, 9H
20007H
60001H
60002H MOV CL, 2H
Main program and
subroutine are written in 60003H
different memory 60004H DIV DL
segment: Far CALL 60005H RET
Subroutine-2
 Near CALL type

Main program: Code segment

20000H MOV AL, 9H
20001H Main program and
20002H MOV BL, 6H subroutine are written in
same memory segment:
20003H
Near CALL
20004H CALL 20007H
20005H ADD BL
20006H CALL 20007H
20007H MOV AL, 9H

MOV DL, 2H Subroutine

MUL DL
RET
 5. Control Transfer instructions contd…
Unconditional Transfer Instruction
1. CALL Instruction :
The CALL instruction is used to Program Execution Transfer Instructions in 8086
Microprocessor to a subprogram or procedure.

Near CALL Far CALL

o A near CALL is a call to a subroutine which o A far CALL is a call to a subroutine which is in
is in the same code segment as the CALL a different segment from that which contains
instruction. the CALL instruction.
o When the 8086 executes a near CALL o When the 8086 executes a far CALL it
instruction it decrements the SP and copies decrements the SP by two and copies the
the offset of the next instruction after the contents of the CS register to the stack. It
CALL on the stack. then decrements the SP by two again and
o It loads IP with the offset of the first copies the offset of the instruction ,after the
instruction of the subroutine in same CALL to the stack.
segment. o Finally, it loads CS with the segment base of
o The near CALL is also known as intra- the segment which contains the procedure
segment CALL and IP with the offset of the first instruction
of the procedure in that segment.
o The far CALL is also known as inter segment
CALL.
 5. Control Transfer instructions contd…
Unconditional Transfer Instruction
RET Instruction :
o The RET instruction will return Program Execution Transfer Instructions in 8086
Microprocessor from a procedure to the next instruction after the CALL instruction in
the calling program.
o If the procedure is a near procedure (in the same code segment as the CALL
instruction), then the return will be done by replacing the instruction pointer with a
word from the top of the stack.
o If the procedure is a far procedure (in a different code segment from the CALL
instruction which calls it), then the instruction pointer will be replaced by the word at
the top of the stack. The stack pointer will then be incremented by two. The code
segment register is then replaced with a word from the new top of the stack. After the
code segment word is popped off the stack, the stack pointer is again incremented by
two. These words/word are the offset of the next instruction after the CALL. So 8086
will fetch the next instruction after the CALL.
 5. Control Transfer instructions contd…
Unconditional Transfer Instruction
JMP Instruction :
o This instruction will always cause the Program Execution Transfer Instructions in 8086
Microprocessor to fetch its next instruction from the location specified in the instruction
rather than from the next location after the JMP instruction.
o There are two basic types of JMPs, near and far. A near JMP is a jump where destination
location is in the same code segment. In this case only IP is changed. A near JMP is known
as intrasegment JMP. A far JMP is a jump where destination location is from a different
segment. In this case both IP and CS are changed as specified in the destination. A far IMP
is known as Inter segment JMP
o Near and far jumps are further described as either direct or indirect. If the destination
address for the jump is specified directly within the instruction, then the jump is described
as direct. If the destination address for the jump is contained in a register or memory
location, the jump is referred as indirect, because the 8086 has to access the specified
register or memory location to get the required destination address.
 5. Control Transfer instructions contd…
Conditional Transfer Instruction
Instruction code Description Condition for Jump
JA/JNBE Jump if above/Jump if not below or equal CF=0 and ZF=0
JAE/JNB Jump if above or equal/Jump if not below CF=0 and ZF=1
JB/JNAE/JC Jump if below/Jump if not above or equal CF=1 and ZF=0
JBE/JNA Jump if below or equal/Jump if not above CF=1 and ZF=1
JE/JZ Jump if equal/Jump if zero flag ZF=1
JG/JNLE Jump if greater/Jump if not less than or equal ZF=0 and CF=0
JGE/JNL Jump if greater than or equal/Jump if not less SF=0
than
JL/JNGE Jump if less than/Jump if not greater than or SF0
equal
JLE/JNG Jump if less than or equal/Jump if not greater ZF=1 and SF0
JNC Jump if no carry CF=0 or CF
JNE/JNZ Jump if not equal/Jump if not zero ZF=0
 5. Control Transfer instructions contd…
Instruction code Description Condition for Jump
JNO Jump if no overflow OF=0
JNP/JPO Jump if no parity/Jump if parity odd PF=0
JNS Jump if not sign or Jump if not positive SF=0
JO Jump if overflow flag=1 OF=1
JP/JPE Jump if parity/Jump if even parity PF=1
JS Jump if sign flag=1 or Jump if negative SF=1
JCXZ Jump if CX is zero CX=0
Example: Accumulator has 50H stored in it. Count the number of 1s in the contents
Solution: AL=50H=0101 0000 has two 1s.
We have written program in which the count in register BL will give the numbers of 1s:
MOV AL, 50H Load the number in Accumulator AL
0 1 0 1 0 0 0 0 C
MVI BL, Initialize register B as a counter
00H with initial value 00H; BL0 CL=8
MVI CL, Initialize register C as a counter
0 0 1 0 1 0 0 0 0
08H for looping with initial value of
08H; CL8 CL=7
LOOP: SAR AL, 1 Rotate the content of the 0 0 0 1 0 1 0 0 0
accumulator right through carry
JNC NEXT If Carry bit is not 1, go to NEXT CL=6
0 0 0 0 1 0 1 0 0
INC BL If the bit is 1, increment BL
CL=5
NEXT: DEC CL Decrement counter CL 0 0 0 0 0 1 0 1 0
JNZ LOOP If the counter CL is not zero, CL=4
jump to loop
0 0 0 0 0 0 1 0 1
HLT Terminate program execution
CL=3
After Five number iterations of CL, the content of BL=1.
This process will continue until BL is not equal to 2
 5. Control Transfer instructions contd…
Iteration Control Instructions:
These instructions are used to execute a series of instructions some number of times.
The number is specified in the CX register. The CX register is automatically decremented
by one, each time after execution of LOOP instruction. Until CX = 0, execution will jump
to a destination specified by a label in the instruction.
Instruction code Description Condition for Exit
LOOP Loop through a sequence of instructions CX=0
LOOPE/LOOPZ Loop through a sequence of instructions CX=0 or ZF=1
LOOPNE/LOOPNZ Loop through a sequence of instructions CX=0 or ZF=1

The use LOOP instruction is explained with example:

MOV CX, 100 The loop starting
from the address
AGAIN:MOV AL, BL
AGAIN is repeated
…… 100 times since CX
is initialized to 100
LOOP AGAIN ; Decrement CX and if CX 0, go to AGAIN.
 6. Shift/Rotate
Shift/rotate instructions perform logical left shift and right-shift and arithmetic left-shift
and right-shift operations.

i. SAL/SHL:
Format: SAL/SHL destination, count
The designation can be register or a memory location and a byte or a word.
The instruction shifts each bit in the designation a specified number of bit position to the
left.
As a bit is shifted out of LESB position, 0 is placed in the LSB position. The MSB is shifted
into the carry flag (CF).
CF MSBLSB0
Example:
SAL AL, 1 ; shift left the content of AL by one bit.
AL
CF 0 1 0 1 0 1 1 0 0 Content of AL before SAL
CF before
SAL

0 1 0 1 0 1 1 0 0 Content of AL after SAL instruction

CF after SAL
 6. Shift/Rotate contd…
Note: Shifting a number by one bit and two bits multiplies the number by two and four,
respectively, and so on.
Example:
Let initial value of AL=1 0 0 0 0 0 0 0 1 AL=1
×2
×4
The content of AL after SAL, 1 0 0 0 0 0 0 1 0 AL=2

The content of AL after SAL, 2 0 0 0 0 0 1 0 0 AL=4

×8
The content of AL after SAL, 3 0 0 0 0 1 0 0 0 AL=8
 6. Shift/Rotate contd...
ii. SAR:
Format: SAR destination, count
The designation can be register or a memory location and a byte or a word.
The instruction shifts each bit in the designation a specified number of bit position to the
right.
As a bit is shifted out of MSB position, a copy is put into the MSB position (i.e. sign bit is
copied into the MSB). The LSB is shifted into the carry flag (CF).
MSB MSBLSBCF

Example:
SAR AL, 1 ; shift right the content of AL by one bit.
AL
0 1 0 1 0 1 1 0 CF Content of AL before SAR

0 0 1 0 1 0 1 1 Content of AL after SAR instruction

 6. Shift/Rotate contd..
iii. SHR:
Format: SHR destination, count
The instruction shifts each bit in the designation a specified number of bit position to the
right.
As a bit is shifted out of MSB position, a 0 is placed in the MSB position. The LSB is shifted
into the carry flag CF.
0MSBLSBCF

Example:
SAR AL, 1 ; shift left the content of AL by one bit.
AL
0 0 1 0 1 0 1 1 0 CF Content of AL before SHR

0 1 0 1 0 1 1 0 0 Content of AL after SHR instruction

 6. Shift/Rotate contd..
iv. ROR:
This instruction rotates all the bits of the specified bytes or word by a specified number of
bit position to the right.
CF MSBLSB

Example:
ROR CH, 1 ; Rotate right the byte in CH by one bit position.
v. ROL:
ROL rotate all the bits in a byte or word in the destination to the left, by one or more bit
position, using CL, as follows:
CFMSBLSB
The data bit moved out of the MSB is copied into CF.
vi. RCR:
RCR rotates byte or word in the destination to the right, through the carry flag CL, either by
one bit position or by the number of bit position given by CL:
CFMSBLSB

vii. RCL:
RCR rotates byte or word in the destination to the left, through
the carry flag CL, either by one bit position or by the number of
bit position given by CL: CFMSBLSB
 7. String Instruction
 String is a series of data byte or word available in memory at consecutive locations. It is
either referred as byte string or word string. Their memory is always allocated in a
sequential order.
 Instructions used to manipulate strings are called string manipulation instructions.
 The register SI contains the offset address of an element (byte or word) in the source
string, which is present in the data segment.
 The register DI contains the offset address of an element (byte or word) in the
destination string.
 The source string is in data segment at the offset address given by SI
 The destination string is in extra segment at the offset address given by DI.
 After each string operation, SI and/or DI are automatically incremented or decremented
by 1 or 2 (for byte or word operation) according to D flag in the register (see slide 70)
 If D=0, SI and or DI are automatically incremented and D=1, SI/DI are automatically
decremented.
 7. String Instruction contd…
Mnemonics Function
MOVSB Move the string byte from DS:[SI] to ES:[DI]
MOVSW Move the string word from DS:[SI] to ES:[DI] (see example in next slide)
CMPSB Compare string bytes (done by subtracting the bytes at ES:[DI] from the bytes at DS:
[SI])
CMPSW Compare string words (done by subtracting the bytes at ES:[DI] from the bytes at DS:
[SI])
LODSB Load the string byte at DS:[SI] into AL
LODSW Load the string word at DS:[SI] into AX
SCASB Compare string bytes (done by subtracting the bytes at ES:[DI] from the bytes at AL)
SCASW Compare string word (done by subtracting the word at ES:[DI] from the word at AX)
REP Decrement the CX and repeat the following string operation if CX0 (next slide)
REPE/REPZ Decrement the CX and repeat the following string operation if CX0 and ZF=1
REPNE/REPNZ Decrement the CX and repeat the following string operation if CX0 and ZF=0
STOSW Load the string word in AX at ES:[DI]
STOSB Load the string byte in AL at ES:[DI]
 7. String Instruction contd…
The REP (repeat) prefix placed before a string instruction causes the
Start
string instruction to be executed CX times.
Example:
MOV CX, 32H ; Load 32H (=decimal 50) in CX
MOV 32H (50) into
REP MOVSW ; Execute MOVSW instruction 50 times
register CX
Execution of these two instructions causes the moving of a string
having 50 words from the data segment to the extra segment.

Decrement the
SS content of CX reg.

ES data will be
moved from
word-50 Move a string word

word-
word-
Data segment
from DS to ES
(DS) to Extra
2
1
segment (ES)
DS 50 times
Is
NO CX=0?

YES
CS
End
 7. String Instruction contd…
Memory address
30000H  When 1-byte
data is moved
30001H then SI/DI is
30002H decremented or
ES 30003H incremented by
1.
30004H  For 2-byte
DI contains offset
30005H (word) data
address of
movement ,
destination string
SI/DI is
70000H incremented or
8-bit data 70001H decremented by
70002H 2.
8-bit data
DS 8-bit data 70003H
 For 4-byte(2
word) data
8-bit data 70004H movement, SI/DI
70005H SI contains offset is increment or
8-bit data (1-byte)
address of source decrement by 4.
string
 8. Machine control instruction
The machine/processor control instructions in the 8086 include HLT, LOCK, NOP, ESC, and
WAIT.
i. HALT:
The halt instruction stops the execution of all instructions and places the processor in the
halt state. An interrupt or a Reset signal causes the processor to resume execution from the
halt state.
ii. LOCK:
The lock instruction provides the processor an exclusive hold on the use of the system bus. It
activates an external locking signal () of the processor and is placed as a prefix to the
instruction for which a lock is to be asserted. The lock functions only with the XCHG, ADD,
OR, ADC, SBB, AND, SUB, XOR, NOT, NEG, INC and DEC instruction.
iii. NOP:
No operation– This instruction is used to insert a delay in software delay programs
iv. ESC:
This instruction is used to pass instructions to a coprocessor such as 8087, which shares the
address and data bus with an 8086.
v. WAIT:
When this instruction is executed, the 8086 checks the status of its TEST input and if the
TEST input is high, it enters an idle condition during which it does not do anything.
 PIN Details of 8086
Description
 Intel 8086 is a 16-bit HMOS
microprocessor.
 It is available in 40 pin DIP chip.
 It uses a 5V DC supply for its
operation.
 The 8086 uses 20-line address bus.
 It has a 16-line data bus.
 The 20 lines of the address bus
operate in multiplexed mode. The
16-low order address bus lines have
been multiplexed with data and 4
high-order address bus lines have
been multiplexed with status signals

It is also seen that some pins have dual functions, and this corresponds to two
modes of operation – minimum and maximum modes
 PIN Details of 8086 contd…
Modes of operation of 8086

Minimum mode Maximum mode

Minimum mode is used when the 8086 is used Maximum mode is used when the
in single processor systems system is a multi processor system, in
which the 8086 is one of the
processors
For minimum mode
operation, pin no. 33
MN / MX should be at
logic high. MN/

For maximum mode

operation, pin no. 33
MN / MX should be at
logic low. MN/
 Both DEN and DT/ R’ are given
Max Mode by 8288 bus controller

The ALE for latch is

given by 8288 bus
controller
Co-processor 8087

A Coprocessor is a specially designed

circuit on microprocessor chip which
can perform the same task very
quickly, which the microprocessor
performs. It reduces the work load of
the main processor. The coprocessor
shares the same memory, IO system,
bus, control logic and clock generator.
The coprocessor handles specialized
tasks like mathematical calculations,
graphical display on screen, etc
Control signals for all operations are generated by decoding S’ 2, S’1 and S’0 using 8288
bus controller.
Advantages of max mode of 8086:
•It helps to interface more devices like 8087. In this 8086 is called as the
host and 8087 as Co-processor.
•It supports multiprocessing, Therefore it helps to increase the efficiency.
•The purpose of the 8087 was to increase calculations operations, such as
add, sub, multiply, divide, and square root.

Disadvantages of max mode over min mode :

• It has more complex circuit than min mode.

Applications of 8086:
•Microcomputer are built using 8086. For example : IBM PC, used the Intel
8088, a version of the 8086 with 8-bit data bus.
•It is used in calculators.
•It is used for control purposes like in traffic signals(uses micro controllers
which are nothing but contains one or more CPUs along with memory
and programmable i/o peripherals).
Min Mode

8282 (8 bits) latch

The latches are

buffered D FF.

8286 (8
bits)
transceiver
s:

Control
signals
provided by
8086 for
memory
operations
and i/o
interfacing
 Min Mode

Control signals for all operations are generated by decoding M/IO’, RD’,
WR’. They are decoded by 74138 3:8 decoder

The direction of data on the data bus is controlled by the DT/R’

signal.
Timing Diagram for Read operation
Timing Diagram for Read operation
 PIN Details of 8086 contd…
Minimum Mode Pins
√ √  A set of 16 pins designated as AD. i.e., AD0–AD15. These
√
√ are the address / data pins.
√  The notation ‘AD’ means that these pins are used for
√ address as well as data.
√  They are multiplexed for data and address, which means
√ that at a particular time they carry address and at other
√ times they carry data.
√  The reason for having multiplexed pins : To reduce the
√ number of pins of the chip.
√  Since the data bus and address bus have to be separate
√ and because the ‘address’ has to be available at all
√
√ times, the address-data lines have to be ‘demultiplexed’
√ i.e., separated. This is done by the use of latches

A19 A18 A17 A16 AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Multiplexed for data and address

 PIN Details of 8086 contd…
 The first step in reading memory
De-multiplexing the Address / Data Bus
(reading 4F) is ‘placing the address
on the address bus’.
MOV CL, AL Opcode (Binary code): 4F  Next, the data (4F) is to appear on
the data bus, which means that
the bus must be made free to
√ 𝑺𝒕𝒆𝒑 − 3 carry data.
 For de-multiplexing, during the
time that the address is on the
address /data bus, it is latched on
√ 𝑺𝒕𝒆𝒑− 4 to a ‘latch IC’ whose clock is the
ALE (Address Latch Enable) signal
supplied by 8086. The signal ALE
goes high and functions as a clock
for a latch that is used to save the
address values, because the
√ 𝑺𝒕𝒆𝒑−𝟏 address has to be available
throughout the bus cycle. Once
the address is latched on to the
√ 𝑺𝒕𝒆𝒑− 2 latches, it can be removed from
the AD lines, and then these lines
are free to carry data
 PIN Details of 8086 contd…
Block diagram of the de-multiplexed address /data bus

The address
values is saved
in LATCH when
ALE=1

These lines
are free to
carry data
when ALE=0
S0, S1, S2
These are the status signals that provide the status of operation, which is
used by the Bus Controller 8288 to generate memory & I/O control
signals. These are available at pin 26, 27, and 28. Following is the table
showing their status −
S2 S1 S0 Status
0 0 0 Interrupt
acknowledge
ment

0 0 1 I/O Read
0 1 0 I/O Write
0 1 1 Halt
1 0 0 Opcode fetch
1 0 1 Memory read

1 1 0 Memory
write

1 1 1 Passive
 PIN Details of 8086 contd…
Minimum Mode Pin Functions
Pin No. Designation Function Type
16 to 2, 39 AD0–AD14, 16 multiplexed address / data lines Bidirectional
AD15 which carry address when ALE is high,
and later functions as data lines
D0–D15, when ALE is low

35 to 38 A19 / S6– Address lines A19 to A16, which are Output

A16 / S3 multiplexed with status signals S6 to S3.
The status bits function are as follows:
S6 – always 0
S5 – condition of the interrupt flag (IF)
S4 and S 3 show the current segment in
use as below:

S4 S3
0 0 Extra Segment
0 1 Stack Segment
1 0 Code or no Segment
1 1 Data Segment
 PIN Details of 8086 contd…
Minimum Mode Pin Functions
Pin No. Designation Function Type
32 When this signal is low, data can be received from Output
memory or input devices

29 When this signal is low, it is an indication that the Output

data on the data lines are available for writing into
memory or outputting to output devices
19 CLK This is the clock pin to which a clock with at least 33% Input
duty cycle is to be supplied
21 RESET This is an active high signal which signals the Input
microprocessor to reset itself provided the pin is held
high for at least 4 clock periods
22 READY For the bus cycle to proceed normally, the READY pin Input
should be found to be at logic high when it is
sampled. If it is at logic low, WAIT states are inserted
into the current bus cycle
 PIN Details of 8086 contd…
Minimum Mode Pin Functions
Pin No. Designation Function Type
23 This pin is used usually when an arithmetic co- Input
processor is in the system. This pin is tested by the
WAIT instruction. If the pin is at logic zero, the ‘WAIT’
instruction becomes a NOP instruction. Otherwise, the
processor waits until this pin becomes logic zero

25 ALE Address Latch Enable’ – this signal goes high in the Output
beginning of a bus cycle and indicates that the
multiplexed address bus contains address
information

26 Data Enable’ – This active low signal functions as an Output

activation signal for the external data bus buffers
27 DT/ Data Transmit / Receive’ – The logic value of this signal Output
indicates whether the data is received (in a read cycle
DT / R = 0) or transmitted (in a write cycle DT / R = 1).
Thus, it is used as a direction pin for external data bus
buffers

28 M/ For I / O access this pin is low, and for Output

memory access, it is high
 PIN Details of 8086 contd…
Minimum Mode Pin Functions
Pin No. Designation Function Type
31 HOLD (See This is a signal from a peripheral requesting direct Input
slide no. 91) memory access (DMA). If the signal is high, the processor
issues a Hold Acknowledge signal and tri-states its data,
address and control bus

30 HLDA(See Hold Acknowledge’ indicates the acknowledgement of Output

slide no. 91) the HOLD request
33 This pin is used to select the mode of operation – Input
minimum or maximum. For minimum mode, the pin is to
be connected to the 5 V supply
34 BHE stands for Bus High Enable. It is available at pin 34 Output
and used to indicate the transfer of data using data bus
D8-D15. This signal is low during the first clock cycle,
thereafter it is active.

1, 20 GND Ground’ – The common point is to be connected to two -----

pins. Two Ground pins are used so as to prevent having
to connect them together internally, due to possible
noise in the internal routing of the pins
 PIN Details of 8086 contd…
Minimum Mode Pin Functions
Pin No. Designation Function Type
40 VCC The power supply must be + 5V + /−10% -----

18 INTR(See Interrupt Request – this is used by an external device to Input

slide no. 91) interrupt the processor, which responds, only if the
interrupt flag (IF) is set, by lowering the INTA line, and
initiating an ‘interrupt acknowledge’ machine cycle input

24 (See slide Interrupt Acknowledge‘ is an active low signal Output

no. 91) acknowledging the interrupt request placed on the INTR
pin
17 NMI Non maskable interrupt request which is placed by an Input
external device – similar to INTR, but the Interrupt Flag
(IF) does not have to be set for it to be serviced. It is a
high priority interrupt
 Timing Diagrams contd…
Read Machine Cycle
The steps involved in a typical read machine cycle are:
1. Place on the address bus, the address of the location whose content is to be read. This
action is performed by the processor.
2. Assert the read control signal which is part of the control bus.
3. Wait until the content of the addressed location appears on the data bus.
4. Transfer the data on the data bus to the processor.
5. De-activate the read control signal. The read operation is over and the address on the
address bus is not relevant anymore.

Step-1: Address of instruction code is placed on

Address bus

Microprocessor Instruction
Step-2: RD signal is sent to Memory chip codes are
(Instruction
code is decoded stored inside
and executed) Memory-chip
Step-3: Content of the address location is placed
on data bus from memory chip
  In T1, the address is placed on
the lines AD0 to AD15 and
A16 to A19 .
 BHE is high or low depending
on the type of data (byte /
word) to be accessed. ALE
goes high.
 M / IO signal is high from T1
to T4.
 Also the DT/ R is low from T1
to T4 indicating that data is to
be ‘received’ by the processor.

 In T2, the address information is removed from AD0 to AD15. The address information is removed from
A16 / S3 to A19 / S6 and BHE / S7 also, and these lines now carry status information. In T2, the RD
signal (which is the READ control signal) is made low. In T2, DEN goes low to enable the data bus buffer
outputs
 The clock cycle T3 is to allow ‘access time’ for bringing data from memory / IO and put it on the data
bus. Thus, after the data appears on the data bus, it is transferred to the 8086 at the end of T3.
 In T4, all the bus signals are de-activated in preparation for the next bus cycle. This machine cycle ends
with T4, and the next machine cycle is scheduled to start.
 Timing Diagrams contd…
Write Machine Cycle
The steps in a write machine cycle are :
1. Place on the address bus, the address of the location to which data is to be written.
2. On the data bus, place the data to be written.
3. Assert the write control signal which is part of the control bus.
4. Wait until the data is stored in the addressed location.
5. De-activate the memory write signal. This ends the memory write operation.
For the 8086, the control signals for a write machine cycle is WR. Also the DT / R signal will
be high (for ‘data transmit’) for writing.
The write bus cycle also uses 4 T states normally.

Step-1: Address (where data is to be written) is

placed on Address bus

Step-2: Content of data to be written is placed on

Memory-chip
Microprocessor data bus Or output
device
Step-3: WR signal is sent to Memory chip/Output device
 Maximum mode
 It is necessary to use the maximum mode if the processor is to be used in multiprocessor
configurations.
 The most important issues in a multiprocessor environment are inter-processor
communication and bus contention.
 In this mode, 8086 has special pins for resolving these issues.
 To use the maximum mode, pin No. 33 MN / MX must be connected to ground.

 This mode of operation was designed by Intel for allowing the 8086 to communicate
with other processors like the arithmetic co-processor (8087) and the input /output
processor 8089.
 It was also used to allow 8086 to be used in large loosely coupled multiprocessor
systems. This mode was dropped from Intel’s designs from 80286 onwards.
 Later processors (80486 onwards) had the arithmetic co-processor integrated on the
processor chip itself.
 PIN description for Maximum mode
Min
mode (Max mode)

√
√
√

The functions of INTA , ALE, DT / R , M / IO , and WR are to

be generated externally by 8288 bus controller PIN diagram in Max mode
 Maximum mode contd…
Control Signals Generated by the Bus Controller
Status signal Machine cycle Control signal
generated by
8288
√
0 0 0 Interrupt √ √
acknowledge
0 0 1 I/O Read
0 1 0 I/O Write
0 1 1 Halt NONE
1 0 0 Instruction
Fetch
1 0 1 Memory Read
1 1 0 Memory write
1 1 1 Inactive NONE Pin diagram of the bus
controller IC 8288
 1. Program to find the factorial of a number

The factorial of a number ‘n’ is 𝑛 × ሺ 𝑛 − 1ሻ × ሺ 𝑛 − 2ሻ × ሺ 𝑛 − 3ሻ …

Solution:

i.e. factorial of 4 is 4*3*2*1 = 24 Note –

Assumptions – The result of multiplication is stored in AX for byte data type.
Starting address of program: 0400
Input memory location: 0500
For the word data type, the result of multiplication is stored in AX-DX. i.e.
Output memory location: 0600 and 0601 90C3×12DA=AA8FC0E;
After multiplication AX=FC0E & DX=AA8
MNEMONICS COMMENTS
MOV CX, [0500] Move the content of memory address 0500 in register CX

MOV AX, 0001 Move 1 in the register AX

MOV DX, 0000 Move 0 in the register DX

L1: MUL CX Multiply the contents of CX & AX and store product in

DX:AX
LOOP L1 Go to address [040A] till CX->00

MOV [0600], AX Move the content of AX in memory address 0600

MOV [0601], DX Move the content of DX in memory address 0601

HLT Stop Execution

1. Program to count the number of 1s in the contents of Accumulator

Solution: Let AL=50H=0101 0000 has two 1s.

We have written program in which the count in register BL will give the numbers of 1s:
MOV AL, 50H Load the number in Accumulator

MVI BL, 00H Initialize register B as a counter with initial value

00H; BL0

MVI CL, 08H Initialize register C as a counter for looping with

initial value of 08H; CL8

L1: SAR AL, 1 Rotate the content of the accumulator right

through carry

JNC NEXT If Carry bit is not 1, go to NEXT

INC BL If the bit is 1, increment BL

NEXT: DEC CL Decrement counter CL(CL-1=6)

JNZ L1 If the counter CL is not zero, jump to loop

HLT Terminate program execution

After Five number iterations of CL, the
content of BL=1. This process will continue
until BL is not equal to 2
1. Program to transfer a block of 4-bytes by using string instruction

Problem – Write a program to transfer a block of 4 bytes, starting address is 0500 and transfer
the block at address 0600 by using string instructions

04 18 AD 05 04 18 AD 05

0500 0501 0502 0503 0600 0601 0602 0603

Mnemonics Comments

MOV SI, 500 SI500 Move the offset address 500 of Data segment to SI

MOV DI, 600 DI600 Move offset address 600 of Extra segment to DI

MOV AX, 0000 AX0000

MOV DS, AX Move 0000H to DS register so that base address of data segment is
0000H

MOV ES, AX Move 0000H to ES register so that base address of Extra segment is
0000H

MOV CX, 0004 CX0004 since four data have to be moved

CLD Clear directional Flag

REP reduce CX and repeat till CX≠ 0

MOVSB Move the string byte from DS:[SI] to ES:[DI]

HLT End of the program

1. Program to find sum of ‘n’ numbers
Problem – Write a program to find sum of ‘n’ numbers. Assume four numbers stored in
memory address 500, 501, 502, 503. Store the sum in address 600

0A
04 03 02 01
0600
0500 0501 0502 0503

Mnemonics Comments

MOV AX, 0000H Initialize AX equal to 0

MOV SI, 500 SI500 Move the offset address 500 to SI

MOV DI, 600 DI600 Move the offset address 600 to DI

MOV CX, 0004 Assume 4 data whose sum has to be found

L1: ADD AX, [SI] AXAX+[SI]

INC SI Increment SI; 500+1=501(SI)……… so on

LOOP L1 Decrement CX. Go to L1 if CX≠0

MOV [DI], AX Assign the value of AX to the memory address pointed by DI

HLT Stop
1. Program to find average of ‘n’ numbers
Problem – Write a program to find average of ‘n’ numbers. Assume four numbers stored in
memory address 500, 501, 502, 503. Store the result in address 600

2.5
04 03 02 01
0600
0500 0501 0502 0503

Mnemonics Comments

MOV AX, 0000H Initialize AX equal to 0

MOV SI, 500 SI500 Move the offset address 500 to SI

MOV DI, 600 DI500 Move the offset address 600 to DI

MOV CX, 0004 Assume 4 data whose sum has to be found

L1: ADD AX, [SI] AXAX+[SI]

INC SI Increment SI; 500+1=501(SI)……… so on

LOOP L1 Decrement CX. Go to L1 if CX≠0

DIV CX AX=AX/CX (Average of four numbers)

MOV [DI], AX Assign the value of AX to the memory address pointed by DI

HLT Stop
1. Program for Sorting an array in ascending order

• The array can be sorted in ascending order by bubble sorting.

• In bubble sorting, n-1 comparisons are performed by taking two data at a time.
• After each comparison, the two data can be rearranged in the ascending order in the
same memory location, i.e., smaller first and larger next.
• When the above n-1 comparisons are performed n-1 times, the array will be sorted in
ascending order in the same locations.
In general
For array of size ‘n’ There will be (n-1) comparison & (n-1) iterations
i.e., array of size 5  4 no. of comparisons & 4 no. of iterations
Procedure to do sorting is explained below
Flow chart to do sorting is shown below
 Memory Device Pins
 The memory can be RAM or ROM – the difference is that ROM can only be read from, so
the signal from the processor does not have any relevance for ROM.

D0
A0

Address : Memory Read

Data
Lines Lines
RAM

: Memory write
AN-1 DM-1
𝑊𝐸 𝐶𝑆 𝑂𝐸

𝑴𝑬𝑴𝑾𝑹
𝑆𝐸𝐿𝐸𝐶𝑇 𝑴𝑬𝑴𝑹𝑫
Active low signals is to be connected to the signal from the processor side for the write
operation to be done in the addressed location. For reading, the pin (from the processor side)
is to be connected to the OE (output enable) pin of the memory chip.
The number of address lines (A0 to AN-1) depends on the number of locations it contains
20 parallel wires
A0 D0

Address Data
Lines Lines
RAM
A19
D15
𝑾𝑬 𝑪𝑺𝑶𝑬

wire 𝑺𝑬𝑳𝑬𝑪𝑻

wire

Note:
 A ROM chip does not have the
WE pin, as it can only be read
from
 256×8 RAM, means that it has 8 data lines (D0 to D7) and a storage capacity of 256
locations – thus it needs 8 address lines (A0 to A7) as 256=28.

A0 D0

Address
Data
Lines
RAM Lines

A7 256=28
D7 Address
𝑾𝑬 𝑪𝑺𝑶𝑬 locations 8-bit storage

𝑺𝑬𝑳𝑬𝑪𝑻

 Think of the following cases then – a 1K×8 RAM needs 10 address lines, as 1K=1024=210, a

 2K×8 RAM has 11 address lines and so on. Thus, it is the capacity of the chip which
decides the number of address lines
 Example:
How many address and data lines are needed for the memory chips with the following
organization?
1. 256×4
2. 512×8
3. 1K×16 Home work
4. 32K×8 Home work
5. 128K×8
Solution:
1. 256×4 means, it has 4 data lines, and 256 memory locations, each of width 4 bits. 256=2 8.
Thus, 8 address lines are needed
2. 512×8
This chip has 8 data lines.
512=29. Thus, it has 9 address lines

5. 128K×8
it has 8 data lines
128K=128×1024=27×210 =217
So, it has 17 address lines
 Memory Address Decoding
Fig 1 shows a 2K×8 memory chip A0
A0-A10
 This memory chip has 11 address lines, A10

which are directly connected to the 11 Memory

A11 2K×8
lower lines of the address bus of the
A19
processor.
𝑪𝑺
 Now the remaining 9 lines of the address
bus of the processor are connected to the
inputs of a NAND gate whose output pin
feeds the CS pin of the memory chip. It fixes 𝑺𝑬𝑳𝑬𝑪𝑻
Fig.1. Memory with address decoding
up the address range of the chip.

 Thus, it is obvious that the chip is selected (enabled) only if all the input lines of the
NAND gate are high – which means that A11-A19 of the address has to be high for the
memory chip to be selected and made active.
 The NAND gate thus functions as the address decoder for the memory.
Example
i) Find out the range of addresses that the memory chip in Fig 1 contains.
Solution
A0-A10 The address lines from to A0-A10 can
vary from 000 0000 0000 to 111 1111
Memory
1111.
A11 2K×8
The address A11-A19 lines must always
A19 be 1111 1111 1 for this chip to be
𝑪𝑺 selected.
As such, the lower and upper range of
the addresses in the chip are seen as:
𝑺𝑬𝑳𝑬𝑪𝑻
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 1 1 0 0
The first address on the chip: 1 1 0 0 0
1 1 0 0 0
The last address on the chip: 11 11 1111
0 1111
0 1111
0
1 1
1 1
Thus, the address range of the chip1 is FF800H to
1 FFFFFH i.e., 2048 bytes i.e., 2 K bytes
Address Decoding Concepts
 Thus the basic idea of address decoding is to decode the extra unused address lines of the
processor to specify the address range.
 When more chips are to be interfaced, decode the extra address lines to a different range
for each group.
 Any logic /logic gate can be used to perform address decoding. From the address decoder
output, the right logic value should be obtained to turn the chip on. Thus the ‘select’ pulse
obtained from the address decoding logic can be high or low, depending on the
requirement of the chip select pin of the memory chip.
 In general, address decoders can be built using:
– Random logic (simple gates, like NAND fate , OR gate)
– Block decoders (e.g. 2 × 4, 3 × 8 …)
– Programmable logic (PLAs, CPLDs, FPGAs, …)
The first two types of address decoders will be discussed in detail here.
Example 7.3
Design an address decoder using OR logic for a 32 K × 8 RAM. Find the address space of this
memory chip.
Solution
32K=1015, it has 15 address lines. Thus the lower 15 lines of the address bus of the processor
are connected to the address lines of the RAM. The upper 5 lines A15–A19 are used for
address decoding. Here the lines are given as input to the OR gate. When the address on the
address bus corresponds to A15 to A19 being all at logic 0, the decoder gives the SELECT
pulse to the CS pin of the memory chip and thus it is selected.

D0
A0 Data bus
D7
Address bus RAM
A14

A15 𝑪𝑺
OR
A19 𝑺𝑬𝑳𝑬𝑪𝑻
Fig. 1 Address decoding using OR logic

0000 0000 0 0 0
The first address on the chip: 0 0 0
0 0 0
The last address on the chip: 0000 0 1111
0 1111
0 1111
0
1
1
Thus, the address range of the chip is 00000H to
1 07FFFH
 Example
Find the address space of the following chips with the address decoding circuitry as shown in
the Fig.1 for 8K×8 EPROM
Solution
A0 D0 8K=213 memory locations has 13 address

Address
lines. The remaining 7 lines of the
Data
Lines EPROM Lines
processor system bus are used for
8K×8 address decoding.
A12 For the EPROM chip to be selected, the
D7 values of A19 to A13 are to be 1111 101.
𝑪𝑺𝑶𝑬
Thus, the lowest and highest addresses in
1=A19 the chip:
1=A18
1=A17 1111 1010 0 0 0
1=A16 0 0 0
0 0 0
1=A15 0 to0 0
0=A14 1111 1011 1111 1111 1111
𝑺𝑬𝑳𝑬𝑪𝑻
1=A13 For example, FA000H to FBFFFH.

Fig.1. EPROM with address decoder

 Home work
Q. Find the address space of the following chips with the address decoding
circuitry as shown in the Figure for 8 K × 8 RAM chip
 A0 is used to enable the even bank.
 To enable the high (odd) bank, 8086
generates a signal (Bus High
Enable) which goes low whenever
the addressed byte is in the high
(odd) bank
 is enabled if and only if the address
on the address bus is for accessing a
byte in the high bank. That is why it
is designated ‘BUS HIGH’ enable.
 A0 is frequently called () (Bus Low
Enable) because it is used to enable
the low bank.

Fig.1. Memory banks with the respective bank

enables signals, along with the decoder

Fig. 1 shows a case when two 32 K × 8 RAMs form the16-bit memory. Thus the total memory is
64 K × 8 bytes. 32 K RAM needs 15 address lines. Of the 20 address bits from the address bus
of the processor, A0 is used to enable the even bank. A1 to A15 are connected to the address
pins A0 to A14 of each RAM chip. The rest of the address lines are used for address decoding.
A0 and are used for selecting each of the banks separately.
 Programmable Peripheral Interface (PPI)-8255
 8086 processor computes what is expected of it and transfers it to the outside world – in
essence, the outside world is external to the processor – memory and I/O devices are
external to the processor
 However, I/O devices are of different varieties, functions, features, specifications and so on.
For example, a keyboard is very different from a video monitor. The point is that the 8086
does not have the requisite hardware within it to manage each of them according to their
special requirements and specifications
8086
Processor

Interfacing chip
(8255) √
No direct
connection
I/O devices
(Keyboard, LED display)
 8255 contd…
 Thus, I/O devices need some extra hardware to let them be interfaced to the processor.
 It is in this context that various interfacing chips have been designed.
 All these chips are programmable in the sense that they can be made to work in different
ways as required, by ‘programming’ them, using 8086 instructions.
 Thus, there are separate chips for managing parallel data transfer, serial data transfer,
keyboard, interrupts and timers for example.
 This 8255 chip is also called a parallel port chip and it eases out the problems and issues
related to parallel data transfer.
 We have transferred 8/16 bits at one go either to/from memory or I/O devices. The I/O
devices we have discussed were quite simple and needed only a read/write control signal
and a select pulse generated during the read/write cycle.
 However, when I/O devices are more versatile and have more features, a PPI will be very
useful, especially when more than one I/O device is to be interfaced to the processor
 8255 contd…
Port A Keyboard

8086 D0-D7 8255 Port B Printer

Port C LED display

Fig.1. The connections between an 8086, 8255 and three peripherals

 The data bus of the 8086 is connected to the 8255

 When data from the 8086 is sent to the 8255 then where does the 8255 keep the data?
The answer is that it has registers called ‘ports’ – there are three ports here – A, B and C,
and these ports have pins connecting it to external devices. Thus, port A has 8 pins PA0 to
PA7 – so also ports B and C, as well. To these port pins, external devices like keyboards,
displays, printers can be connected
 To route data between 8086 processor and I/O devices, these Ports must be programmed.
 Programming interfacing chips entails writing of ‘control words’ in their control/command
registers
 8255 contd…
Pin Configuration and Internal Block Diagram
It is DIP (dual-in-line) chip which has 40 pins, that consist of three 8-bit ports named Port A
(PA), Port B (PB) and Port C (PC), each of which can be programmed as input or output ports.
1 PA3 PA4 40
2 PA2 PA5 39
PA0-PA7
3 PA1 PA6 38 Group A
Group A Port A
4 PA0 PA7 37
Control
5 RD WR 36
𝑫𝒂𝒕𝒂𝒃𝒖𝒔
6 RESET 35 Data bus PC4-PC7
Group A
7 GND D0 34 D0-D7 buffer Port C
8 A1 D1 33 Upper
9 A0 D2 32
10 PC7 D3 31
Group B PC0-PC3
11 PC6 D4 30 Port C
12 PC5 D5 29
𝑹𝑫 Lower
13 PC4
14 PC0
D6 28
D7 27
𝑾𝑹 Read/ Group B
15 PC1 VCC 26
𝑨𝟏 Write
Control
Control PB0-PB7
Group B
16 PC2 PB7 25 𝑨𝟎 Logic Port B
17 PC3 PB6 24
18 PB0 PB5 23 𝑹𝑬𝑺𝑬𝑻
19 PB1 PB4 22
20 PB2 PB3 21
𝑪𝑺
Fig.1. Pin diagram of 8255 Fig.1. Internal block diagram of the 8255
Data Bus Buffer There is a three state bi-directional 8-bit buffer which is used to interface the
chip to the data bus of the system. Upon execution of the processor’s input or output
instructions, data and control/status words are received or transmitted by the buffer.
Read/Write Control Logic It manages all data transfer between the chip and the processor, on
accepting control signals from the control and address buses of the system.

Group A and B Controls Functionally this chip has been divided as Group A and B and they
have their corresponding controls. The way the chip is to act is decided by a register called the
control/status register which can be written to and read from.
 1. MP doing some work Interrupt 2. Interrupted by
external device
wire

Peripheral
2000 MVI AL,5
3. Go to the (Keyboard)
2001 MVI BL,4 address of
2002 ADD AL,BL Interrupt 3000 Interrupt
Service
2003 Next 3001 Routine
instruction 3002 (ISR)
3003
4. MP spend some
time in executing
8086 PROCESSOR ISR & return back
to main program 3004 IRET

1st option--Processor continually keeps checking if a key has been pressed (polling)
When a key is pressed, the processor goes on to the task of identifying the key.
However, if the processor is ‘polling’ for a key press, it is obviously waiting and doing nothing
else. This is just a waste of processor time.
2nd option--A better way of organizing the setup would be to let the processor do some task,
and ‘interrupt’ it only when a key is pressed
1. Working inside home 2. Doorbell rings

3. Go to the door and attend to the

4. We spend some time attending to
person who has interrupted us
the task requested by the visitor,
 Interrupts of 8086
 8086 has
Hardware interrupts (external signal given through one of its interrupt pin INTR/NMI)
Software interrupts (INT n where n is interrupt type 00H to FFH=256 in decimal)
Error generated interrupts (such as divide by 0 using DIV/IDIV)
 For the three cases mentioned here, the interrupting mechanism is different, but the way
the processor responds is similar
 The point to note is that, after an interrupt request is processed, the processor has to
come back to its previous task which was left unfinished
 Thus, an interrupt is not very different from a CALL instruction in its philosophy, but there
are some differences in the way it is handled and processed
 Interrupt Response of 8086
After every instruction cycle, the processor checks if any interrupt is awaiting service. If, it
finds an interrupt request and decides to acknowledge and service it, the response is the
following sequence of steps:
I. The flag register is pushed on to the
stack.
II. The interrupt flag is disabled (IF = 0).
III. The trap flag is disabled (TF = 0). ISR
IV. The CS register is pushed on to the stack. Main Program
PUSHF
V. The IP register is pushed on to the stack. CLEAR IF
CLEAR TF
VI. Control is transferred to the location in PUSH CS
which the corresponding ‘Interrupt PUSH IP
CET ISR
Service Routine’ (ISR) is stored. This in
effect, would be a far jump. IRET
POP IP
VII. The program corresponding to the ISR is POP CS
POPF
executed. The last instruction in the ISR
will be IRET.
VIII.Then IP is popped off the stack.
IX. CS is popped off the stack.
X. The Flag register is popped off the stack.
XI. Control returns to the point at which it
had left off .
 Interrupt Service Routine and Interrupt Vector
What is an interrupt service routine?

When an interrupt occurs, the processor suspends the execution of its current task and takes
on another task as required by the interrupting source. This program, or routine as it may be
called, is designated as an ‘interrupt service routine’
This means that for any interrupt that occurs, there is a particular interrupt service routine (ISR).
Where is this ISR available?

It is to be available in memory and must be accessed on the occurrence of the specific

interrupt. For that, the address of the ISR must be obtained. The address of an ISR is called its
‘interrupt vector’
For an 8086 based system, any address of code is in the following form, CS:IP.

Thus, the interrupt vector for any interrupt has 4 bytes – two for the CS value and two for the
IP value

Thus, if the interrupt vector for a particular interrupt is obtained, control can be transferred
to the new location by using the new values of CS and IP specified as the ‘interrupt vector’.
 Interrupt Vector Table
The 8086 has 256 interrupt vectors and since each vector is specified by 4 bytes, it implies
that 256 × 4 = 1024 bytes (1K) of memory are allocated to store the interrupt vectors
These 256 vectors are stored in a table called the ‘Interrupt Vector Table’ (IVT) in system
RAM from locations 00000 to 003FFH i.e., up to 0000: 03FF
These numbers thus turn out to be what can CS INT 255 VECTOR
3FC
be called as the ‘type numbers’ of the IP
interrupts.
Thus, there are interrupts designated as INT 0,
INT 1, INT 2 …… INT 255

Since each interrupt vector is 4 bytes long, the

memory location corresponding to the vector INT 2 VECTOR
of INT n is obtained as n × 4 i.e., for INT 1, the CS
address of the first byte of its vector is 1 × 4 = 0008 INT 1 VECTOR
IP
0004, for INT 0 it is 0000 and so on
CS
It multiplies the type number by 4, gets the 0004 INT 0 VECTOR
address of its interrupt vector and loads IP IP
and CS with these new values and starts CS
executing the ISR it has located. 0000
IP
 Dedicated Interrupt Types
1. INT 0 (Divide by Zero Error)

On division, if the quotient register is not large enough to contain the quotient, this
interrupt is generated automatically

Thus, the ISR for this error generated interrupt is written in the address 0000:0000

What could be a possible ISR for this condition?

One possibility is just to display a message indicating ‘divide overflow’ and expect the
programmer to correct his data/program.
Another possibility is to write as the ISR, a program which increases the size of the
quotient register, so that the problem is corrected without user intervention. It is up to
the system designer to decide how the error handler is to be written.
 2. INT 1 (Single Stepping)
This type number is dedicated for ‘single stepping’ or ‘trace’ (debugging—error finding).
During logical debugging of our programs, we would like to stop after the execution of each
instruction and check the contents of registers, memory and so on.
Intel has provided the ‘Trap’ flag for this, and this flag has to be set to let this happen.

The ISR for viewing the register and memory contents will be pointed by the vector of
interrupt type 1.
However, an important issue in this is how to set the trap flag. No such instruction has been
encountered so far.
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
U U U U OF DF IF TF SF ZF U AF U P U CF

The Trap flag is the D8 bit of the flag register.

PUSHF ; push the flag register to the stack
POP AX ; pop it to AX 0000000100000000
OR AX, 0000000100000000 ; OR it to set bit D8 i.e., TF 0011000000001100
PUSH AX ; push AX to stack 0011000100001100
POPF ; pop it to the flag register
This program segment sets the trap flag which causes INT 1 to occur.
3. INT 2 (Non Maskable Interrupt)
This interrupt corresponds to the vector (pointer) of the hardware interrupt NMI. When an
interrupt is received on the pin NMI (Non Maskable Interrupt) of the processor, a type 2
interrupt occurs – this means that the ISR for NMI must be written in the address pointed
by the corresponding IVT content
4. INT 3 (Breakpoint Interrupt)
This is the breakpoint interrupt, which is useful for de-bugging.
We will need to set breakpoints (stop after executing a group of instructions) and check the
content of registers and memory after executing instructions up to the breakpoint.
code (CCH) is inserted and getting executed at the position in the program where the
breakpoint is set. MOV AL, NUM1
Example:
ADD AL, NUM2
CCH ; interrupt on overflow
5. INT 4 (Overflow Interrupt)
If the overflow flag is set, this interrupt occurs
An instruction INTO (interrupt on overflow) must be written after the program segment
which is likely to cause the overflow flag (OF) to be set
The last line of this program
Example: MOV AL, NUM1 segment can pass control to the
ADD AL, NUM2 ISR written for INT 4, if the
INTO ; interrupt on overflow overflow flag is set by the result of
the addition.
 Table Interrupt Vector Table Allocation

INT type no. Location in IVT Application

(HEX)
0 0000:0000 Divide by zero error
1 0000:0004 Single step interrupt
2 0000:0008 Non maskable interrupt
3 0000:000C Breakpoint
4 0000:0010 Overflow
5 to 31 Reserved by Intel
32 to 255 Available to user
 Software Interrupts
What is meant by the term ‘software interrupt’?
When an interrupt is initiated by an instruction, it is called a software interrupt. The format of
this instruction is:
INT type number.
The type numbers can vary from 0 to 255.
This is a very important and interesting way of using procedures whose vectors are inserted
into the IVT.
Thus, the user can write any procedure as an ISR, store it in some address in memory and call
it by using the instruction INT n.
Before using it this way, the user must however insert the CS and IP values of his ISR in the IVT
in the location corresponding to INT n

Hardware interrupt service routines can be tested using software interrupts. Take the case
of NMI which is a hardware interrupt. This is vectored to location 0000:0008 i.e., it
corresponds to type number 2. The routine corresponding to this hardware interrupt can be
tested by using the instruction INT 2. In effect, a hardware interrupt on the NMI pin and the
software instruction INT 2 takes us to the same absolute address
 Hardware Interrupts
There are two pins on which interrupt requests can be received – they are the INTR pin and
the NMI pin.
NMI
This is a +v edge triggered interrupt, but it is also required to have a duration in the high state
of more than two clock cycles. Any high going transition of NMI is latched on-chip and will be
serviced at the end of the current instruction. This is a non maskable interrupt, in that it does
not depend on the setting of the interrupt flag (IF). It cannot be masked or prevented from
being activated. It is a Type 2 interrupt, meaning that its vector is obtained from the
corresponding location in the interrupt vector table.
INTR
This is the non-vectored interrupt pin of the 8086, which means that when an interrupt
request is received on this pin, it does not get automatically directed towards any particular
entry in the interrupt vector table. Another feature of this interrupt is that the interrupt flag
(IF) is required to be set for an interrupt request on the INTR line to be honored. When the
processor is reset, all flags are found to be cleared and so is the IF. It is to be ensured that the
IF is set by the instruction STI if interrupts on the INTR lines are to be acknowledged
 Syllabus
 Evolution of Microcontrollers
 Architecture of 8051 Microcontroller
 Pin diagram of 8051
 External memories
 Counters & Timers
 Serial Communication
 Interrupts
 Instruction set of 8051
 Addressing Modes of 8051
 Assembly Language Programming examples using 8051
Difference between General purpose processor & Microcontrollers
 Difference between MP & MC
MP MC

Microprocessor is the heart of Micro Controller is the heart of

Computer system an embedded system
Application Used where intensive Used where the task is fixed
processing is required. It is used and predefined. It is used in
in personal computers, laptops, the washing machine, alarm,
mobiles, video games, etc. etc.

Structure It has only the CPU in the chip. CPU, Memory, I/O port and all
Other devices like I/O port, other devices are connected on
memory, timer is connected the single chip.
externally.

Clock speed High. It is in terms of the GHz. It Less. It is in terms of the MHz.
ranges between 1 GHz to 4 GHz. it ranges between 1 MHz to 300
MHz.
complexity It’s complex and expensive, with It’s simple and inexpensive
a large number of instructions to with less number of
process
instructions to process
 Difference between MP & MC
MP MC
Programming The program for the The program for the
microprocessor can be microcontroller is fixed once it is
changed for different designed.
applications
Bit size It is available in 32-Bit and 64- It is available in 8-bit, 16-bit, and
bit. 36-bit.
Cost The cost of the microprocessor It is cheaper.
is high compared to the
microcontroller.
Power The power consumption for The power consumption for the
consumption the microprocessor is high. microcontroller is less.
Size The overall size of the The overall size of the system is
system is large. small.
Microprocessor has a Microcontroller has more
smaller number of register. Hence the programs
registers, so more are easier to write.
operations are memory-
based.
 Examples where Microcontrollers are used
Telephone, Security system, TVs, VCR, Cable TV Tuner, Home computers, Remote
controller, Video games, Paging, Camera, Cellular Phones, Fax machine , Microwave
oven, Laser printer, Color printer

Fig.2. Examples where Microcontrollers are used

 Embedded systems

 In embedded system devices, the software

application and hardware are embedded
together and are designed to do a specific
task.
 For example, digital camera, vacuum
cleaner, mp3 player, mouse, keyboard, and
printer, are some examples of embedded
systems.
 It is interesting to note that embedded  In most cases embedded
systems run a fixed program
and contain a microcontroller.
 Criteria for choosing Microcontrollers
1. The first and foremost criteria for choosing a MC is that it must meet the task
at hand efficiently and cost effectively. We must see whether an 8-bit or 16-bit
MC can best handle the computing needs of the task most effectively. Among
other considerations in this category are:
a. Speed : What is the highest speed that MC supports?
b. Packaging: Does it comes in 40-pin DIP (dual inline package) or a QFP (quad flat
packaged) or some other packaging format? This is important in terms of space,
assembling, and prototyping the end product.

DIP (dual inline package) QFP (quad flat packaged)

 Criteria contd…

d. Power consumption: This is specially critical for battery-powered products.

e. The amount of RAM and ROM on chip.
f. The number of I/O pins and the timer on the chip.
g. How easy is it to upgrade to higher-performance or lower power
consumption versions.
h. Cost per unit: This is important in terms of the final cost of the product in
which a MC is used.
2. The second criterion in choosing a MC is how easy it is to develop products
around it. Key considerations include the availability of an assembler,
debugger, a code-efficient C language compiler, emulator, technical support,
and both in-house and outside expertise.
 Criteria contd…

3. The third criterion in choosing a MC is its ready availability in needed quantities

both now and in the future. Currently, of the leading 8-bit MC, the 8051 family
has the largest number of diversified (multiple source) suppliers. By supplier is
meant a producer besides the originator of the MC. In case of 8051, which was
originated by Intel, several companies also currently produce the 8051. These
companies include: Intel, Amtel, Philips/signetics, AMD, Infineon (formerly
Siemens), Matra and Dallas semiconductor.
 The overview of 8051 MC
In 1981, Intel corporation introduces an 8-bit microcontroller called 8051.
8051 is an 8-bit processor, meaning that the CPU can work on only 8-bits of data at a time.
Features of 8051 Microcontroller
 4KB bytes on-chip program memory (ROM)
 128 bytes on-chip data memory (RAM)
 Four register banks bank 0, bank 1, bank 2, and bank 3. Each register bank consists of 8
registers (R0 to R7).
 8-bit Stack pointer
 8-bit bidirectional data bus
 16-bit unidirectional address bus
 34 general purpose registers each of 8-bit [A, B R0-R7 for four register bank (32)]
 It has 11 Special Function Registers (SFR)
 16 bit Timers (usually 2, but may have more or less)
 Three internal and two external Interrupts
 Four 8-bit ports,(short model have two 8-bit ports)
 Evolution of 8051 contd….
The comparison between 8051 family members
Features 8051 8052 8031
ROM (on-chip space in bytes) 4K 8K 0K
RAM (bytes) 128 256 128
Timers 2 3 2
I/O pins 32 32 32
Serial port 1 1 1
Interrupt sources 6 8 6

8031 Microcontroller
 Another member of 8051 family is the 8031 chip.
 This chip is often referred to as a ROM-less 8051 since it has 0K bytes of on-chip ROM.
 To use this we have to add external ROM to it.
 This external ROM must contain the program that 8031 will fetch and execute.
 In process of adding external ROM, we loose two ports.
 That leaves only 2 ports (of the 4 ports) for I/O operations.
 To solve this problem, we can add external I/O to the 8031.
8751 Microcontroller
 The UV-EPROM version of 8051 is the 8751.
 8751 chip has 4K bytes of on-chip UV-EPROM.
 Using this chip for development requires access to a PROM burner, as well as a UV-
EPROM eraser to erase the contents of UV-EPROM inside the 8751 chip before we can
program it again.
 It takes around 20 minutes to erase the 8751 before it can be programed again.
 This has led many manufacturers to introduce flash NV-RAM version of 8051

DS89C4×0 from Dallas semiconductor

 To eliminate the waiting needed to erase the chip and thereby speed up the
development time, AT89C51 from Amtel corp. was introduced with flash ROM.
 The erasing of flash is done by the PROM burner itself, which is why a separate eraser
is not needed.
 To eliminate the need for a PROM burner, Dallas semiconductor has a version of
8051/52 called DS89C4×0 that can be programmed via the serial COM port of a IBM
PC.
Architecture of 8051 Microcontroller
 The system bus connects
all the support devices to
the CPU.
 The system bus consists of
an 8-bit data bus, a 16-bit
address bus and bus
control signals.
 All other devices like
program memory, ports,
data memory, serial
interface, interrupt
control, timers, and the
CPU are all interfaced
together through the
system bus.

Central Processor Unit (CPU)

The CPU is the brain of any processing device of the microcontroller. It monitors and
controls all operations that are performed on the Microcontroller units. The User has no
control over the work of the CPU directly . It reads program written in ROM memory and
executes them and do the expected task of that application
Interrupts

 Interrupt is a subroutine call that interrupts the microcontrollers main operations and
causes it to execute any other program, which is more important at the time of
operation.
 The feature of Interrupt is very useful as it helps in case of emergency operations.
 An Interrupts gives us a mechanism to put on hold the ongoing operations, execute a
subroutine and then again resumes to another type of operations.
 The Microcontroller 8051 can be configured in such a way that it temporarily terminates
or pause the main program at the occurrence of interrupts.
 When a subroutine is completed, Then the execution of main program starts.
 Generally five interrupt sources are there in 8051 Microcontroller. There are 5 vectored
interrupts are shown in below
INTO
TFO
INT1
TF1
R1/T1
Memory
Microcontroller requires a program which is a collection of instructions. This program tells
microcontroller to do specific tasks. These programs require a memory on which these can
be saved and read by Microcontroller to perform specific operations of a particular task. The
memory which is used to store the program of the microcontroller is known as code memory
or Program memory of applications. It is known as ROM memory of microcontroller also
requires a memory to store data or operands temporarily of the micro controller. The data
memory of the 8051 is used to store data temporarily for operation is known RAM memory.
8051 microcontroller has 4K of code memory or program memory, that has 4KB ROM and
also 128 bytes of data memory of RAM.

BUS
Basically Bus is a collection of wires which work as a communication channel or medium for
transfer of Data. These buses consists of 8, 16 or more wires of the microcontroller. Thus,
these can carry 8 bits,16 bits simultaneously.
Address Bus:
 Microcontroller 8051 has a 16 bit address bus for transferring the data. It is used to
address memory locations and to transfer the address from CPU to Memory of the
microcontroller.
Data Bus:
Microcontroller 8051 has 8 bits of the data bus, which is used to carry data of particular
applications.
Oscillator
 It requires clock pulses for its operation of microcontroller applications.
 For this purpose, microcontroller 8051 has an on-chip oscillator which works as a clock
source for Central Processing Unit of the microcontroller.
 The output pulses of oscillator are stable.
 Therefore, it enables synchronized work of all parts of the 8051 Microcontroller.

Input/output Port
 Normally microcontroller is used in embedded systems to control the operation of
machines in the microcontroller.
 Therefore, to connect it to other machines, devices or peripherals we require I/O
interfacing ports in the microcontroller interface.
 For this purpose microcontroller 8051 has 4 input, output ports to connect it to the other
peripherals
Timers/Counters
 8051 microcontroller has two 16 bit timers and counters.
 These counters are again divided into a 8 bit register.
 The timers are used for measurement of intervals to determine the pulse width of pulses
 Different Registers and Register Bank of 8051
The most widely used registers of 8051 are
Registers Function
A: Accumulator (8-bit): To hold one of the operand in all most all arithmetic and logical
operations, accumulator A is used
B (8-bit): This is general purpose 8-bit register
R0,R1,R2,R3,R4,R5,R6,R7 These are also 8bit general purpose registers.
(8-bit):
DPTR-Data Pointer This register is used as pointer to memory address
register (16-bit):
PC- Program Counter (16- PC points to the address of the next instruction to be executed.
bit): As the CPU fetches the opcode from the program ROM, the PC is
incremented to point to the next instruction
Flag register To indicate the arithmetic conditions such as carry bit
In 8051, Flag register is
called as program status CY AC F0 RS1 RS0 OV ---- P PSW
word (PSW) : 8-bit

CY: PSW. 7: Carry flag AC : PSW. 6: Auxiliary carry flag

F0: PSW. 5: Available to user for general purpose RS1: PSW. 4: Register bank selector bit 1
RS0: PSW. 3: Register bank selector bit 0 OV: PSW. 2: Overflow flag
---- : PSW. 1: User definable bit P: PSW. 0: Parity bit
 Registers Function
SP: Stack pointer (16-bit): To access the stack
P0: Port 0 This port is used for I/O interfacing
P1: Port 1 This port is used for I/O interfacing
P2: Port 2 This port is used for I/O interfacing
P3: Port 3 This port is used for I/O interfacing
IP: Interrupt Priority control To change the default priority order of interrupt as per the desire or
need.

IE: Interrupt Enable control To enable or unmask a particular interrupt using instructions
TMOD: Timer/Counter mode control To select the operating mode and the timer/counter operation of the
timers
TCON: Timer/Counter control To control operations of counter and timers
T2CON: Timer/Counter 2 control This register contains bits controlling the operation of timer 2
T2MOD: Timer/Counter mode control Timer/Counter Mode Control
SCON: serial counter The Serial Control or SCON is used to control the 8051 Microcontroller’s
Serial Port
SBUF: Serial data buffer SBUF register holds data which is to be transmitted or received.

PCON: Power control To force the 8051 microcontrollers into power-saving mode
 Register bank and Stack
8051 MC as a total 128 bytes of RAM which are assigned address from 00H to 7FH
These 128 bytes are divide into three different groups as follows:

1. A total of 32 bytes from locations 00 to 1F bytes are 7F

Scratch Pad
RAM
assigned for register banks & stack
2. A total of 16 bytes from locations 20H to 2FH are set
aside for bit-addressable read/write memory 30
2F
3. A total of 80 bytes from locations 30H to 7FH are used Bit addressable
RAM
for read and write storage (also called scratch pad). 20
1F
These 80 locations are used for the purpose of storing Register Bank 3
18
data and parameters by 8051 programmers. 17
Register Bank 2
R7
10
R6
0F
R5 Register Bank 1
R4 08 (Stack)
R3 07
Register Bank 0
R2
R1 00
R0 Fig.1. RAM allocation in 8051
Register Bank of 8051
 In Byte addressable
we can only access
the data by byte by
byte i.e. whole
bunch of 8 bits but
in bit addressable
addresses we can
access or
manipulate each
bit individually.
 By using some
simple instructions
with 8-bit memory
address we can
check the bit
addressing.
 For an example the
instruction CLR
6FH, using this
instruction it clears
the location 6FH
 Register bank contd…
How to switch register bank?
Register bank 0 is the default when 8051 is powered up..
We can switch to other bank with the help of PSW register. Bit D3 and D4 of the PSW are
used to select the desired register bank
RS1 (PSW. 4) RS0 (PSW. 3)
Bank 0 0 0
Bank 1 0 1
Bank 2 1 0

D4 (PSW. 4) and D3 (PSW. 3) can be accessed by bit-addressable instructions SETB and CLR
Ex. SETB PSW. 3 will make PSW.3=1 and select bank register 1.

How stack are accessed in 8051?

 If the stack is selection of RAM, there must be registers inside the CPU to point to it.
 The register used to access the stack is called the SP (stack pointer) register.
 When 8051 is powered up, the SP register contains value 07. Thus RAM location 08 is the
first location used for the stack by 8051.
 The storing of CPU register in the stack is called a PUSH, and pulling the content of stack
back into CPU register is called POP.
Example of PUSH instruction
Example of POP instruction
Pin diagram and it’s description
 Pin description contd….
Pins 1 – 8:
Port1 uses the Pins 1 to 8. Each pin is bidirectional Input /Output with internal pull – up
resistors.
Pin 9:
It is a reset input Pin which used to reset the 8051 microcontrollers. It is an active HIGH Pin
i.e. if we apply a high pulse to this pin, the microcontroller will reset and terminate all
activities.
Note: All value of the register will be lost after activating a power-on reset.
Pins 10-17:
Port3 uses the Pins 10 to 17. Each pin is bidirectional Input /Output with internal pull – up
resistors. Besides the Input /Output, each pin has some special functionality.
The below table (next slide) describe the other functionality of Port-3
 Pin description contd….
PORT 3 Bit and Function Description
Pin
P3.0 (10) RXD Serial Input
P3.1 (11) TXD Serial Output
P3.2 (12) INT0 External Interrupt 0
P3.3 (13) INT1 External Interrupt 1
P3.4 (14) T0 Timer 0
P3.5 (15) T1 Timer 1
P3.6 (16) WR External Memory Write
P3.7 (17) RD External Memory Read

Pins 18 & 19:

Pin 18 and 19 are used for interfacing an external crystal oscillator to get the system clock.
Pin 20 (GND):
Pin 20 is the Ground Pin of the 8051 Microcontroller.
 Pin description contd….
Pins 21 -28: Port 2 uses the Pins 21 to 28. Each pin is bidirectional Input /Output with internal
pull – up resistors. Besides the Input /Output, when external memory is interfaced, PORT 2 pins
act as the higher-order address byte.

Pin 29 (PSEN): Pin 29 is the Program Store Enable Pin (PSEN). It is an output pin and using this
pin, external Program Memory can be read.

Pin 30 (ALE/PROG): Pin 30 is the Address Latch Enable Pin. It is an output pin and using this Pin,
external address can be separated from data (as they are multiplexed by 8051).

Pin 31 (EA/VPP): Pin 31 is the External Access Enable Pin i.e. allows external Program Memory. It
is an input pin and must be connected from VCC or GND. If we want to access the code from
external program memory, it must be connected with GND. If we want to use on-chip memory, it
must be high (connected with VCC).

Pins 32–39:
Port 0 uses the Pins 32 to 39. Each pin is bidirectional Input /Output but without internal pull –
up resistors. So we need to use an external pull-up before using Port0 as Input /Output.

Pin 40 (VCC): Pin 40 is the power supply pin of the 8051 Microcontroller. It should be +5V.
 Addressing mode of 8051
In 8051 there are six types of addressing modes.
1. Immediate Addressing Mode
2. Register Addressing Mode
3. Direct Addressing Mode
4. Register Indirect Addressing Mode
5. Indexed Addressing Mode
6. Implied Addressing Mode

Immediate addressing mode

In Immediate Addressing Mode, the data is provided in the instruction itself. The data is
provided immediately after the opcode.
Example:
Note: The immediate data must be preceded by the pound sign, ‘#’
MOV A, #0AFH;
MOV R3, #45H; The DPTR stands for Data Pointer. Using this, it
MOV DPTR, #FE00H; points the external data memory location.
is same as Although DPTR is 16-bit register, it can also be
MOV DPL, #00H accessed as two 8-bit registers, DPH and DPL where
MOV DPH, #FEH DPH is high byte and DPL is low byte
 Addressing contd…
Register addressing mode
In the register addressing mode the source or destination data should be present in a register
(R0 to R7). These are some examples of Register Addressing Mode.
Example:
Note: we can move data between the accumulator A and Rn (for n=0 to 7)
MOV A, R5; but no movement of data between Rn registers is allowed.
MOV R2, #45H; MOV R4, R7

MOV R0, A;

Direct Addressing Mode

In the Direct Addressing Mode, the source or destination address is specified by using 8-bit
address in the instruction. Only the internal data memory can be used in this mode.
Example:
Note: The absence of # sign shows that 45H is address of memory
MOV 80H, R6; location and not constant data
MOV R2, 45H; The # sign distinguishes between immediate addressing mode and
direct addressing mode
MOV R0, 05H;
 Addressing contd…
Register indirect addressing Mode
In this mode, the source or destination address is given in the register. By using register indirect
addressing mode, the internal or external addresses can be accessed. The R0 and R1 are used
for 8-bit addresses, and DPTR is used for 16-bit addresses, no other registers can be used for
addressing purposes. When R0 and R1 are used as pointers, that is, when they hold the address
of RAM locations, they must be preceded by the ‘@’ sign, as shown below
Example
MOV A, @R0 : Move the content of RAM location whose address is held by R0 into A
MOV@DPTR, A; The content of A is overwritten in the location pointed by DPTR
Indexed addressing mode
In the indexed addressing mode, the source memory can only be accessed from program
memory only. The destination operand is always the register A.
MOVC A, @A+DPTR; Note: The C in MOVC instruction refers to code byte.
For the first instruction, let us consider A holds 30H. And the PC
value is1125H. The contents of program memory location 1155H
(30H + 1125H) are moved to register A
 Addressing contd…
Implied Addressing Mode
In the implied addressing mode, there will be a single operand. These types of instruction
can work on specific registers only. These types of instructions are also known as register
specific instruction.
Example:
RLA; Rotate the A register content to the Left
SWAP A; Swap the nibbles in A.
 Instruction set of 8051
8051 Microcontroller Instruction Set are divided into five groups. They are:
1. Data Transfer Instructions
2. Arithmetic Instructions
3. Logical Instructions
4. Boolean or Bit Manipulation Instructions
5. Program Branching Instructions
DATA TRANSFER ARITHMETIC LOGICAL BOOLEAN PROGRAM
BRANCHING
MOV ADD ANL CLR LJMP
MOVC ADDC ORL SETB AJMP
MOVX SUBB XRL MOV SJMP
PUSH INC CLR JC JZ
POP DEC CPL JNC JNZ
XCH MUL RL JB CJNE
DIV RLC JNB DJNZ
DA A RR JBC NOP
RRC ANL LCALL
SWAP ORL ACALL
CPL RET
RETI
JMP
 Instruction contd…
Data Transfer Instructions
The Data Transfer Instructions are associated with transfer of data between registers or
external program memory or external data memory. The Mnemonics associated with Data
Transfer are given below.
Mnemonic Description
MOV Move Data from source to destination
MOVC Move data from code memory pointed by DPTR+A to A . ex. MOVC A, @A+DPTR
MOVX Transfers data between the accumulator and external data memory.
Syntax: MOVX operand1, operand2
Ex. MOVX @Rn, A
PUSH Move Data to Stack
POP Copy Data from Stack
XCH Exchange Data between A and specified Register.
Syntax: XCH A, register.
Ex. XCH A,R0
XCHD Exchange Lower Order Data between A and specified RAM location’s data
Syntax: XCHD A,[@R0/@R1]
Ex. XCHD A, @R0; Exchanges bits 0-3 of the Accumulator with bits 0-3 of the Internal
RAM address pointed to indirectly by R0
 Instruction contd…
Arithmetic Instructions
Using Arithmetic Instructions, we can perform addition, subtraction, multiplication and
division. The arithmetic instructions also include increment by one, decrement by one and a
special instruction called Decimal Adjust Accumulator.

Mnemonic Description
ADD Addition without Carry
ADDC Addition with Carry
SUBB Subtract with Carry
INC Increment by 1
DEC Decrement by 1
MUL Multiply
DIV Divide
DA A Decimal Adjust the Accumulator (A Register)

The arithmetic instructions have no knowledge about the data format i.e., signed, unsigned,
ASCII, BCD, etc. Also, the operations performed by the arithmetic instructions affect flags
like carry, overflow, zero, etc. in the PSW Register.
 Instruction contd…
Logical Instructions
The next group of instructions are the Logical Instructions, which perform logical operations
like AND, OR, XOR, NOT, Rotate, Clear and Swap. Logical Instruction are performed on Bytes
of data on a bit-by-bit basis.
Mnemonic Description
ANL Logical AND
ORL Logical OR
XRL Ex-OR
CLR Clear Register
CPL Complement the Register
RL Rotate a Byte to Left
RLC Rotate a Byte and Carry Bit to Left
RR Rotate a Byte to Right
RRC Rotate a Byte and Carry Bit to Right
SWAP Swap Accumulator Nibbles
Syntax: SWAP A; SWAP swaps bits 0-3 of the Accumulator with bits 4-7
of the Accumulator

Before SWAP A 1 0 1 0 1 1 1 1 After SWAP A 1 1 1 1 1 0 1 0

 Instruction contd…
Boolean or Bit Manipulation Instructions
As the name suggests, Boolean or Bit Manipulation Instructions deal with bit variables. We
know that there is a special bit-addressable area in the RAM and some of the Special
Function Registers (SFRs) are also bit addressable.
Mnemonic Description
CLR Clear a Bit (Reset to 0)
Syntax: CLR register
Ex. CLR A; will clears (sets to 0) all the bit(s) of the register A
SETB Set a Bit (Set to 1)
MOV Move a Bit
JC Jump if Carry Flag is Set
JNC Jump if Carry Flag is Not Set
JB Jump if specified Bit is Set
JNB Jump if specified Bit is Not Set
JBC Jump if specified Bit is Set and also clear the Bit
ANL Bitwise AND
ORL Bitwise OR
CPL Complement the Bit

These instructions can perform set, clear, and, or, complement etc. at bit level.
 Instruction contd…

Program Branching Instructions

The last group of instructions in the 8051 Microcontroller Instruction Set are the Program
Branching Instructions. These instructions control the flow of program logic.
Mnemonic Description
LJMP Long Jump (Unconditional)
AJMP Absolute Jump (Unconditional)
SJMP Short Jump (Unconditional)
JZ Jump if A is equal to 0
JNZ Jump if A is not equal to 0
CJNE Compare and Jump if Not Equal
DJNZ Decrement and Jump if Not Zero
NOP No Operation
LCALL Long Call to Subroutine
ACALL Absolute Call to Subroutine (Unconditional)
RET Return from Subroutine
RETI Return from Interrupt
JMP Jump to an Address (Unconditional)
OBJECTIVE: TO TRANSFER A BLOCK OF DATA BYTES FROM SOURCE MEMORY TO
DESTINATION MEMORY USING 8051.
PROGRAM:
MOV R0, #50H // Initialize the source memory pointer
MOV R1, #60H // Initialize the destination memory pointer
MOV R2, #05H // Initialize Iteration counter
BACK: MOV A, @R0 // Get the data from source memory pointer
MOV @R1, A // Store the data into destination memory pointer
INC R0 // Increment the source memory pointer
INC R1 // Increment the destination memory pointer
DJNZ R2, BACK // Decrement iteration count and if it
// is not zero go to relative Address and // repeat the same process until
MEMORY WINDOW:
count become // zero.
Before execution:
END
D:0x50H: 22 AB 3D 44 55 00
D:0X60H: 22 AB 3D 44 55 00
D:0X60H: 00 00 00 00 00 00
After execution:
D:0x50H: 22 AB 3D 44 55 00
D:0X60H: 22 AB 3D 44 55 00
BLOCK EXCHANGE
OBJECTIVE: TO EXCHANGE TWO BLOCKS OF DATA BYTES USING 8051 PROGRAM:
MOV R0,#50H // Initialize the source memory pointer
MOV R1,#60H // Initialize the destination memory pointer
MOV R2,#05H // Initialize Iteration counter
BACK: MOV A, @R0 // Get the data from source memory pointer and Load // into Accumulator
XCH A, @R1 // Exchange data between Accumulator and destination memory pointer
MOV @R0, A // Store the data into source memory pointer
INC R0 // Increment the source memory pointer
INC R1 // Increment the destination memory pointer
DJNZ R2, BACK /* Decrement iteration count and if it is not zero,
go to relative Address and repeat the same process until count become zero*/
END MEMORY WINDOW:
Before execution:
D:0x50H: 01 02 03 04 05 00
D:0X60H: 06 07 08 09 10 00
After execution:
D:0x50H: 06 07 08 09 10 00
D:0X60H: 01 02 03 04 05 00
Features Memory Mapped IO IO Mapped IO
IO devices are accessed like any other They cannot be accessed like any other
Addressing
memory location. memory location.
They are assigned with 16-bit address
Address Size They are assigned with 8-bit address values.
values.

Instructions Used The instruction used are LDA and STA, etc. The instruction used are IN and OUT.

Cycles involved during operation are IO

Cycles involved during operation are
Cycles read and IO writes in the case of IO Mapped
Memory Read, Memory Write.
IO.

Any register can communicate with the IO Only Accumulator can communicate with
Registers Communicating
device in case of Memory Mapped IO. IO devices in case of IO Mapped IO.

216 IO ports are possible to be used for Only 256 I/O ports are available for
Space Involved
interfacing in case of Memory Mapped IO. interfacing in case of IO Mapped IO.

During writing or read cycles (IO/M` = 0 ) During writing or read cycles (IO/M` = 1) in
IO/M` signal
in case of Memory Mapped IO. case of IO Mapped IO.

No separate control signal required since we

Special control signals are used in the case
Control Signal have unified memory space in the case of
of IO Mapped IO.
Memory Mapped IO.

Arithmetic and logical operations are Arithmetic and logical operations cannot be
Arithmetic and Logical operations performed directly on the data in the case of performed directly on the data in the case of
Memory Mapped IO. IO Mapped IO.