Cadence AXI

SystemC library
usage guide
Rev. 2.0

OCTOBER 3, 2017
DESIGN METHODOLOGY DEPARTMENT

RENESAS ELECTRONICS CORPORATION

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 AGENDA
 Introduction Page 03

 SystemC design and verification Page 07

 Operation synthesis Page 25

 RTL verification Page 28

 Inquiry ahead and change tracking Page 35

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 1. INTRODUCTION

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 Cadence SystemC library
 In using the library
 The interface protocol operation mounted on the library can be simulated only by calling the
function prepared in the library.
- In this book, the AXI protocol is indicated.
 In the input of the SystemC description to operation synthesis tool Stratus, it is ..RTL
description.. generable.

 Interface protocol supported by Cadence SystemC library

 AXI3
 AXI4-Lite

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 Method of obtaining Cadence SystemC library
 The SystemC library made by Cadence is bundled to the Stratus tool package.
 (Stratus installation directory)/share/stratus/include
 Please confirm Stratus HLS User Guide Chapter 36 about details in the AXI3 SystemC library.
 /common/appl/Cadence/stratus/16.23-s100/doc/Stratus_HLS_User_Guide/
Stratus_HLS_User_Guide.pdf and page 808

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 CONTENT OF THIS BOOK
 Content of this book
 Procedure for SystemC design, verification, operation synthesis, and verifying RTL by using
AXI3 SystemC library made by Cadence

 Object tool and version

Tool name Version Tool overview

When each tool described in this book is compiled
SystemC 2.2 SystemC package SystemC package in tool package
Because the library is referred, special
IES 15.20s020 Simulator correspondence is unnecessary.

VIPCAT 11.30.048 Verification IP

Stratus 16.23-s100 Behavior synthesis tool
JasperGold 2017.03p001 Formal verification tool

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 2. SystemC design and verification

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 SystemC design and verification
 Content of this chapter
 The procedure of the design and the verification of the module with the AXI3 master interface is
described in following the order.
simtop (3-3)
(0) Traits specification file
top (2)
(1) AXI3 master IF module
Another
(2) The design top module Module axifunc M memory
M channel S
(In case of (1) (3-1)
(3) Verification environment
being. )
(3-1) AXI3 slave IF model
(3-2) AXI3 bus monitor
(3-3) The simulation top module monitor The AXI3 monitor of
VIPCAT Instance
(3-2)
(3-4) Simulation script

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 (0) TRAITS SPECIFICATION FILE
 Please prepare the header file that specifies attribute (traits) of the library, and do include with
each file. Please change the deficit part if necessary.
#ifndef __SAMPLE_TRAITS_H__ // Continuation
#define __SAMPLE_TRAITS_H__
template<typename simple_bus_traits_base>
#include “cynw_axi3.h" struct sample_traits
using namespace axi3; {
typedef axi3_traits<axi3_types_traits<axi3_width_traits<simple_bus_traits_base> > > tlm_traits;
#ifdef MAP_TLM2
#include “cynw_bus_interfaces/simple_bus/tlm2_transactors.h" #ifdef MAP_AXI3_SIGNAL
#include "cynw_bus_interfaces/axi3/axi3_tlm2.h" typedef axi3_traits<axi3_types_traits<axi3_width_traits<simple_bus_traits_base> > > hw_bus_traits;
#endif #endif

#ifdef MAP_AXI3_SIGNAL #if defined(MAP_TLM2)

static const bool sig_level = true; static const int io_config = IO_CONFIG_TLM2;
#else typedef FAST_TLM_TRAITS put_get_traits;
static const bool sig_level = false; #elif defined(MAP_AXI3_SIGNAL)
#endif static const int io_config = IO_CONFIG_AXI3_SIG;
typedef SIG_TRAITS_RESET put_get_traits;
struct FAST_TLM_TRAITS : public SIG_TRAITS #else
{ static const int io_config = IO_CONFIG_TLM1;
static const bool Level = 0; // configures flex channels for TLM level typedef FAST_TLM_TRAITS put_get_traits;
}; #endif
// typedef DEFAULT_TRAITS put_get_traits;
struct SIG_TRAITS_RESET : public SIG_TRAITS };
{ ResetData: Specification and true of the reset operation existence of
static const bool ResetData = true;
the data port are recommended.
static const bool ResetSync = true;
static const bool ResetLevel = true; ResetSync: Synchronous reset (true) /asynchronization reset (false)
}; ResetLevel: Polarity of reset

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 (0) TRAITS SPECIFICATION FILE
 Please prepare the header file that specifies attribute (traits) of the library, and do include with
each file. Please change the deficit part if necessary.
// Continuation of last page The width of data of the bus can be specified, and it
select it from 16, 32, and 64,128.
// typedef sample_traits<simple_bus_traits_base_32> sample_traits_32bit; simple_bus_traits_base_16
typedef sample_traits<simple_bus_traits_base_64> sample_traits64;
simple_bus_traits_base_32
typedef axi3_initiator<sample_traits64> initiator1_t;
simple_bus_traits_base_64
typedef axi3_target<sample_traits64> target1_t; simple_bus_traits_base_128

typedef sample_traits64::tlm_traits::awchan_t awchan_t;

Typedef declaration of master and slave of AXI3
typedef sample_traits64::tlm_traits::wchan_t wchan_t; In axi3_initiator, the master and axi3_target are
typedef sample_traits64::tlm_traits::bchan_t bchan_t; slaves.
typedef sample_traits64::tlm_traits::archan_t archan_t;
typedef sample_traits64::tlm_traits::rchan_t rchan_t; Typedef declaration of each
channel of AXI3
typedef hier_axi3_initiator<sample_traits64> hier_initiator1_t;
typedef hier_axi3_target<sample_traits64> hier_target1_t; Typedef declaration
for connecting wires
#endif

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 simtop (3-3)
top (2)
axifunc

(1) AXI3 MASTER IF MODULE MODULE HEADER M M S memory

(1) (3-1)
monitor

FILE (1/2) (3-2)

 Please add the following to the module header file of SystemC (header file generated in the mode
of the generation of the module of ssgen) for the high-level design.
#ifndef AXIFUNC_H
 Addition of include file #define AXIFUNC_H

#include <systemc.h>
 Declaration of master IF port #include "ssgenlib.h"
With cynw_tlm/cynw_tlm.h
#include “cynw_tlm/cynw_tlm.h"
Include does the Traits specification file prepared for last page.
 Constructor initialization [ko] of IF port #include “sample_traits.h"

SC_MODULE(axifunc) {
 Connection of clock reset in IF port sc_in < bool > ACLK;
sc_in < bool > ARESET;
... Declaration of master IF port
 Reset function of each channel of IF call The data type is a type to have declared typedef
initiator1_t initiator1; with the Traits specification file.
SC_CTOR(axifunc)
: ACLK("ACLK")
...
, initiator1("initiator1") Constructor initialization [ko] of master IF port
{
initiator1.clk_rst(ACLK, ARESET);
Connection of clock reset in master IF port
#ifndef _CTOS_TOP
SC_CTHREAD(main_thread, ACLK.pos());
reset_signal_is(ARESET, true);
#endif
}

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 simtop (3-3)
top (2)
axifunc

(1) AXI3 MASTER IF MODULE MODULE HEADER M M S memory

(1) (3-1)
monitor

FILE (2/E) (3-2)

 Please add the following to the module header file of SystemC (header file generated in the mode
of the generation of the module of ssgen) for the high-level design. 。
// Continuation of last page
 Addition of include file void reset_main_thread() {
initiator1.awchan->reset_put();
Reset function of each channel of master IF call
 Declaration of master IF port initiator1.wchan->reset_put();
initiator1.bchan->reset_get(); Master IF
initiator1.archan->reset_put(); The reset function name of awchan, wchan, and archan
 Constructor initialization [ko] of IF port initiator1.rchan->reset_get();
...
is "Reset_put. “

}
 Connection of clock reset in IF port ...
};

 Reset function of each channel of IF call #ifdef __CTOS__

SC_MODULE_EXPORT(axifunc);
#endif

#endif // AXIFUNC_H

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 simtop (3-3)
top (2)
axifunc

(1) AXI3 MASTER IF MODULE MODULE SOURCE M M S memory

(1) (3-1)
monitor

FILE (1/3) (3-2)

 The IF protocol of AXI3 is achieved by calling the function prepared in each channel of AXI3.
 The I/O port of AXI3 is driven by calling the prepared function in the function. The designer need
not drive the port directly.
 awchan, wchan, archan
- valid is controlled, ready is received, and data is transmitted.
- nb_can_put: It is confirmed whether ready has come from the slave.
- nb_put : Data is transmitted.
 rchan, bchan
- valid is received, ready is controlled, and data is received.
- nb_can_get : It is confirmed whether valid has come from the slave.
- nb_get : Data is received.

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 simtop (3-3)
top (2)
axifunc

(1) AXI3 MASTER IF MODULE MODULE SOURCE M M S memory

(1) (3-1)
monitor

FILE (2/3) (3-2)

 Example of mounting light sequence (The deficit calls the function of the IF library).
// awchan
while( !initiator1.awchan->nb_can_put() ) wait(); Awready waiting

awchan_t v_awchan; The variable of awchan is temporarily

v_awchan.addr = 256; prepared.
v_awchan.len = 0xf; The address etc. are set.
initiator1.awchan->nb_put(v_awchan); Data transfer of awchan

// wchan
wchan_t v_wchan; Burst transfer of 16 times
int i = 0;
while( !v_wchan.last ) { Wready waiting
while(!initiator1.wchan->nb_can_put()) wait();
The variable of wchan is
v_wchan.data = i; temporarily prepared.
v_wchan.last = (i==v_awchan.len); The light data etc. are
initiator1.wchan->nb_put(v_wchan); set.
cout << "WDATA = " << v_wchan.data << endl;
wait(); i++; Data transfer of wchan
}

// bchan
while( !initiator1.bchan->nb_can_get() ) wait(); Bvalid waiting

Data transfer of bchan

bchan_t v_bchan;
Bchan to the variable
initiator1.bchan->nb_get(v_bchan);
temporarily
cout << "RESP = " << v_bchan.resp << endl; The response is stored.

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 simtop (3-3)
top (2)
axifunc

(1) AXI3 MASTER IF MODULE MODULE SOURCE M M S memory

(1) (3-1)
monitor

FILE (3/E) (3-2)

 Example of mounting lead sequence (The deficit calls the function of the IF library).
// archan
while( !initiator1.archan->nb_can_put() ) wait(); Arready waiting

archan_t v_archan; The variable of archan is temporarily

v_archan.addr = 256; prepared.
v_archan.len = 0xf; The address etc. are set.
initiator1.archan->nb_put(v_archan);
Data transfer of archan
// rchan
rchan_t v_rchan; Burst transfer of 16 times
while( !v_rchan.last ) {
while(!initiator1.rchan->nb_can_get()) wait(); Rvalid waiting
Data transfer of rchan
initiator1.rchan->nb_get(v_rchan);
The lead data of rchan etc. are
cout << "RDATA = " << v_rchan.data << endl;
temporarily stored in the variable.
wait();
}

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 simtop (3-3)
top (2)
axifunc memory
(1) M M S
(3-1)

(2) THE DESIGN TOP MODULE monitor

(3-2)

 Please add the following to the hierarchical module header file of SystemC (header file generated
in the hierarchical generation mode of ssgen) for the high-level design. 。
#ifndef TOP_H
 Declaration of master IF port for connecting wires #define TOP_H

#include <systemc.h>
 Constructor initialization [ko] of IF port #include "ssgenlib.h"
#include “axifunc.h”
,,,
 Connecting wires with IF port of subordinate position module
SC_MODULE(top) {
sc_in < bool > ACLK;
sc_in < bool > ARESET;
...
axifunc xf0;
... Declaration of master IF port for connecting wires
The data type is a type to have declared typedef with
hier_initiator1_t initiator1; the Traits specification file.

SC_CTOR(top)
: ACLK("ACLK")
...
, initiator1("initiator1") Constructor initialization [ko] of master IF port
{
initiator1.hier_bind(xf0.initiator1);
... Connecting wires with IF port of subordinate
} position module (axifunc)
...

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 simtop (3-3)
top (2)
axifunc memory
(1) M M S
(3-1)

(3-1) AXI3 SLAVE IF MODEL monitor

(3-2)

 The example of mounting the memory model who with slave IF of AXI3 is described. It is possible
to use it as it is because of the model who corresponds to burst transfer.
#ifndef MEMORY_H // Continuation
#define MEMORY_H memory(sc_module_name name)
: sc_module(name)
#include “sample_traits.h" , CTOR_NM(target1)
, CTOR_NM(multi_rw_adaptor)
class memory : public sc_module, axi3_multi_rw_if<sample_traits64> {
{ target1.target_port(multi_rw_adaptor);
public: multi_rw_adaptor.target_port(*this);
sc_in_clk clk;
sc_in<bool> reset; Size of memory array target1.clk_rst(clk, reset);

static const int num_words = 1000; // size in WORDS abort = true;

}
// The memory has a single target socket that is used for read and write bursts:
target1_t target1; Declaration of slave IF port void init_mem()
The data type is a type to have declared typedef with {
SC_HAS_PROCESS(memory); the Traits specification file. // initialize the memory with some known non-zero values
for (unsigned i = 0; i < num_words; i++)
// The multi_rw_adaptor allows the memory to use the simpler multi_read() and multi_write() API data_array[i] = i * target1_t::data_bytes;
axi3_multi_rw_adaptor<sample_traits64> multi_rw_adaptor; }

// this memory model currently has these restrictions: bool do_read(target1_t::data_t& val, unsigned index)
// addresses on the bus are BYTE addresses, must be aligned to {
// target1_t::data_bytes if (abort) sc_assert(index < num_words);
// lengths on the bus are in terms of # of BYTES, if (index >= num_words) return false;
// must be multiple of target1_t::data_bytes val = data_array[index];
return true;
}

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 simtop (3-3)
top (2)
axifunc memory
(1) M M S
(3-1)

(3-1) AXI3 SLAVE IF MODEL monitor

(3-2)

 Here, the example of mounting the memory model who with slave IF of AXI3 is described. It is
possible to use it as it is because of the model who corresponds to burst transfer.
// Continuation of last page // Continuation
bool do_write(target1_t::data_t val, unsigned index) virtual void multi_write(awchan_t& awchan, const wchan_t& wchan,
{ bchan_t& bchan, bool& burst_done) {
if (abort) sc_assert(index < num_words); //if (abort) sc_assert(awchan.size == sample_axi3_traits::default_size);
if (index >= num_words) return false; if (!do_write(wchan.data, awchan.addr / target1_t::data_bytes))
data_array[index] = val; bchan.resp = AXI_SLVERR_RESPONSE;
return true; if (awchan.len == 0)
} burst_done = true;
awchan.addr += target1_t::data_bytes;
virtual void multi_read(archan_t& archan, rchan_t& rchan, bool& burst_done) awchan.len -= 1;
{ }
//if (abort) sc_assert(archan.size == sample_axi3_traits::default_size);
if (!do_read(rchan.data, archan.addr / target1_t::data_bytes)) virtual bool can_multi_read() const { return true; }
rchan.resp = AXI_SLVERR_RESPONSE; virtual bool can_multi_write() const { return true; }
if (archan.len == 0) virtual void reset_multi_read() {}
burst_done = true; virtual void reset_multi_write() {}
archan.addr += target1_t::data_bytes;
archan.len -= 1; void set_abort(bool _abort) {
} abort = _abort;
}

private:
target1_t::data_t data_array[num_words];
bool abort;
};

#endif

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 simtop (3-3)
top (2)
axifunc memory
(1) M M S
(3-1)

(3-2) AXI3 BUS MONITOR monitor

(3-2)

 When the instance is done with SystemC, the Verilog module that instancing does AXI3 monitor
(cdn_abvip_axi3_monitor.svp) of VIPCAT and the Verilog module are described about a necessary port map
file. 。
 Verilog module
module monitor(ACLK, ARESET, awid, awaddr, ... rready); // Continuation
input ACLK;
parameter ADDR_WIDTH = 32; input ARESET;
parameter DATA_WIDTH = 64; input [ID_WIDTH-1:0] awid;
parameter ID_WIDTH = 4; input [ADDR_WIDTH-1:0] awaddr;
parameter LEN_WIDTH = 4; ...
parameter SIZE_WIDTH = 4; input rready;
parameter BURST_WIDTH = 2;
parameter LOCK_WIDTH = 2; cdn_abvip_axi3_monitor #(
parameter CACHE_WIDTH = 4; .ADDR_WIDTH (ADDR_WIDTH ),
parameter PROT_WIDTH = 3; .DATA_WIDTH (DATA_WIDTH ),
parameter BRESP_WIDTH = 2; ...
parameter RRESP_WIDTH = 2; .LOW_POWER_ON(LOW_POWER_ON)
parameter COVERAGE_ON = 1; Parameter of VIP of AXI3 ) axi_monitor ( VIP of AXI3 : for negedge reset.
parameter RST_CHECKS_ON = 1; .aclk (ACLK), .aresetn (!ARESET), The reversing signal of ARESET of posedge
parameter X_CHECKS_ON = 1; .awid (awid), .awaddr (awaddr),
reset is connected.
parameter MAX_WAIT_CYCLES_ON = 1; ...
parameter ALL_STROBES_HIGH_ON = 0; .rvalid (rvalid), .rready (rready),
parameter BYTE_STROBE_ON = 1; .csysreq (1’b0),
parameter EXCL_ACCESS_ON = 1; .csysack (1’b0),
parameter LOCKED_ACCESS_ON = 1; .cactive (1’b0)
parameter READ_INTERLEAVE_ON = 0; );
parameter WRITE_INTERLEAVE_ON = 0;
parameter READ_RESP_IN_ORDER_ON = 1; endmodule
parameter WRITE_RESP_IN_ORDER_ON = 1;
parameter LOW_POWER_ON = 1;

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 simtop (3-3)
top (2)
axifunc memory
(1) M M S
(3-1)

(3-2) AXI3 BUS MONITOR monitor

(3-2)

 When the instance is done with SystemC, the Verilog module that instancing does AXI3 monitor
(cdn_abvip_axi3_monitor.svp) of VIPCAT and the Verilog module are described about a necessary port map file.
 Port map file (for IES)
-sctype "PCLK:bool"
-sctype "PRESET:bool"
-sctype "paddr:sc_uint<32>"
-sctype "psel:sc_uint<1>"
-sctype "penable:bool"
-sctype "pwrite:bool"
-sctype "pwdata:sc_uint<32>"
-sctype "pstrb:sc_uint<4>"
-sctype "pprot:sc_uint<3>"
-sctype "prdata:sc_uint<32>"
-sctype "pready:bool"
-sctype "pslverr:bool"

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 simtop (3-3)
top (2)
axifunc memory
(1) M M S
(3-1)

(3-3) THE SIMULATION TOP MODULE monitor

(3-2)

 Please add the following to the hierarchical module header file of the test bench (header file
generated in the hierarchical generation mode of#ifndef SIMTOP_H
ssgen).
#define SIMTOP_H

 Addition of include file #include <systemc.h>

#include "ssgenlib.h" With AXI3 slave IF model
#include “top.h” It is include as for the header file of the AXI3 bus
 Instance of AXI3 slave IF model monitor.
#include “memory.h" Last page of header file of bus monitor
 Instance of AXI3 bus monitor #include "monitor.h" From the Verilog file and the port map file
IES generates it automatically.
SC_MODULE(simtop) {
 Declaration of channel of AXI3 sc_in < bool > ACLK;
sc_in < bool > ARESET;
 Constructor initialization [ko] ...

top dut0;
 Connecting of AXI3 channel
memory memory0; Instance of slave IF model and bus monitor
monitor monitor0;
 Connecting wires of slave IF
axi3_channel<sample_traits64> dut_to_memory; Declaration of channel of AXI3
Master-slave ties.
 Connecting of bus monitor
SC_CTOR(simtop)
...
, memory0("memory0")
Constructor initialization
, monitor0("monitor0")
[ko]
, dut_to_memory("dut_to_memory")
{

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 simtop (3-3)
top (2)
axifunc memory
(1) M M S
(3-1)

(3-3) THE SIMULATION TOP MODULE monitor

(3-2)

 Please add the following to the hierarchical module header file of test bench SystemC (header file
generated in the hierarchical generation mode of// Continuation
ssgen). of last page
dut_to_memory(memory0.target1); Slave IF(target1) and master IF(initiator1)
dut0.initiator1(dut_to_memory); are connected with the channel.
 Addition of include file ...

memory0.clk(ACLK);
 The AXI3 slave IF model's declaration memory0.reset(ARESET);
Call of connecting wires and initialization
function of slave IF
memory0.init_mem();
 Declaration of AXI3 bus monitor
monitor0.ACLK(ACLK);
monitor0.ARESET(ARESET);
 Declaration of channel of AXI3 monitor0.awid(dut_to_memory.awid);
monitor0.awaddr(dut_to_memory.awaddr); Connecting of bus monitor
 Constructor initialization [ko] ...
monitor0.rvalid(dut_to_memory.rvalid);
With each port of the bus monitor
Each member of the channel is
monitor0.rready(dut_to_memory.rready); connected directly.
 Connecting of AXI3 channel }
...
};
 Connecting wires of slave IF
#ifdef __CTOS__
 Connecting of bus monitor SC_MODULE_EXPORT(simtop);
#endif

#endif // SIMTOP_H

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 (3-4) SIMULATION SCRIPT
 Please add the following to a standard IES script (run_ies.csh and ncverlog_lsfsh_sc generated
putting up ..-.. ies when ssgen of simtop is executed) for the high-level design.
ncverilog -c -access +rw \
+incdir+${AXI3_ABVIP}/rtl \
 run_ies.csh +incdir+${VIPCAT_HOME}/utils/cdn_v_utils \
-loadpli1 ${VIPCAT_HOME}/lib/libviputil.so:cdsVip_PLIPtr \
${AXI3_ABVIP}/rtl/cdn_abvip_axi3_monitor.svp \
- Environmental setting of VIPCAT and Stratus (run_ies.csh) ../tb/monitor.v

source /common/appl/dotfiles/cadence.CSHRC_vipcat11.30.048 ncshell -nocompile -import verilog -into systemc monitor \

setenv VIPCAT_HOME ${DENALI}/.. -file ../tb/monitor_ies.map
setenv AXI3_ABVIP ${VIPCAT_HOME}/abvip/axi3
source /common/appl/dotfiles/cadence.CSHRC_stratus_v16.23-s100 irun \
-Wcxx,-fpermissive \
bs -M 8000 -os RHEL6 ... ... \
-D_MEM_MODEL \
-I${STRATUS_HOME}/share/stratus/include \
 ncverilog_lsfsh_sc (right deficit) -DMAP_AXI3_SIGNAL=1 \
+incdir+${AXI3_ABVIP}/rtl \
+incdir+${VIPCAT_HOME}/utils/cdn_v_utils \
- Compilation command of AXI3 bus monitor and VIPCAT -loadpli1 ${VIPCAT_HOME}/lib/libviputil.so:cdsVip_PLIPtr \
-coverage all \
-access +rw -input probe.tcl
- “-Wcxx,-fpermissive" Flag (limitations of 15.20- s0xx)
imc -64bit \
- Compilation flag for AXI3 library and compilation flag for VIPCAT -batch -init ./imc.cmd -licqueue -logfile ./imc.log -nostdout

- IMC uses 64 bit version (For the memory allocation error evasion).

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 OTHERS
 Execution of another EDA tool
 Please execute the tool after an environmental configuration file of Stratus also does source.
-I${STRATUS_HOME}/share/stratus/include \
 Please add the compilation flag for the AXI3 library (right picture). -DMAP_AXI3_SIGNAL=1 \

 The module (this axifunc and top) with IF of AXI3 cannot execute SLEC.
- The purpose of SLEC is not to support the IF library of the [keidensu] Co..

 Treatment of code coverage (GCOV)

 The confirmation of the code coverage result to the file of [keidensu] Co. IF library is unnecessary. The
function in the library is called from both of master/slave. Therefore, the purpose is not to be able to judge
from which call to have become a treatment of "Street" as line coverage.
 Please use AXI3 bus master's function coverage (assert/cover) about the verification index of [keidensu]
Co. IF library.

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 3. OPERATION SYNTHESIS

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 OPERATION SYNTHESIS
 Please add the compilation flag for the AXI3 library to "Cc_options" of a standard Stratus script
(project_*.tcl generated with ssgen) and “hls_cc_options".
...
# Compiler options
set CLOCK_PERIOD "5.0"
set_attr cc_options " -g -DSTRATUS -DMAP_AXI3_SIGNAL=1 -I[get_install_path]/share/stratus/include -I/common/appl/Renesas/SystemC/utility/ssgen/v1.9.3 "
set_attr hls_cc_options “ -DSTRATUS -DMAP_AXI3_SIGNAL=1 -I[get_install_path]/share/stratus/include -I/common/appl/Renesas/SystemC/utility/ssgen/v1.9.3 "

# Stratus-HLS options
...

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 AXI PORT NAME
 The name of the AXI port of RTL generated with Stratus is sure to become "Prefix" _ "AXI port
name".
 The character string defined with SystemC enters for "Prefix".
 It is not possible to make it to an arbitrary port name. When the port name cannot observe the
design rule, it is necessary to correct RTL that Stratus generated directly.
SystemC Verilog
SC_MODULE(axifunc) { module axifunc(...);
sc_in < bool > ACLK; input ACLK;
sc_in < bool > ARESET; input ARESET;
... ...
input initiator1_AWREADY;
initiator1_t initiator1; input initiator1_WREADY;
...

SC_MODULE(top) { module top(...);

sc_in < bool > ACLK; input ACLK;
sc_in < bool > ARESET; input ARESET;
... ...
axifunc xf0; input initiator1_AWREADY;
... input initiator1_WREADY;
...
hier_initiator1_t initiator1;

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 4. RTL VERIFICATION

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 RTL VERIFICATION
 Content of this chapter
 Verification procedure of wanting operation synthesis do RTL

(1) RTL simulation

(2) JasperGold

 When the AXI SystemC library is used, the SystemC-RTL equivalence verification by
SLEC cannot be applied to the RTL verification.
- SLEC unsupports the library made by the [keidensu] company SystemC.
- Please guarantee the quality of operation synthesis RTL based on the SystemC verification
environment. Please strengthen the verification by formal verification (JasperGold) if
necessary.

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 simtop (3-3)
top (2)
axifunc

(1) RTL シミュレーション M M S memory

(1) (3-1)
monitor
シミュレーショントップモジュールの変更 (3-2)

 テストベンチの階層モジュールヘッダファイル (2 の (3-3) のファイル ) を修正してください。

 DUT の結線 SC_MODULE(simtop) {
sc_in < bool > ACLK;
 DUT の sc_trace 関数呼び出し ...

SC_CTOR(simtop)
{
dut_to_memory(memory0.target1); DUT を RTL にする場合の結線方法を追加
#ifndef _MODE_RTL -D_MODE_RTL で切り替える
dut0.initiator1(dut_to_memory); RTL では AXI3 ポートが明示的に宣言されているため、各ポートとチャネルの
#else 各メンバを直接接続する
dut0.initiator1_AWID(dut_to_memory.AWID);
dut0.initiator1_AWADDR(dut_to_memory.AWADDR);
...
dut0.initiator1_RREADY(dut_to_memory.RREADY);
#endif
}
...
void vcd_trace(ssgen_trace_file* tf, int depth = HIER_MAX) {
...
#ifndef _MODE_RTL
DUT を RTL にする場合、
dut0.vcd_trace(tf, depth-1);
DUT の sc_trace 関数を呼び出さないようにする
#endif
-D_MODE_RTL で切り替える
}
};

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 simtop (3-3)
top (2)
axifunc

(1) CHANGE IN RTL SIMULATION PORT MAP FILE (1) M M

monitor
S memory
(3-1)

(3-2)

 Please add the AXI3 port to a top port map file (*_ ies.map generated in the hierarchical generation mode
of ssgen) for the design.
 Port map file (for IES)
-sctype "ACLK:bool"
-sctype "ARESET:bool"
-sctype “initiator1_AWID:sc_uint<4>" -To the argument of sctype
-sctype “initiator1_AWADDR:sc_uint<32>“ "Port name: the type in SystemC" is
... specified.
-sctype “initiator1_RREADY:bool"

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 (1) CHANGE IN RTL SIMULATION SIMULATION SCRIPT

 Please change to the IES script (file of (3-4) of two).

 ncverilog_lsfsh_rtl (right deficit) mv ../../src/top.h ../../src/top.h.T

ncverilog -c -access +rw ../../rtl/top.v ../../rtl/axifunc.v

- The header file of the main module of DUT is renamed, and after it ncshell -nocompile -import verilog -into systemc top -file ./top_ies.map

simulates it, returned.

ncverilog -c -access +rw \
- DUT of RTL is compiled. +incdir+${AXI3_ABVIP}/rtl \
...
- -D_MODE_RTL is added. irun \
... \
-D_MODE_RTL \
-I${STRATUS_HOME}/share/stratus/include \
...

mv ../../src/top.h.T ../../src/top.h

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 top VIPCAT の
スレーブモデル

axifunc M S axi3_slave

(2) JasperGold “bind” により

top 直下に VIP を
インスタンスし、結線

 The example of the IEV environment that connects VIPCAT (slave of AXI3) is described.
 Bind description of DUV and VIP
// 続き
`define ADDR_WIDTH 32 bind top axi3_slave #(
`define DATA_WIDTH 64 .ADDR_WIDTH (`ADDR_WIDTH ),
`define ID_WIDTH 4 .DATA_WIDTH (`DATA_WIDTH ),
`define LEN_WIDTH 4 ...
`define SIZE_WIDTH 4 .LOW_POWER_ON (`LOW_POWER_ON)
`define BURST_WIDTH 2 )
`define LOCK_WIDTH 2 axi3_slave_inst
`define CACHE_WIDTH 4 (
`define PROT_WIDTH 3 .aclk (ACLK), AXI3 の VIP は negedge リセットのため、
`define BRESP_WIDTH 2 .aresetn (!ARESET), posedge リセットの ARESET の反転信号を接続
`define RRESP_WIDTH 2 AXI3 の VIP の parameter .awid (initiator1_awid),
`define COVERAGE_ON 1 フォーマル検証ではリセット期間の検証は行わないた .awaddr (initiator1_awaddr),
`define RST_CHECKS_ON 0 め、 RST_CHECKS_ON は 0 に変更 ...
`define X_CHECKS_ON 1 .rready (initiator1_rready),
`define MAX_WAIT_CYCLES_ON 1 .csysreq (1’b0),
`define ALL_STROBES_HIGH_ON 0 .csysack (1’b0),
`define BYTE_STROBE_ON 1 .cactive (1’b0)
`define EXCL_ACCESS_ON 1 );
`define LOCKED_ACCESS_ON 1
`define READ_INTERLEAVE_ON 1
`define WRITE_INTERLEAVE_ON 1
`define READ_RESP_IN_ORDER_ON 1
`define WRITE_RESP_IN_ORDER_ON 1
`define LOW_POWER_ON 1

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 (2) JasperGold
 Script of JasperGold (fpv.tcl)
abvip -set_location /common/appl/Cadence/vipcat/11.30.048/tools/abvip

analyze -clear
analyze -sv top_axi3_slave_bind.sv
analyze -verilog [glob ../stratus/rtl/*.v] For X_CHECKS_ON=1
elaborate -top top -bbox_a 100 -multiple_clock -enable_sva_isunknown -The enable_sva_isunknown option is
necessary.
clock ACLK
reset ARESET

set_engine_mode {Ht Hp Tri}

prove -all
report -summary -results -file fpv_report.log -force
check_assumptions -conflict

 Execution command of JasperGold

Cadence.CSHRC_jasper17.03.001jg fpv.tcl OS appl/dotfiles/batch/bs-n10-M8000RHEL6 source/general

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 5. INQUIRY AHEAD AND CHANGE
TRACKING

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 THE INQUIRY AHEAD
 About the content of this book
 High-level design and high-ranking, synthetic support ML ([email protected])
 There must be it ..the smell.. ..[mon].. each other.

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 CHANGE TRACKING
Revision 内容 承認 審査 作成
1.0 新規作成 RSD/DM 技 RSD/DM 技 RSD/DM 技
浅野 浅野 今村
2016/1/22 2016/1/22 2016/1/22
2.0 対象ツールを CtoS から Stratus に変更 SRDD2/DMD SRDD2/DMD SRDD2/DMD
浅野 今村 酒井
2017/9/28 2017/9/27 2017/8/30

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 BIG IDEAS FOR EVERY SPACE
Renesas.com

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