Logic Design

Ch 4

Combinational Circuits
Introduction
 Two classes of logic circuits:
 Combinational
 Sequential

 Combinational Circuit:

inputs Combinational outputs

:: Logic
::

Each output depends entirely on the immediate

(present) inputs.
Introduction
 Sequential Circuit:

inputs Combinational outputs

:: Logic
::

Memory

Output depends on both present inputs and past

outputs.
Memory (via feedback loop) contains past information.
Analysis Procedure
 Given a combinational circuit, can you analyze its
function?
A A+B
B F1 = (A+B).(A'+B')

F2 = (A'+B')' = A.B
A'+B'
 Steps: A B
0 0
(A+B) (A'+B') F1
0 1 0
F2
0
 1. Label the inputs and outputs. 0 1 1 1 1 0
1 0 1 1 1 0
 2. Obtain the functions of 1 1 1 0 0 1
intermediate points and the outputs.
 3. Draw the truth table.
 4. Deduce the functionality of the circuit.
Design Methods

 Different combinational circuit design methods:

 Gate-level method (with logic gates)

 Block-level design method

 Design methods make use of logic gates and useful functional

blocks.
 These are available as Integrated Circuit (IC) chips.
Design Methods

 Type of IC chips (based on packing density) :

 Small-scale integration (SSI): up to 12 gates

 Medium-scale integration (MSI): 12-99 gates

 Large-scale integration (LSI): 100-9999 gates

 Very large-scale integration (VLSI): 10,000-99,999 gates

 Ultra large-scale integration (ULSI): > 100,000 gates

Design Methods

 Main objectives of circuit design:

 (i) reduce cost

 reduce number of gates (for SSI circuits)

 reduce IC packages (for complex circuits)

 (ii) increase speed

 (iii) design simplicity (reuse blocks where possible)

Gate-level (SSI) Design: Half Adder
 Design procedure:
1) State Problem
Example: Build a Half Adder to add two bits
2) Determine and label the inputs & outputs of circuit.
Example: Two inputs and two outputs labelled, as
follows:

X Y C S
X S 0 0 0 0
Half
0 1 0 1
Y Adder C 1 0 0 1
1 1 1 0
(X + Y)

3) Draw truth table.

Gate-level (SSI) Design: Half Adder
4) Obtain simplified Boolean function. X Y C S
0 0 0 0
Example: C = XY 0 1 0 1
S = X'Y + XY' = XY 1 0 0 1
1 1 1 0

5) Draw logic diagram.

X
Y S

Half Adder
C
Gate-level (SSI) Design: Full Adder
 Half-adder adds up only two bits.
 To add two binary numbers, we need to add 3
bits (including the carry).
 Example: 1
0
1
0
1
1 1
carry
X
+ 0 1 1 1 Y
1 0 1 0 S

 Need Full Adder (so called as it can be made from

two half-adders).
X
Full S
Y
Z
Adder C
(X + Y + Z)
Gate-level (SSI) Design: Full Adder
 Truth table:
X Y Z C S
Note:
0 0 0 0 0
0 0 1 0 1 Z - carry in (to the current
0 1 0 0 1 position)
0 1 1 1 0 C - carry out (to the next position)
1 0 0 0 1
1 0 1 1 0 C
YZ
1 1 0 1 0 X
00 01 11 10
1 1 1 1 1 0 1

 Using K-map, simplified SOP 1 1 1 1

form: YZ S
00 01 11 10
C = XY + XZ + YZ X
0 1 1
S = X'Y'Z + X'YZ'+XY'Z'+XYZ
1 1 1
Gate-level (SSI) Design: Full Adder
 Circuit for above formulae:
C = XY + (XY)Z
S = (XY)Z

X (XY)
Y S

(XY)

Full Adder made from two Half-Adders (+ OR gate).

Gate-level (SSI) Design: Full Adder
 Circuit for above formulae:
C = XY + (XY)Z
Block diagrams.
S = (XY)Z

X (XY)
X Sum X
Y Sum S
Y Y
Half Half
Adder Adder
(XY)
Carry Carry
C

Full Adder made from two Half-Adders (+ OR gate).

Code Converters
 Code converters – take an input code, translate to its
equivalent output code.

Input Code Output

code converter code

 Example: BCD to Excess-3 Code Converter.

Input: BCD digit
Output: Excess-3 digit
BCD-to-Excess-3 Code Converter
 Truth table:  K-maps:
C C
BCD Excess-3 CD CD
AB 00 01 11 10 AB 00 01 11 10
A B C D W X Y Z
00 00 1 1 1
0 0 0 0 0 0 0 1 1
1 0 0 0 1 0 1 0 0 01 1 1 1 01 1
B B
2 0 0 1 0 0 1 0 1 11 X X X X 11 X X X X
3 0 0 1 1 0 1 1 0 A A
10 1 1 X X 10 1 X X
4 0 1 0 0 0 1 1 1
5 0 1 0 1 1 0 0 0 W D
X D

6 0 1 1 0 1 0 0 1
7 0 1 1 1 1 0 1 0
C C
8 1 0 0 0 1 0 1 1 CD CD
AB 00 01 11 10 AB 00 01 11 10
9 1 0 0 1 1 1 0 0
00 1 1 00 1 1
10 1 0 1 0 X X X X
11 1 0 1 1 X X X X 01 1 1 01 1 1
B B
12 1 1 0 0 X X X X 11 X X X X 11 X X X X
13 1 1 0 1 X X X X A A
10 1 X X 10 1 X X
14 1 1 1 0 X X X X
15 1 1 1 1 X X X X Y D
Z D
BCD-to-Excess-3 Code Converter
C C
CD CD
AB 00 01 11 10 AB 00 01 11 10
00 00 1 1 1 W = A + BC + BD
01 1 1 1 01 1
B B
11 X X X X 11 X X X X
A
10 1 1 X X
A
10 1 X X X = B'C + B'D + BC'D'
D D
W X
Y = CD + C'D'
C C
CD CD
AB 00 01 11 10 AB 00 01 11 10
00 1 1 00 1 1 Z = D'
01 1 1 01 1 1
B B
11 X X X X 11 X X X X
A A
10 1 X X 10 1 X X

D D
Y Z
 BCD-to-Excess-3 Code Converter
A B C D

Z
4-bit Parallel Adder
 Consider a circuit to add two 4-bit numbers together
and a carry-in, to produce a 5-bit result:
X 4 X 3 X2 X 1 Y 4 Y 3 Y 2 Y1

C5
4-bit
Parallel Adder C1

Black-box view of 4-bit

S 4 S3 S2 S 1 parallel adder

 5-bit result is sufficient because the largest result is:

(1111)2+(1111)2+(1)2 = (11111)2
4-bit Parallel Adder
 Alternative design possible.
 Addition formulae for each pair of bits (with carry in),
Ci+1Si = Xi + Yi + Ci
has the same function as a full adder.
Ci+1 = Xi Yi + (Xi  Yi ) Ci
Si = Xi  Yi  Ci
4-bit Parallel Adder
 Cascading 4 full adders via their carries, we get:
Y4 X4 Y3 X3 Y 2 X2 Y1 X1
C4 C3 C2

C5 FA FA FA FA C1

S4 S3 S2 S1
Input
Output
Parallel Adders

 Note that carry propagated by cascading the carry from one full
adder to the next.

 Called Parallel Adder because inputs are presented

simultaneously (in parallel). Also, called Ripple-Carry Adder.
BCD-to-Excess-3 Code Converter
 Excess-3 code can be BCD Excess-3
converted from BCD code 0
A
0
B C
0 0
D
0
W X Y Z
0 0 1 1
using truth table: 1 0 0 0 1 0 1 0 0
2 0 0 1 0 0 1 0 1

 Gate-level design can be 3

4
0
0
0 1
1 0
1
0
0 1 1 0
0 1 1 1
5 0 1 0 1 1 0 0 0
used since only 4 inputs. 6 0 1 1 0 1 0 0 1

 However, alternative design 7

8
0
1
1 1
0 0
1
0
1 0 1 0
1 0 1 1
possible. 9
10
1
1
0 0
0 1
1
0
1 1 0 0
X X X X
 Use problem-specific 11
12
1
1
0 1
1 0
1
0
X X X X
X X X X
formula: 13
14
1
1
1 0
1 1
1
0
X X X X
X X X X
Excess-3 Code 15 1 1 1 1 X X X X

= BCD Code + (0011)2

BCD-to-Excess-3 Code Converter
Excess-3 Code = BCD Code + (0011)2
 Block-level circuit: unused

Cout
X4
BCD X3

4-bit Parallel
code X2 S4

Adder
X1 S3 Excess-3
0 Y4 S2 code
0 Y3 S1
1 Y2
1 Y1 Cin
A BCD-to-Excess-3
Code Converter 0
16-bit Parallel Adder
 Larger parallel adders can be built from smaller ones.
 Example: a 16-bit parallel adder can be constructed
from four 4-bit parallel adders:
X16..X13 Y16..Y13 X12..X9 Y12..Y9 X8..X5 Y8..Y5 X4..X1 Y4..Y1
4 4 4 4 4 4 4 4

C17 4-bit // C13 4-bit // C9 4-bit // C5 4-bit // C1

adder adder adder adder
4 4 4 4

S16..S13 S12..S9 S8..S5 S4..S1

A 16-bit parallel adder

16-bit Parallel Adder
 Shortened notation for multiple lines.

4 is a shortened
notation for
S4 .. S1 S4 S3 S2 S1

Such ripple-carry circuits are “slow” because of long delays

needed to propagate the carries.
4-bit Parallel Adder combined with
Subtractor
 Subtraction can be performed through addition using
2s-complement numbers.
 Hence, we can design a circuit which can perform
both addition and subtraction, using a parallel adder.
X 4 X3 X2 X 1 Y4 Y3 Y2 Y1

4-bit adder S: control signal

cum subtractor for add/subtract

Result: either X+Y or X-Y

4-bit Parallel Adder cum Subtractor
 The control signal S=0 means add
S=1 means subtract
 Recall that:
X-Y = X + (-Y)
= X + (2’s complement of Y)
= X + (1’s complement of Y) +1
X+Y = X + (Y)
4-bit Parallel Adder cum Subtractor
 Design requires:
(i) XOR gates:

Y Y Y Y'
S=0 S=1

such that: output = Y when S=0

= Y' when S=1

(ii) S connected to carry-in.

4-bit Parallel Adder cum Subtractor
 Adder cum subtractor circuit:
Y4 Y3 Y2 Y1

S
X 4 X 3 X2 X 1

C Cout 4-bit Cin

parallel adder Analysis:
If S=1, then
X + (1's complement of Y) +1
S 4 S 3 S2 S 1 appears as the result.
A 4-bit adder cum subtractor If S=0, then X+Y appears as
the result.
Combinational Circuits
Decoder:
 Is combinational circuit.
 Accepts the set of inputs that represents a binary number and
activates only that output corresponding to the input number,
all other outputs remain inactive.
 There are 2n possible input combinations.
 For each of these combinations only one output will be HIGH
(active), the other outputs are LOW.
 Decoder has one or more ENABLE (E ) inputs that are used
to control the operations of decoder.
Combinational Circuits
Decoder:
Combinational Circuits
Decoder:

D0 to D7

Only one output is HIGH

Combinational Circuits
Encoder:
 Is combinational circuit.
 Perform inverse operations of Decoder.
 Encoder converts an active input signal into a coded output
signal.
 Only one input is HIGH (active) and produces an output code
depending on which input is activated.
Combinational Circuits
Encoder:
Combinational Circuits
Encoder:
Combinational Circuits
Multiplexer:
 Is combinational circuit.
 selects binary information from one of many input lines and
directs it to a single output line.
 The selection of a particular input line is controlled by a set of
selection lines.
 There are 2n input lines and n selection lines whose bit
combinations determine which input is selected.
Combinational Circuits
Multiplexer:
Combinational Circuits
Multiplexer:
Combinational Circuits
Demultiplexer:
 Is combinational circuit.
 Perform inverse operations of Multiplexer.
Sequential Circuits

Present output depends on both present input as well

as past outputs.

inputs Combinational outputs

:: Logic
::

Memory

Latch/Flip-Flop
Sequential Circuits
Latch and Flip-Flop

Clock

• The state of a latch or flip-flop is switched by a change in the control

input (Clock).
• Latch is memory element that responds to a change in the level of a
clock pulse.
• Flip-flop is memory element that responds to a change in the edge of a
clock pulse (low to high or high to low).
Flip-Flop
D Flip-Flop
• Data Flip-flop.
• When the input pulse changes to the logic-1 level, the
data from the external D input are transferred to Q.
 D Flip-Flop

• Flip-flop responds to the edge transition of the clock.

• (a) When input clock in the positive-edge triggered flip-flop
makes a positive transition, the value of D is transferred to Q.
• (b) When input clock in the Negative-edge triggered flip-flop
makes a negative transition, the value of D is transferred to Q.