SystemVerilog Data Types Summary
SystemVerilog Data Types Summary
Overview
Built-In Data Types
•Logic Type:
•A 4-state data type (0, 1, X, Z), used to represent
unknown or high-impedance states.
•Useful for hardware modeling to simulate
realistic scenarios.
•Example: logic [3:0] signal;
•2-State Types:
•Types like bit, byte, int, and shortint store only 0
or 1 values.
•Provide faster simulation since they do not
account for X or Z states.
•Example: bit flag;
•Floating-Point and Strings:
•real: For fractional values.
•string: Dynamic and supports rich text
manipulation.
2. Definition:Fixed-Size Arrays
•Arrays with a defined size at compile-time.
•Example: int my_array[10]; declares an array of 1
•Initialization:
•Arrays can be initialized inline: int array[3] = '{1, 2
•Operations:
•Use for and foreach loops for iteration.
•Copy (=) and compare (==) operations are straigh
•Example: foreach(my_array[i]) my_array[i] = i;
•Packed Arrays:
•Contiguous bit-level storage.
•Ideal for efficient bit manipulations in hardware d
•Example: bit [7:0] packed_array;
Introduction to Data Types
• Covers built-in types such as 'logic', 'bit', and
'int'. Introduces 2-state and 4-state types.
Fixed-Size Arrays
• Explanation of array declaration, initialization,
and operations like 'foreach' and 'for' loops.
Dynamic and Associative Arrays
• Dynamic arrays for flexible sizes and
associative arrays for key-value pairs.
Array Methods
• Includes reduction methods, sorting, and
locator functions like 'find', 'min', and 'max'.
Structures and Unions
• How to use 'struct' and 'union' to define
complex data types.
Typedefs
• Defines new data types using 'typedef' for
clarity and reusability.
Enumerated Types
• Declares enums for readable constants and
their associated methods.
Strings and Constants
• Discusses string manipulation methods and
the use of 'const' for constant values.