UNIT-I

VLSI design methodology, VLSI technology- NMOS, CMOS and BICMOS circuit fabrication.
Layout design rules. Stick diagram. Latch up.

Presented by
Dr. B. Chandrababu Naik
Assistant Professor
Department of ECE
NIT- Tiruchirappalli
Tamil Nadu - 620015, India.

8
 Introduction

• The transistor, the heart of electronics and one of the most important inventions in 1947.

• The second enormous step, the invention of the integrated circuit in 1959.
• An Integrated Circuit (IC, Microchip, Chip) is an electronic circuit made up of small semiconductor
devices and other electronic components.
• More than sixty years since the invention of integrated circuits technology and there has been
extraordinary escalation of the electronic industry with a massive impact on the way people live and work.
• In the last thirty years or so, by far the area of the industry with most developments have been in the Very
Large-Scale Integration (VLSI) of silicon chips.
• Integrated circuit design is becoming much more complicated task as design extended across VLSI and
technology scaling makes the chip density higher. Therefore, nowadays chip design is concerning the
optimal trade-off between various facts such as performance, power, area, etc.
 Table.1 Classification of integrated circuits.
Name of the Integrated circuit Year Number of Number of
Transistors Logic Gates

Small-Scale Integration
1964 1 to 10 1 to 12
(SSI)

Medium-Scale Integration
1968 10 to 500 13 to 99
(MSI)

Large-Scale Integration
1971 500 to 20000 100 to 9999
(LSI)

Very Large-Scale Integration 20000 to

1980 10000 to 99 999
(VLSI) 1000000

Ultra-Large-Scale Integration 1000000 and

1984 100000 and more
(ULSI) more
Fig. Dimensions of VLSI optimization.
• Integrated circuit design has evolved through some eras and nowadays VLSI is also feasible and available.
However, there are two major portions of the IC design in the nature.
• General integrated circuit design steps are follows whether it is a digital or analog.
• Digital Integrated circuits deploys only few discrete states of transistors, which is consist of billions of
transistors with VLSI. Digital IC design refer to production of components such as Microprocessor,
Memories (RAM, ROM and FLASH), FPGA, ASIC, NOC, and SOC.
• Digital design mostly focus on
• Logical correctness
• Maximizing circuit density
• Placing circuits in a way so that clock and timing signal can be routed efferently.
Moore's Law
• Moore's Law states that the number of transistors on a microchip doubles about every two years, though
the cost of computers is halved.
• In 1965, Gordon E. Moore, the co-founder of Intel, made this observation that became known as Moore's
Law.
• Another principle of Moore's Law says that the growth of microprocessors is exponential.
Table 2: Most significant technology nodes over the past 20 years and prospective vision for 2023- 2027

The processor die size has been reduced over the past node generations
Main roles in VLSI industry

• RTL Engineer (coding)

• DFT Engineer (testing)
• Synthesis Engineer (netlist optimization)
• PD Engineer (layout level)
Required skills

• Basic knowledge Electronics subjects (EDC, STLD, ANALOG CKT, VLSI)

• Basic unix/linux commands
• TCL/PERL/C languages
List of TCL
• 00_init.tcl
• User_settings.tcl
• 01_place.tcl
• 03_cts.tcl • Project .tcl
• 04_cts_opt.tcl • Lib .tcl
• 06_route.tcl • Tool_settings .tcl
• 07_route_opt.tcl
Fig.. ASIC design flow
Design Objectives and Challenges
 Challenges Seen As Technology Shrinks

• Channel length reduces

• Coupling capacitance increases
• Size reduces
• More complex design
• More leakage power impact
• More placement issues
• DFM & Yield issues
• More colour violations
• DRC’S increases as technology decreases
• More runtime and iterations
• In cutoff region there is no conduction between drain to source.
• Channel formation happened due to VGS – VTh
• Pinch off region happened at VDS= VGS-VTh
• For Linear region VDS < VGS-VTh
• For Saturation region VDS > VGS-VTh
Advantages and disadvantages of MOSFET

Applications of MOSFET

• It is used as an inverter.
• It is used in digital circuits.
• It is used as a passive element, like in an inductor, resistor,
and capacitor.
• It is used as a high-frequency amplifier.
• It is used in brushless DC motor drives.
• It is used in electronic DC relays.
• It is used in SMPS.
Example Problems on MOSFET
 NMOS FABRICATION PROCESS
BASIC STEPS OF FABRICATION
• The fabrication cycle of VLSI chips consists of a sequential set of basic steps which are wafer preparation, oxidation,
lithography and etching.
• During fabrication process, the devices are created on the chip. So, IC may be viewed as a set of patterned layers.
• A layer must be patterned before the next layer of material is applied on the chip.
• Pattering uses the process of lithography. The process used to transfer a pattern to a layer on the chip is called
lithography.
• The lithography sequence must be repeated for every layer
1. Processing is carried out on a thin wafer cut from a single crystal of silicon of high purity into which the required p-
impurities are introduced as the crystal is grown.

2. A layer of silicon dioxide (Si02), typically 1 μm thick, is grown all over the surface of the wafer to protect the surface, act as
a barrier to dopants during processing.

3. The surface is now covered with a photo resist which is deposited onto the wafer and spun to achieve an even distribution of
the required thickness.

4. The photo resist layer is then exposed to ultraviolet light through a mask which defines those regions into which diffusion is
to take place together with transistor channels. Assume, for example, that those areas exposed to ultraviolet radiation are
polymerized (hardened), but that the areas required for diffusion are shielded by the mask and remain unaffected.

5. These areas are subsequently readily etched away together with the underlying silicon dioxide so that the wafer surface is
exposed in the window defined by the mask

6. The remaining photoresist is removed and a thin layer of Si02 (0.1 𝝻m typical) is grown over the entire chip surface and
then polysilicon is deposited on top of this to form the gate structure.

7. Further photo resist coating and masking allows the polysilicon to be patterned (as shown in Step 6) and then the thin oxide
is removed to expose areas into which n- type impurities are to be diffused to form the source and drain as shown.
8. Thick oxide (Si02) is grown over all again and is then masked with photoresist and etched to expose selected arcs of
the polysilicon gate and the drain and source areas where connections (i.e. contact cuts) are to be made.

9. The whole chip then has metal (aluminum) deposited over its surface to a thickness typically of 1μm. This metal layer
is then masked and etched to form the required interconnection pattern
 CMOS Fabrication Process
• CMOS - Complementary Metal Oxide Semiconductor
or
• COS - MOS – Complementary Symmetry Metal Oxide Semiconductor
• CMOS is an arrangement of two complementary and symmetrical MOSFET
• CMOS is used in Micro Processor and Micro Controller.
Applications
Applications
 Latch up
• Latch up is condition in which low impedance path is formed between VDD and Ground. Due to that direct current
flow from VDD to Ground and that may damage the CMOS circuit.
Condition 1: If Vin or Vout > Vdd
Condition 2: If Vin or Vout < Gnd
Latch up prevention steps:

• By Gold impurities in substrate, we can minimize the latch up

• By using epitaxial layer at substrate
• Place substrate and well as close as possible
• Avoid forward bias of source and drain
• PMOS close to VDD and NMOS close to ground