Digital Circuit Design

Unit-V
Hardware Description Language: VERILOG
 Unit-V:
Hardware Description Language: Introduction to Verilog as HDL-gate
level, behavioral level and structural level modeling of logic circuits.

Module, Test bench, Keywords, Identifiers, White Space, Characters,

Comments, Numbers, Strings, Logic Values, Data Types, Scalars and
Vectors

Continuous Assignment Structure, Delays and Continuous Assignments,

Assignment to Vector.

Verilog for combinational circuits - conditional operator, if-else statement,

case statement, for loop,

Verilog Operators

using Verilog constructs for storage elements,

Blocking and Non-blocking Assignments.

Contents
Concurrency
Simulation
Synthesis
Programming Language Interface(PLI)
Module
Contents
Language Constructs and Conventions
Module
Introduction
Keywords
Identifiers
White
space characters
Comments
Numbers
Strings
Logic Values
Data Types
Scalarsand Vectors
Operators
Concurrency
 In an electronic circuit all the units are to be active and
functioning concurrently.
 The voltages and currents in the different elements in the circuit
can change simultaneously.
 In turn the logic levels too can change.
 Simulation of such a circuit in an HDL calls for concurrency of
operation.
 Verilog simulators are built to simulate concurrency.
 This is in contrast to programs in the normal languages like C
where execution is sequential
 In some cases the circuit itself may demand sequential
operation as with data transfer and memory-based operations.
 Only in such cases sequential operation is ensured by the
appropriate usage of sequential constructs from Verilog HDL

SIMULATION :
It is The Process of applying inputs and verifying the Outputs.

SYNTHESIS:
Translation of the debugged design into the corresponding
hardware circuit (using an FPGA or an ASIC) is called
"synthesis."
Programming Language
Interface(PLI)
 PLI provides an active interface to a compiled Verilog module.
 The interface adds a new dimension to working with Verilog
routines from a C platform.
 The key functions of the interface are as follows:
 One can read data from a file and pass it to a Verilog module as
input. Such data can be test vectors or other input data to the
module.
 Similarly, variables in Verilog modules can be accessed and
their values written to output devices.
 Delay values, logic values, etc., within a module can be accessed
and altered.
 Blocks written in C language can be linked to Verilog modules.

Verilog PLI (Programming Language Interface) is a mechanism to

invoke C or C++ functions to Verilog code.
 Example 1:
MODULE
 Any Verilog program begins with a keyword - called a "module."
 A module is the name given to any system considering it as a
black box with input and output terminals
The terminals of the module are referred to as 'ports'. The ports
attached to a module can be of three types:
• Input: ports through which one gets entry into the module, they
signify the input signal terminals of the module.
• Output: ports through which one exits the module, these signify
the output signal terminals of the module.
• inout : These represent ports through which one gets entry into the
module or exits the module, These are terminals through which
signals are input to the module sometimes, at some other times
signals are output from the module through these.
• A module comprises a number of "lexical tokens" arranged
according to some pre defined order.
• The possible tokens are of seven categories:
 White spaces
 Comments
 Operators
 Numbers
 Strings
 Identifiers
 Keywords
• In Verilog any program which forms a design description is a
"module." Any program written to test a design description is
also a "module."
• The latter are often called as "stimulus modules" or "test
benches."
• Verilog takes the active statements appearing between the
"module" statement and the "endmodule" statement and
interprets all of them together as forming the body of the
module.
 LANGUAGE CONSTRUCTS AND
CONVENTIONS IN VERILOG
INTRODUCTION
 The constructs and conventions make up a software language.
 A clear understanding and familiarity of these is essential for the
mastery of the language.
 Verilog has its own constructs and conventions
 In many respects they resemble those of C language.
 Any source file in Verilog (as with any file in any other
programming language) is made up of a number of ASCII
characters.
 The characters are grouped into sets-referred to as "lexical

tokens.“
lexical tokens
 A lexical token in Verilog can be a single character or a group of
characters. Verilog has 7 types of lexical tokens
1. operators
2. Keywords
3. Identifiers
4. white spaces
5. comments
6. numbers
7. strings.
Case Sensitivity

Verilog is a case-sensitive language like C. Thus sense, Sense,

SENSE, SENse,... etc., are all treated as different entities/quantities
in Verilog.

Keywords
 The keywords define the language constructs.
 A keyword signifies an activity to be carried out, initiated, or
terminated.
 As such, a programmer cannot use a keyword for any purpose
other than that it is intended for.
 All keywords in Verilog are in small letters and require to be
used as such (since Verilog is a case- sensitive language).
 All keywords appear in the text in New Courier Bold-type
letters.
Examples
 module-signifies the beginning of a module definition.
 endmodule-signifies the end of a module definition.
 begin-signifies the beginning of a block of statements.
 end -signifies the end of a block of statements.
 if -signifies a conditional activity to be checked
 while-signifies a conditional activity to be carried out.
Identifiers
 Any program requires blocks of statements, signals, etc., to be
identified with an attached nametag. Such nametags are identifiers.
 It is good practice for us to use identifiers, closely related to the
significance of variable, signal, block, etc., concerned.
 This eases understanding and debugging of any program.
e.g., clock, enable, gate_1, . . .
 There are some restrictions in assigning identifier names.
 All characters of the alphabet or an underscore can be used as the
first character. Subsequent characters can be of alphanumeric type,
or the underscore (_), or the dollar ($) sign
for example
 name, _name. Name, name1, name_$, . . .all these are allowed
as identifiers
 name aa  not allowed as an identifier because of the blank
( “name” and “aa” are interpreted as two different identifiers)
 $name  not allowed as an identifier because of the presence of
“$” as the first character.
 1_name  not allowed as an identifier, since the numeral “1” is
the first character
 @name  not allowed as an identifier because of the presence
of the character “@”.
 A+b  not allowed as an identifier because of the presence of
the character “+”
White Space Characters
 Blanks (\b), tabs (\t) and newlines (\n) are the white space
characters in Verilog.
 In any design description, the white space characters are included
to improve readability.
 Functionally, they separate legal tokens. They are introduced
between keywords, keyword and an identifier, between two
identifiers, between identifiers and operator symbols, and so on.
 White space characters have significance only when they appear
inside strings
Comments
 It is a healthy practice to comment a design description liberally –
as with any other program.
 Comments are incorporated in two ways. A single line comment
begins with “//” and ends with a new line
 for example
module d_ff (Q, dp, clk); //This is the design description of a D
flip-flop.
//Here Q is the output.
// dp is the input and clk is the clock.
 One can incorporate multiline comments also without resorting to
“//” at every line.
 For such multiline comments “/*” signifies the beginning of a
comment and “*/” its end.
 All lines appearing between these two symbol combinations are
together treated as a single block comment
for example
module d_ff (Q, dp, clk);
/* This module forms the design description of a d_flip_flop wherein
Q is the output of the flip-flop ,
dp is the data input and
clk the clock input*/
 Multiline comments cannot be nested. For example, the
following comment is not valid.
/* The following forms the design description of a D flip-flop
/*which can be modified to form other types of flip-flops*/ with
clock and data inputs.*/
A valid alternative can be as follows:-
/* The following forms the design description of a D flip-flop
(which can be modified to form other types of flip-flops) with
clock and data inputs */
Numbers
 Frequently numbers need to be specified in a design description. Logic
status of signal lines, buses, delay values, and numbers to be loaded in
registers are examples.
 The numbers can be of integer type or real type.
1. Integer Numbers
2. Real Numbers

Integer Numbers
Integers can be represented in two ways.
In the first case it is a decimal number- signed or unsigned
 an unsigned number is automatically taken as a positive number.
 Some examples of valid number representations of this category
are given below:
2
25
253
-253

 The following are invalid since non decimal representations are

not permissible.
2a
B8
-2a
-B8
 Normally the number is taken as 32 bits wide.
 Thus all the following numbers are assigned 32 bits of width:
2
25
253
-2
-25
-253
 If a design description has a number specified in the form given
here, the circuit synthesizer program will assign 32 bits of width
to it and to all the related circuits.
 The alternate form of number representation is more specific
though elaborate.
 The number can be specified in binary, octal, decimal, or
hexadecimal form.
 The representation has three tokens with an optional sign
preceding it.
 Figure 3.1 shows typical number representations with the
significance of each field explained separately.
Real numbers
 Real numbers can be specified in decimal or scientific notation.
The decimal notation has the form -a.b
 where a, b, the negative sign, and the decimal point have the
usual significance The fields a and b must be present in the
number.
 A number can be specified in scientific notation
4.3e2
where 4.3 is the mantissa and 2 the exponent.
 The decimal equivalent of this number is 430. Other examples of
numbers represented in scientific notation are
4.3e2, -4.3e-2, and 4.3e-2.
Strings
 A string is a sequence of characters enclosed within double quotes.
 A string must be contained on a single line. that is, it cannot be
carried over to two lines with a carriage return.
 Special characters are specified by preceding them with the “\”
character.
 Verilog treats a string as a sequence of ASCII characters
 for example,
“This is a string”
“This string is one \t with a gap in between”
“This is called a \”string\””.
 When a string of ASCII characters as above is an operand in an
expression, it is treated as a binary number.
 This binary number is formed by replacing each ASCII
character by 8 bits – a 0 bit followed by the 7-bit ASCII
equivalent – and treating the resulting binary sequence as a
single binary number.
 For example, the statement (with P defined as a 32-bit vector
beforehand)
P = “numb”
assigns the binary value
0110 1110 0111 0101 0110 1101 0110 0010 to P (0110 1110, 0111
0101, 0110 1101 and 0110 0010 are the 8-bit equivalents of the
letters n, u, m, and b, respectively).
Logic Values
 Signal lines, logic values appearing on signal lines, etc., can
normally take two logic levels:
1  signifies the 1 or high or true level
0  signifies the 0 or low or false level.
 Two additional levels are also possible – designated as x and z.
 Here x represents an unknown or an uninitialized value. This
corresponds to the don‘t care case in logic circuits.
 z represents / signifies a high impedance state. This is possible
when a signal line is tri-stated or left floating.
The following are note worthy here:
 When a variable in an expression is in the z state, the effect is
the same as it having z value. But when an input to a gate is in
the z state, it is equivalent to having the x value.
 If the input to a MOS switch is in the z state, its output also
remains at the z state.
 With a few exceptions all data types in Verilog can take on all
the 4 logic values or levels. The event is an exception to this. It
cannot store any value. The trireg cannot take on the z value
Data Types
 The data handled in Verilog fall into two categories:
(i) Net data type (ii) Variable data type
 The two types differ in the way they are used as well as with
regard to their respective hardware structures.
 Data type of each variable or signal has to be declared prior to its
use. The same is valid within the concerned block or module.
Net Data Type
 A net signifies a connection from one circuit unit to another. Such
a net carries the value of the signal it is connected to and
transmits to the circuit blocks connected to it.
 If the driving end of a net is left floating, the net goes to the high
impedance state.
 A net can be specified in different ways.
wire: It represents a simple wire doing an interconnection. Only one
output is connected to a wire and is driven by that.
tri: It represents a simple signal line as a wire. Unlike the wire, a
tri can be driven by more than one signal outputs. Functionally,
wire and tri are identical. Distinct nomenclatures are provided
for the convenience of assigning roles.
Variable Data Type
 A variable is an abstraction for a storage device. It can be declared
through the keyword reg and stores the value of a logic level: 0, 1,
x, or z.
 A net or wire connected to a reg takes on the value stored in the
reg and can be used as input to other circuit elements.
 But the output of a circuit cannot be connected to a reg.
 The value stored in a reg is changed through a fresh assignment in
the program. time, integer, real, and realtime are the other variable
types of data; these are dealt with later.
Scalars and Vectors
 Entities representing single bits — whether the bit is stored,
changed, or transferred are called scalars
 Often multiple lines carry signals in a cluster – like data bus,
address bus, and so on. Similarly, a group of regs stores a value,
which may be assigned, changed, and handled together.
 The collection here is treated as a vector.
 Below figure illustrates the difference between a scalar and a vector.
 wr and rd are two scalar nets connecting two circuit blocks circuit1
and circuit2.
 b is a 4-bit-wide vector net connecting the same two blocks. b[0],
b[1], b[2], and b[3] are the individual bits of vector b. They are part
vectors.
 A vector reg or net is declared at the outset in a Verilog program
and hence treated as such. The range of a vector is specified by a
set of 2 digits (or expressions evaluating to a digit) with a colon
in between the two. The combination is enclosed within square
brackets.
 wire[3:0] a; /* a is a four bit vector of net type; the bits are
designated as a[3], a[2], a[1] and a[0]. */
 reg[2:0] b; /* b is a three bit vector of reg type; the bits are
designated as b[2], b[1] and b[0]. */
 reg[4:2] c; /* c is a three bit vector of reg type; the bits are
designated as c[4], c[3] and c[2]. */
 wire[-2:2] d ; /* d is a 5 bit vector with individual bits designated
as d[-2], d[-1], d[0], d[1] and d[2]. */
 Whenever a range is not specified for a net or a reg, the same is
treated as a scalar – a single bit quantity.
 In the range specification of a vector the most significant bit and
the least significant bit can be assigned specific integer values.
 These can also be expressions evaluating to integer constants –
positive or negative.
 Normally vectors – nets or regs are treated as unsigned quantities.
They have to be specifically declared as signed if so desired.
Examples
wire signed[4:0] num; // num is a vector in the range -16 to +15.
reg signed [3:0] num_1; // num_1 is a vector in the range -8 to
+7.
Operators
 Verilog has a number of operators similar to the C language.
These are of three types:
1. Unary: the unary operator is associated with a single operand.
The operator precedes the operand – for example, ~a.
2. Binary: the binary operator is associated with two operands. The
operator appears between the two operands – for example, a&b.
3. Ternary: the ternary operator is associated with three operands.
The two operators together constitute a ternary operation. The
two operators separate the three operands
for example
a?b:c // Here the operators “?” and “:” together define an operation