UNIT V

ASIC DESIGN AND

TESTING

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 2

1.Introduction to wafer to chip

fabrication process flow

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Introduction:
3

 Hundreds of process
 Manufacturing process has 8 steps
1. Wafer processing
2. Oxidation
3. Photolithography
4. Etching
5. Deposition and ion implementation
6. Metal wiring
7. Testing
8. Packaging

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Semiconductor Manufacturing process:
4

SAND SILICON WAFER CHIP

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Steps involved in chip fabrication process:
5
Step Process Operation
1 Wafer Foundation for semiconductor
2 Oxidation Create oxide flim on wafer surface
3 Photolithography Draw circuit design on wafer
4 Etching Remove unnecessary materials
5 Deposition and ion Coating thin flim at a desired molecular or atomic level
implementation on to a wafer
6 Metal wiring Allows electricity to flow by depositing a thin metal
flim
7 EDS Process of testing to ensure flawless semiconductor
chips
8 Packaging Final wafer are cut into individual semiconductor chips

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1.1.Silicon Wafer manufacturing:
6

 Starts with a grain of sand

 Wafer is a round slice formed by cutting a single crystal
 To get high purity silicon material, silica sand is needed
 Wafer processing is the process of making and obtaining wafers.

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1.2.Oxidation
7

 Silicon wafer get in step 1 is not in conductive

 Need to convert in semiconductive
 First oxygen or water vapor is sprayed to form uniform oxide film

Remove Thermal Oxide film

impurities oxidation test
 2 types of Oxidation
Dry Oxidation Method Wet Oxidation Method
Use oxygen Use water vapor
Slow speed and thin oxide Fast speed and thick oxide
layer layer

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1.3.Photolithography:Photomask:
8

 Print circuit patterns onto a wafer by using light.

 When light transfers the circuit is drawn on the wafer surface
 After inspection need to check the pattern is drawn well.
 3 steps
 Photoresist coating
 Exposure
 Development
 2 types
 Positive glue
 Negative glue

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1.4.Etching:
9

 Its time to remove unnecessary materials from the wafer surface

 Using liquid or gas for etching process
 Unnecessary materials are selectively removed to draw the
desired design
 2 types of Etching
 Wet etching
 Chemical solutions are used

 Dry etching
 Gas or Plasma are used

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1.5. Deposition and ion implementation(Implantation)
10

 Coating a thin film at a desired molecular on to a wafer

 To get a semiconductor electrical characteristics Ion
implementation is needed
 Low temperature technique
 Adding impurities into the semiconductor
 Used to adjust the threshold voltage

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1.6.Metal wiring:
11

 Electrical signal must be applied

 Necessary to create a path for electricity, according the circuit
pattern.
 Depositing a thin metal film using materials such as aluminum,
titanium or tungsten

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1.7.Testing:
12

 Process of testing to ensure flawless semiconductor chips

 Testing used to sort out defective chips

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1.7.Packaging:
13

 Last process in manufacturing

 Cut into individual semiconductor chips

 individual chip must have a path to electrical signals with the

outside
 Protect from various external elements

 Saw chips are placed on the PCB board

 After final test Sealing and labeling the

Product name, the semiconductor chip

we commonly see.

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 14

2. Microchip Design Process

And Issues In Test And
Verification Of Complex Chips

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2.1.Introduction:
15

 Microchip is also called a chip or computer chip or Integrated

circuit(IC)
 Unit of integrated circuitry that is manufactured at a microscopic
scale using a semiconductor material such as silicon or
germanium
 Electronic components such as transistors and resistors are etched.
 Link the components together and facilitate the flow of electric
signals
 So small and measured in nanometers(nm)
 Fit billions of components on a single chip.

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Chip Design:
16
 Chip design is a Process of designing a chip and is an essential part of
electronics engineering
 Involves the circuit design and its logic formation
 Basic elements are transistors
 MOSFET is the basic building block of digital chips
 Advance EDA tools made the chips in more reliable and more scalable
 Physical size of transistors has decreased over past years.
 Chips consumes very less power in micro watts
 Algorithm is divided into 2 sub blocks
 Sub modules- intensive computation are taken to hardware
 Complex modules- dependent on data and are involved in decision
making are processed on the software.

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Chip Design flow:
17

 Very similar to the FPGA design

flow
 But the chips are manufactured

after the design is finalized

 Chip design flow is shown in figure

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Contd;
18

i. System specifications:
Defining and creating the specification of the system

ii. Architecture Design:

Decide which blocks are need to be used

iii.Basic Logic Design:

The basic Logic system is designed

iv.Logic Verification:
When schematic design is complete , next step is to verify the
system functionality
It can be done by using simulation tools
If any issues are find means it can be debugged in schematic

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Contd;
19
v. Physical Design Layout:
 Translate the system into physical level
 Schematic is converted into physical layout using building blocks

vi.Physical Design and Verification:

 Verification of Physical layout is required
 Multiple techniques are used
 Design Rule Check(DRC)-Check any violations like metal

spacing , contact sizes etc

 Layout Vs Schematic(LVS)-Check all the connections and

verifies them
 Timing and Power Analysis- Check any delay and timing issues

 Poor planning causes the less frequency of operation

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Contd;
20

vii.Fabrication and Final Testing:

Final step is the fabrication of physical design layout

All the libraries and layer information is provide by the

foundry
After the system is designed and verified .GDS file is

sent to foundry for verification

 Issues in Test and Verification:

 Specification problems
 Implementation problems
 Verification process

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 21

3. EMBEDDED CORES AND

SOCS

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3.1. Embedded Cores:
22
 Application specific and are built around a central core
 Hardware/ software systems are basically designed to regulate a physical
variable by sending some control signals.
 Input signals provided by end users
 Memory is responsible for holding the control algorithm
 The categories are
 General purpose and Domain specific processor
 Microprocessor and Microcontroller
 Digital signal processor
 Application Specific Integrated Circuits(ASIC’s)
 Programmable Logic Devices(PLD’s)
 Commercial Off-the shelf Components(COT’s)

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3.1. Embedded Cores cont.,
23

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3.1.1.General Purpose and Domain Specific Processor:
24
 Allows 80% of the embedded systems and processor /controller based.
 Depending on the domain and application
 Microprocessor:
 Dependent unit. It requires other hardware like memory, timer, controller
 2 different system
 Harvard- separate buses for data and memory
 Von-Neumann-Shared a single bus for both

 Microcontroller:
 Highly integrated chip that contains a CPU, RAM, Memory, I/O ports
 Instruction set of a microcontroller can be RISC or CISC
 Digital Signal Processor:
 Powerful special purpose processor to need computational demands and Power

constraints.
 2 to 3 times faster than general purpose microprocessors in signal Processing

Applications.
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3.1.2.Application Specific Integrated Circuits(ASIC)
25

 Microchip design to perform specific and unique applications

 Single chip for several functions
 Reduces the system development cost
 Single chip consumes very less area

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3.1.3.Programmable Logic Devices:
26

 An electronic component used to build digital circuits which re

reconfigurable
 Does not have a defined function while manufacturing
 Reconfigured any time to perform another function
 Inexpensive
 2 types
 Complex Programmable Logic Devices(CPLD){1000 Gates only}
 Field Programmable Gate Array(FPGA)
 Advantages of PLD:
 More flexibility
 Do not require long lead times
 Reprogrammed

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3.1.4.Commercial off the shelf components(COT’s)
27

 To provide easy integration and interoperability with existing

system components
 May be develop around general purpose 0r ASIC or PLD’s
 Advantages:
 Ready to use
 Easy to integrate
 Reduces Development time
 Disadvantages:
 Discontinued the production of COT’s

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3.1.5.System On Chip(SOC’s)
28

 Integrated circuit where all functional elements such as

dedicated hardware, processor, memory, I/O and Peripherals are
embedded into a single chip
 Most SOC’s use various pre designed hardware block which is
called IP cores.

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3.1.6.Design flow of SOC’s:
29

 Requires various SOC development

Skills and EDA tools.
1.Specifications:
Firststep to specify the requirements
Requirements need for both hardware

and Software
Must completely describe all the interfaces
Hardware and Software specifications

Needed

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3.1.6.Design flow of SOC’s cont.,
30
2. SOC Architecture Design:
 Gathering all the SOC specifications comes under architecture design
 Consist of behavioral and functional modeling
 In terms of combinational logic blocks, registers, buses, on & off chip
memories , switches and finite state machines, switches and FSM etc
 The design is portioned in Hardware and Software.

3. Software Development:
 Both Hardware and Software developed and tested.

4. SOC Hardware Development:

 After partition Hardware goes to various number of stages
 Where Hardware optimized based on a number of stages
 Then the design is simulated, tested, analyzed and refined.
3Modeling
High level modeling
RTL Design
Functional simulation and Hardware 12/24/2024
3.1.6.Design flow of SOC’s cont.,
31
5. Physical Design Implementation:
 process of translating the gate level
net list into a Physical layout
i. Floor Planning:
 Firststep of physical design
 Determines the area of aspect ratio and area
 Power planning is also done

ii. Logic Placement:

 All
standard cells in the design are placed and
Assigned a legal location
iii.Clock Tree Synthesis:
 Whilefloor planning & placement, the clock is considered as a ideal network
 Good quality clock is very crucial to meet the timing requirements

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3.1.6.Design flow of SOC’s cont.,
32
5. Physical Design Implementation contd.,:
iv. Routing:
 All standard cells are legally placed and the clock network is
synthesized
 Done during the routing stage
 After routing optimizations are performed

v. Timing Analysis and Signoff:

 After routing static timing analysis is performed
 It is critical to analyze the performance of the design

vi.Physical verification and signoff:

 Layout must verified
 The verification completes when it meets all specified rules

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3.1.6.Design flow of SOC’s cont.,
33
6.Design for manufacturing:
At the end of physical design the design is analyzed with simulation
All physical design checks and the bugs can be rectified and re-verified
Then the GDSII file sent to specified semiconductor fabrication plants it
is called fabrication or fabs.
GDSII consist only physical design
But the manufacturing process has 2 steps
Wafer Fabrication

Assembly

7.Post silicon Validation and Integration:

It offers the benefit of running at real time system speed in GHZ.
More complex due to the physical nature of validation target

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3.1.7.Advantages of SOC’s:
34
i. Compact Size:
 Integrating all the components into a single chip
ii. Low Power Consumption:
 Operating at lower power levels
iii. Cost effectiveness:
 More cost effective than traditional IC’s
iv. Improved Performance
v. Flexibility:
 It is more flexible and adaptable
vi. Reliability
vii.Integration of Advanced Features:
 Advanced features such as Artificial Intelligence and Machine learning
capabilities, enabling the development of intelligent electronic systems
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 35

4. INTRODUCTION TO
ASIC’S

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4.1.Introduction to ASIC’s:
36
 ASIC stands for Application Specific Integrated Circuit
 Performing a particular operation

 A silicon chip or IC is more properly called DIE

 Will have embedded CPU to manage the suitable tasks.

 Hardware Description Language (HDL) such as Verilog &VHDL is used

for implementing ASIC’s

 Advantages:

i. Better performance ii. High reliability

iii. More secure iv. Cheaper Cost
v. Lower power Dissipation vi. Faster Turn around time
 Disadvantages:
 It cannot be replaced

 Testing and debugging is very difficult

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4.2.Types of ASIC:
37

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4.2.Types of ASIC’s contd.,
38
1. Full
Custom ASIC:
 Some or all of the logic cells, circuits or layout specifically for one ASIC

are customized by the designer.

 Predesigned or Pretested cells are cannot be used in this design.

 Example: Microprocessor

 Advantages:

Custom design at physical level

Smallest, faster, and lower power circuit
High degree of optimization in performance and area
Substantial reduction in die area
Ability to integrate analog component and Pre designed Component
 Disadvantages:
 Increase Design time
 Expensive
 Complexity and high risk 12/24/2024
4.2.Types of ASIC’s contd.,
39
1. Full Custom ASIC contd.,

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4.1.1.Types of ASIC’s contd.,
40
2. Semi Custom ASIC contd.,
 Portion of the circuit is predefined and unalterable
 Other portions can be configured to meet the design specific needs
2 types of Semicustom IC’s
A. Standard Cell based ASIC’s
B. Gate Array Based ASIC’s
a. Standard Cell Based ASIC:
Reusing the library of cells called standard cell library
Mostly designed for digital logic features
Flexible block can be built from several rows of standard cells, it can also
be connected to other standard cells or full custom blocks

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4.1.1.Types of ASIC’s contd.,
41
2. Semi Custom ASIC contd.,
 CBIC’S:

Stands for Cell Based Integrated

Circuit
Uses predesigned logic cells known as
Standard cells
Standard cells are custom designed
and inserted into library
 Designer specifies the placement
of standard cells and interconnects on a CBIC
Main Features:
All mask layers are customized
Custom blocks are embedded
Manufacturing lead time is about eight weeks
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4.2.Types of ASIC’s contd.,
42
2. Semi Custom ASIC contd.,
 CBIC’S:

Standard cells can fit

together like a wall.
 Power line and GND run
Horizontally on metal lines inside
the cells

 Interconnections between logic cells

use spaces between rows of cells
called channels.

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4.2.Types of ASIC’s contd.,
43
2. Semi
Custom ASIC contd.,
 Advantage of Standard cell based ASIC:
Smaller, faster, and lower power chips than gate arrays
Higher productivity
High performance and flexibility
 Less design time
Minimum risk
Good for bottom up design
 Disadvantages:
 High expensive
Requires more time for fabrication
Wiring channels can exceed 50% of the internal chip

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4.2.Types of ASIC’s contd.,
44
2. Semi Custom ASIC contd.,
b. Gate array based ASIC:
 Transistors masks are completely predefined on the silicon wafer
 Smallest element used to form base array it is called Base cell or
Primitive cell
the interconnection between transistors is customized by using custom
masks it is called Masked Gate Array(MGA)
Macro:
The predesigned and Pre characterized logic cells are called Macros
Both cell based and Gate array based ASIC’s use predefined cells
But in standard cell transistor size optimized by using fixed size of

gate array. It is called Pre diffused array.

It uses to reduce the turn around time.

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4.2.Types of ASIC’s contd.,
45
2. Semi Custom ASIC contd.,
b. Gate array based ASIC:
 3 types
i. Channeled Gate Array
ii.Channelless Gate Array
iii.Structured Gate Array
a. Channeled Gate Array:
Gate array is channeled that is the space between the rows of
transistors
are wired
 Features:
Only the interconnect is customized
Interconnect uses predefined spaces
Manufacturing lead time is 2 days to 2 weeks
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4.2.Types of ASIC’s contd.,
46
2. Semi Custom ASIC contd.,
b. Gate array based ASIC:

b. Channelless Gate Array:

No predefined area for routing
Routing is done over the top of the gate

array devices
 Features:
Only some mask layers are customized
Manufacturing lead time is 2 days to 2 weeks

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4.2.Types of ASIC’s contd.,
47
2. Semi Custom ASIC contd.,
b. Gate array based ASIC:

c. Structured Gate Array:

MGA uses fixed gate array

base cell
Also known as Embedded

gate array or Master slice or

Master image
 This embedded block contains
different base cells
 Features:
Only the interconnect is customized
Custom blocks can be embedded
Manufacturing lead time is 2 days to 2 weeks
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 48

5. ASIC DESIGN FLOW

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5.1.ASIC Design flow:
49
 The sequence of steps to design an ASIC
which is called as Design Flow
i. Design Entry:
 Enter the design by using HDL or

schematic entry
ii. Logic Synthesis:
 To produce a netlist for logic cells and
their interconnections
iii. System Partitioning:
 Divide a large system into ASIC sized

Pieces. Main Goal to,

Partitioning a large system into small

Minimize the number of pins

Minimize Package cost

Minimize the external connections 12/24/2024

5.1.ASIC Design flow:
50
iv. Pre Layout Simulation:
 Verifying the function of the design

v. Floor Planning:
 Arrange the blocks of the netlist on the chip.

 The main Goal is,

 Arrange the blocks on a chip

 Decide the location of I/O pins
 Decide the location and number of power pads
 Decide the type of power distribution
 Decide the type and location of clock distribution
vi. Placement:
 Defines the location of logic cells within the flexible blocks

 The Goal is,

 Minimize the interconnect length

 Minimize power dissipation 12/24/2024
5.1.ASIC Design flow:
51
vii. Routing:
 Routing makes the connection between logic cells

viii.Extraction:
 After verifying the exact length and position of interconnect net, the

parasitic capacitance and resistance can be calculated,

 The data is generated by circuit extraction tool.

ix. Post Layout Simulation:

 Verifying the function of design still works with the added loads of the

interconnect.

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 52

6.AUTOMATIC TEST
PATTERN GENERATION
(ATPG)

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6.1.ATPG:
53
 The task of the ATPG process is to Determine a minimum set of excitation
vectors.
 It cover sufficient portion of the fault set as defined as the adopted model
 One possible approach is to start from a random set of test patterns
 Determine how many of the potential faults are detected.
 As guidance extra vectors can be added or removed

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6.1.ATPG contd.,
54
Consider this example, the goal is to determine the input excitation that
exposes an sa0 fault occurring at node U at the output of the network Z.
 U to be 1 under circumstances that is A=1 and B=1.
 The faulty signal is to propagate to output node Z, so that it can be observed.

It is called path sensitizing.

 Necessary for node X to be set to 1 and note E to 0. Then the unique test
vector for Usa0

A=B=C=D=1, E=0

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 55

7.DESIGN FOR
TESTABILITY

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7.1. Introduction:
56
 Key to designing the circuits
 Testable for both controllability and observability
 Controllability is the ablility to set(to 1) and reset (to 0) every node internal
to the circuit.
 Observability is the ability to observe either directly or indirectly, the state of
any node in the circuit
 Adding some extra logic circuit to reduce the test difficulty is known s
Testable circuit Design or Design of Testability (DFT)
 Good observability and Controllability reduces the cost of manufacturing
testing.
 DFT can be categorized as follows

i.Ad hoc testing

ii.Scan based approaches

iii.Built-In –Self test

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7.2.Ad hoc testing:
57
Collections of ideal aimed at reducing the combinational explosion of
testing
Useful for small designs where scan, ATPG, and BIST are not availble.

Complete scan based testing methodology

Used to increase both the observability and controlability

Common techniques are,

Partitioning large sequential circuits

Adding test points
Adding multiplexers
Providing for easy state reset
 TG multiplexers provide a low area and delay overhead
 It makes a testing easier and makes a simulation as faster.

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7.3. Scan Design:
58
Testing has evolved to provide observability and controlability at each
register
2 modes of operation:
Normal mode
Scan mode =>registers are connected to form a giant shift register. It spanning
the Whole chip
For N clock pulses in scan mode, N bits can be shifted out and shifted in.
Modern scan is based on the
use of scan registers
When scan is asserted data
Loaded from the Scan-In pin.
When Scan is deasserted and CLK
is asserted circuit operate with predefined
inputs
Test generation is highly automated

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7.3. Scan Design contd.,
59
 Serial scan becomes so long and loading and unloading dominate the
time.
7.3.1.Parallel Scan:
 Splitting the chains into smaller segments like module- by module
 Extending with this in serial scan process is known as Random access
scan
 Global write
signal connected to
all registers

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7.3. Scan Design contd.,
60
7.3.2.Scannable Register Design :
 Ordinary flip flop can be
made by scannable by adding a
Mux on the data input.
 Setup time increases by the
delay of extra transmission gate
 If a clock is enable, it is
used to stop the clock for an unused
portions of the chip.

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7.4.Built-In Self –Test(BIST)
61
BIST relies on augmenting logic circuits to allow them to carry out
operations upon themselves that prove the correct operations of the logic circuit
Add an area to the chip but reduces the test time and overall system cost

Method of testing:
Signature Analysis
Cyclic Redundancy check(CRC)
Both method are used Pseduo- Random Sequence Generator(PRSG) to
produce the input signals
Signature Analyzer for observe the output signals.
2 types of PRSG:
 Linear feedback Shift Register(LFSR)
 Described by Characteristics Polynomial which bits are fedback
 Complete Feedback Shift Register(CFSR)
 Converting LFSR to CFSR by adding a n-1 input NOR Gate

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7.4.Built-In Self –Test(BIST) contd.,
62

 In figure a=>LFSR
 In figure b=>CFSR

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7.4.Built-In Self –Test(BIST) contd.,
63

1.BIST:{BILBO}
 Built –In Logic Block Observation

 Combination of Signature Analysis

and Scan technique

 Scannable, Resettable Register

 4 operation modes

i. Scan mode (00)

FF’s configured as 3 bit shift register(SI&SO)

ii.Test mode(01)
Behaves as Random sequence generator

iii.Reset mode(10)
Synchronously initialized as 0

iv.Normal mode(11)
Behaves normally with their D input and Q output

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7.4.Built-In Self –Test(BIST) contd.,
64

2.Memory BIST:
 Multiplexers are placed on the address, data and control inputs
 While testing a state machine use this multiplexers to directly write a
checkerboard pattern of alternating 1s and 0s.
 Data is read back and checked, then the inverse pattern also applied and
checked
 ROM testing is very simpler

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7.4.Built-In Self –Test(BIST) contd.,
65

3.Other On-Chip Test strategies:

 On chip speed is high
 So internal behavior for testing can be difficult and an impossible

 So we use On-Chip Logic Analyzers and Oscilloscopes

 Also used to characterize

power supply noise and clock jitter

 In both DAC and ADC a

loop strategy can be employed

 Providing On-chip debug circuitry

involves a bit of imagination and

Forethrough in terms what go wrong.
it is known as “Defensive Design”

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7.5. IDDQ Testing:
66
 Method of testing for Bridging faults is called IDDQ test
 IDDQ test(VDD supply current Quiescent or supply current monitoring)
 If bridge fault occurs, a measurable DC current will flow
 Very sensitive
 Completed externally to the chip by measuring current drawn on VDD line.
 Gives a form of indirect massive observability

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7.6.Design for Manufacturability:
67
 Circuits can optimized to increase their yield.
 The different ways are
i. Physical:
By reducing the process defects yield and manufacturability is improved
Increasing the spacing between the wires

Reduces the short circuit defect

Increase the overlap of Layers around contacts and vias
 Reduce the misallignement
Increase the number of vias at wire intersections
 Reduce the open circuit defect

ii. Redundancy:
Used to Compensate the defective Components on a chip

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iii. Power:
 Elevated power can cause failure due to excess current in wires
 It causes Metal Migration Failures
 High power devices rise the Die temperature , it degrades the device

Performance
 Suitable package and Het Sink should be chosen to remove extra heat

iv.Process spread:
Carried out at different process corners
Monte Carlo Analysis can provide better modeling for process speed

v.Yield Analysis:
When a chip has poor yield, it fails the manufacturing test in lab.
Yield analysis used to locate the root cause of the failure
Then the layout structures can be redesigned

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8.SCAN TEST

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8.1.Scan Test:
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 Many system defects occur at Board level including Open or shorted PCB
traces
and incomplete solder joints
 “Bed – Of –Nails” Can be sensed(the observable points) and driven (the

controllable points) to test the complete board

 When a computer boots, run a memory

test to find a possible defects.

 For complex boards Surface Mount

Technologies are used.

 Boundary scan used for testing

chips at board and system level

 Originally developed by the Joint Test

Access Group(JTAG)
 All I/O pins are accessed through the Test Access Port(TAP)

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Thank You

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